xref: /OK3568_Linux_fs/kernel/drivers/media/platform/vsp1/vsp1_clu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * vsp1_clu.c  --  R-Car VSP1 Cubic Look-Up Table
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Renesas Electronics Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include "vsp1.h"
16*4882a593Smuzhiyun #include "vsp1_clu.h"
17*4882a593Smuzhiyun #include "vsp1_dl.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define CLU_MIN_SIZE				4U
20*4882a593Smuzhiyun #define CLU_MAX_SIZE				8190U
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define CLU_SIZE				(17 * 17 * 17)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
25*4882a593Smuzhiyun  * Device Access
26*4882a593Smuzhiyun  */
27*4882a593Smuzhiyun 
vsp1_clu_write(struct vsp1_clu * clu,struct vsp1_dl_body * dlb,u32 reg,u32 data)28*4882a593Smuzhiyun static inline void vsp1_clu_write(struct vsp1_clu *clu,
29*4882a593Smuzhiyun 				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun 	vsp1_dl_body_write(dlb, reg, data);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
35*4882a593Smuzhiyun  * Controls
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define V4L2_CID_VSP1_CLU_TABLE			(V4L2_CID_USER_BASE | 0x1001)
39*4882a593Smuzhiyun #define V4L2_CID_VSP1_CLU_MODE			(V4L2_CID_USER_BASE | 0x1002)
40*4882a593Smuzhiyun #define V4L2_CID_VSP1_CLU_MODE_2D		0
41*4882a593Smuzhiyun #define V4L2_CID_VSP1_CLU_MODE_3D		1
42*4882a593Smuzhiyun 
clu_set_table(struct vsp1_clu * clu,struct v4l2_ctrl * ctrl)43*4882a593Smuzhiyun static int clu_set_table(struct vsp1_clu *clu, struct v4l2_ctrl *ctrl)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	struct vsp1_dl_body *dlb;
46*4882a593Smuzhiyun 	unsigned int i;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	dlb = vsp1_dl_body_get(clu->pool);
49*4882a593Smuzhiyun 	if (!dlb)
50*4882a593Smuzhiyun 		return -ENOMEM;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
53*4882a593Smuzhiyun 	for (i = 0; i < CLU_SIZE; ++i)
54*4882a593Smuzhiyun 		vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	spin_lock_irq(&clu->lock);
57*4882a593Smuzhiyun 	swap(clu->clu, dlb);
58*4882a593Smuzhiyun 	spin_unlock_irq(&clu->lock);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	vsp1_dl_body_put(dlb);
61*4882a593Smuzhiyun 	return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
clu_s_ctrl(struct v4l2_ctrl * ctrl)64*4882a593Smuzhiyun static int clu_s_ctrl(struct v4l2_ctrl *ctrl)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	struct vsp1_clu *clu =
67*4882a593Smuzhiyun 		container_of(ctrl->handler, struct vsp1_clu, ctrls);
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	switch (ctrl->id) {
70*4882a593Smuzhiyun 	case V4L2_CID_VSP1_CLU_TABLE:
71*4882a593Smuzhiyun 		clu_set_table(clu, ctrl);
72*4882a593Smuzhiyun 		break;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	case V4L2_CID_VSP1_CLU_MODE:
75*4882a593Smuzhiyun 		clu->mode = ctrl->val;
76*4882a593Smuzhiyun 		break;
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static const struct v4l2_ctrl_ops clu_ctrl_ops = {
83*4882a593Smuzhiyun 	.s_ctrl = clu_s_ctrl,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static const struct v4l2_ctrl_config clu_table_control = {
87*4882a593Smuzhiyun 	.ops = &clu_ctrl_ops,
88*4882a593Smuzhiyun 	.id = V4L2_CID_VSP1_CLU_TABLE,
89*4882a593Smuzhiyun 	.name = "Look-Up Table",
90*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_U32,
91*4882a593Smuzhiyun 	.min = 0x00000000,
92*4882a593Smuzhiyun 	.max = 0x00ffffff,
93*4882a593Smuzhiyun 	.step = 1,
94*4882a593Smuzhiyun 	.def = 0,
95*4882a593Smuzhiyun 	.dims = { 17, 17, 17 },
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static const char * const clu_mode_menu[] = {
99*4882a593Smuzhiyun 	"2D",
100*4882a593Smuzhiyun 	"3D",
101*4882a593Smuzhiyun 	NULL,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static const struct v4l2_ctrl_config clu_mode_control = {
105*4882a593Smuzhiyun 	.ops = &clu_ctrl_ops,
106*4882a593Smuzhiyun 	.id = V4L2_CID_VSP1_CLU_MODE,
107*4882a593Smuzhiyun 	.name = "Mode",
108*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_MENU,
109*4882a593Smuzhiyun 	.min = 0,
110*4882a593Smuzhiyun 	.max = 1,
111*4882a593Smuzhiyun 	.def = 1,
112*4882a593Smuzhiyun 	.qmenu = clu_mode_menu,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
116*4882a593Smuzhiyun  * V4L2 Subdevice Pad Operations
117*4882a593Smuzhiyun  */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static const unsigned int clu_codes[] = {
120*4882a593Smuzhiyun 	MEDIA_BUS_FMT_ARGB8888_1X32,
121*4882a593Smuzhiyun 	MEDIA_BUS_FMT_AHSV8888_1X32,
122*4882a593Smuzhiyun 	MEDIA_BUS_FMT_AYUV8_1X32,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
clu_enum_mbus_code(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)125*4882a593Smuzhiyun static int clu_enum_mbus_code(struct v4l2_subdev *subdev,
126*4882a593Smuzhiyun 			      struct v4l2_subdev_pad_config *cfg,
127*4882a593Smuzhiyun 			      struct v4l2_subdev_mbus_code_enum *code)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	return vsp1_subdev_enum_mbus_code(subdev, cfg, code, clu_codes,
130*4882a593Smuzhiyun 					  ARRAY_SIZE(clu_codes));
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
clu_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)133*4882a593Smuzhiyun static int clu_enum_frame_size(struct v4l2_subdev *subdev,
134*4882a593Smuzhiyun 			       struct v4l2_subdev_pad_config *cfg,
135*4882a593Smuzhiyun 			       struct v4l2_subdev_frame_size_enum *fse)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	return vsp1_subdev_enum_frame_size(subdev, cfg, fse, CLU_MIN_SIZE,
138*4882a593Smuzhiyun 					   CLU_MIN_SIZE, CLU_MAX_SIZE,
139*4882a593Smuzhiyun 					   CLU_MAX_SIZE);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
clu_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)142*4882a593Smuzhiyun static int clu_set_format(struct v4l2_subdev *subdev,
143*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
144*4882a593Smuzhiyun 			  struct v4l2_subdev_format *fmt)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	return vsp1_subdev_set_pad_format(subdev, cfg, fmt, clu_codes,
147*4882a593Smuzhiyun 					  ARRAY_SIZE(clu_codes),
148*4882a593Smuzhiyun 					  CLU_MIN_SIZE, CLU_MIN_SIZE,
149*4882a593Smuzhiyun 					  CLU_MAX_SIZE, CLU_MAX_SIZE);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
153*4882a593Smuzhiyun  * V4L2 Subdevice Operations
154*4882a593Smuzhiyun  */
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops clu_pad_ops = {
157*4882a593Smuzhiyun 	.init_cfg = vsp1_entity_init_cfg,
158*4882a593Smuzhiyun 	.enum_mbus_code = clu_enum_mbus_code,
159*4882a593Smuzhiyun 	.enum_frame_size = clu_enum_frame_size,
160*4882a593Smuzhiyun 	.get_fmt = vsp1_subdev_get_pad_format,
161*4882a593Smuzhiyun 	.set_fmt = clu_set_format,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun static const struct v4l2_subdev_ops clu_ops = {
165*4882a593Smuzhiyun 	.pad    = &clu_pad_ops,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
169*4882a593Smuzhiyun  * VSP1 Entity Operations
170*4882a593Smuzhiyun  */
171*4882a593Smuzhiyun 
clu_configure_stream(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,struct vsp1_dl_body * dlb)172*4882a593Smuzhiyun static void clu_configure_stream(struct vsp1_entity *entity,
173*4882a593Smuzhiyun 				 struct vsp1_pipeline *pipe,
174*4882a593Smuzhiyun 				 struct vsp1_dl_list *dl,
175*4882a593Smuzhiyun 				 struct vsp1_dl_body *dlb)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct vsp1_clu *clu = to_clu(&entity->subdev);
178*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *format;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/*
181*4882a593Smuzhiyun 	 * The yuv_mode can't be changed during streaming. Cache it internally
182*4882a593Smuzhiyun 	 * for future runtime configuration calls.
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	format = vsp1_entity_get_pad_format(&clu->entity,
185*4882a593Smuzhiyun 					    clu->entity.config,
186*4882a593Smuzhiyun 					    CLU_PAD_SINK);
187*4882a593Smuzhiyun 	clu->yuv_mode = format->code == MEDIA_BUS_FMT_AYUV8_1X32;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
clu_configure_frame(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,struct vsp1_dl_body * dlb)190*4882a593Smuzhiyun static void clu_configure_frame(struct vsp1_entity *entity,
191*4882a593Smuzhiyun 				struct vsp1_pipeline *pipe,
192*4882a593Smuzhiyun 				struct vsp1_dl_list *dl,
193*4882a593Smuzhiyun 				struct vsp1_dl_body *dlb)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct vsp1_clu *clu = to_clu(&entity->subdev);
196*4882a593Smuzhiyun 	struct vsp1_dl_body *clu_dlb;
197*4882a593Smuzhiyun 	unsigned long flags;
198*4882a593Smuzhiyun 	u32 ctrl = VI6_CLU_CTRL_AAI | VI6_CLU_CTRL_MVS | VI6_CLU_CTRL_EN;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* 2D mode can only be used with the YCbCr pixel encoding. */
201*4882a593Smuzhiyun 	if (clu->mode == V4L2_CID_VSP1_CLU_MODE_2D && clu->yuv_mode)
202*4882a593Smuzhiyun 		ctrl |= VI6_CLU_CTRL_AX1I_2D | VI6_CLU_CTRL_AX2I_2D
203*4882a593Smuzhiyun 		     |  VI6_CLU_CTRL_OS0_2D | VI6_CLU_CTRL_OS1_2D
204*4882a593Smuzhiyun 		     |  VI6_CLU_CTRL_OS2_2D | VI6_CLU_CTRL_M2D;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	vsp1_clu_write(clu, dlb, VI6_CLU_CTRL, ctrl);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	spin_lock_irqsave(&clu->lock, flags);
209*4882a593Smuzhiyun 	clu_dlb = clu->clu;
210*4882a593Smuzhiyun 	clu->clu = NULL;
211*4882a593Smuzhiyun 	spin_unlock_irqrestore(&clu->lock, flags);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	if (clu_dlb) {
214*4882a593Smuzhiyun 		vsp1_dl_list_add_body(dl, clu_dlb);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 		/* Release our local reference. */
217*4882a593Smuzhiyun 		vsp1_dl_body_put(clu_dlb);
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
clu_destroy(struct vsp1_entity * entity)221*4882a593Smuzhiyun static void clu_destroy(struct vsp1_entity *entity)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	struct vsp1_clu *clu = to_clu(&entity->subdev);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	vsp1_dl_body_pool_destroy(clu->pool);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static const struct vsp1_entity_operations clu_entity_ops = {
229*4882a593Smuzhiyun 	.configure_stream = clu_configure_stream,
230*4882a593Smuzhiyun 	.configure_frame = clu_configure_frame,
231*4882a593Smuzhiyun 	.destroy = clu_destroy,
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
235*4882a593Smuzhiyun  * Initialization and Cleanup
236*4882a593Smuzhiyun  */
237*4882a593Smuzhiyun 
vsp1_clu_create(struct vsp1_device * vsp1)238*4882a593Smuzhiyun struct vsp1_clu *vsp1_clu_create(struct vsp1_device *vsp1)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun 	struct vsp1_clu *clu;
241*4882a593Smuzhiyun 	int ret;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	clu = devm_kzalloc(vsp1->dev, sizeof(*clu), GFP_KERNEL);
244*4882a593Smuzhiyun 	if (clu == NULL)
245*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	spin_lock_init(&clu->lock);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	clu->entity.ops = &clu_entity_ops;
250*4882a593Smuzhiyun 	clu->entity.type = VSP1_ENTITY_CLU;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	ret = vsp1_entity_init(vsp1, &clu->entity, "clu", 2, &clu_ops,
253*4882a593Smuzhiyun 			       MEDIA_ENT_F_PROC_VIDEO_LUT);
254*4882a593Smuzhiyun 	if (ret < 0)
255*4882a593Smuzhiyun 		return ERR_PTR(ret);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/*
258*4882a593Smuzhiyun 	 * Pre-allocate a body pool, with 3 bodies allowing a userspace update
259*4882a593Smuzhiyun 	 * before the hardware has committed a previous set of tables, handling
260*4882a593Smuzhiyun 	 * both the queued and pending dl entries. One extra entry is added to
261*4882a593Smuzhiyun 	 * the CLU_SIZE to allow for the VI6_CLU_ADDR header.
262*4882a593Smuzhiyun 	 */
263*4882a593Smuzhiyun 	clu->pool = vsp1_dl_body_pool_create(clu->entity.vsp1, 3, CLU_SIZE + 1,
264*4882a593Smuzhiyun 					     0);
265*4882a593Smuzhiyun 	if (!clu->pool)
266*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/* Initialize the control handler. */
269*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&clu->ctrls, 2);
270*4882a593Smuzhiyun 	v4l2_ctrl_new_custom(&clu->ctrls, &clu_table_control, NULL);
271*4882a593Smuzhiyun 	v4l2_ctrl_new_custom(&clu->ctrls, &clu_mode_control, NULL);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	clu->entity.subdev.ctrl_handler = &clu->ctrls;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	if (clu->ctrls.error) {
276*4882a593Smuzhiyun 		dev_err(vsp1->dev, "clu: failed to initialize controls\n");
277*4882a593Smuzhiyun 		ret = clu->ctrls.error;
278*4882a593Smuzhiyun 		vsp1_entity_destroy(&clu->entity);
279*4882a593Smuzhiyun 		return ERR_PTR(ret);
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	v4l2_ctrl_handler_setup(&clu->ctrls);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	return clu;
285*4882a593Smuzhiyun }
286