xref: /OK3568_Linux_fs/kernel/drivers/media/platform/ti-vpe/cal.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * TI Camera Access Layer (CAL)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2015-2020 Texas Instruments Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Authors:
8*4882a593Smuzhiyun  *	Benoit Parrot <bparrot@ti.com>
9*4882a593Smuzhiyun  *	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #ifndef __TI_CAL_H__
12*4882a593Smuzhiyun #define __TI_CAL_H__
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/bitfield.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/list.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <linux/spinlock.h>
19*4882a593Smuzhiyun #include <linux/videodev2.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <media/media-device.h>
22*4882a593Smuzhiyun #include <media/v4l2-async.h>
23*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
24*4882a593Smuzhiyun #include <media/v4l2-dev.h>
25*4882a593Smuzhiyun #include <media/v4l2-device.h>
26*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
27*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define CAL_MODULE_NAME			"cal"
30*4882a593Smuzhiyun #define CAL_NUM_CONTEXT			2
31*4882a593Smuzhiyun #define CAL_NUM_CSI2_PORTS		2
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MAX_WIDTH_BYTES			(8192 * 8)
34*4882a593Smuzhiyun #define MAX_HEIGHT_LINES		16383
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun struct device;
37*4882a593Smuzhiyun struct device_node;
38*4882a593Smuzhiyun struct resource;
39*4882a593Smuzhiyun struct regmap;
40*4882a593Smuzhiyun struct regmap_fied;
41*4882a593Smuzhiyun struct v4l2_subdev;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* CTRL_CORE_CAMERRX_CONTROL register field id */
44*4882a593Smuzhiyun enum cal_camerarx_field {
45*4882a593Smuzhiyun 	F_CTRLCLKEN,
46*4882a593Smuzhiyun 	F_CAMMODE,
47*4882a593Smuzhiyun 	F_LANEENABLE,
48*4882a593Smuzhiyun 	F_CSI_MODE,
49*4882a593Smuzhiyun 	F_MAX_FIELDS,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct cal_fmt {
53*4882a593Smuzhiyun 	u32	fourcc;
54*4882a593Smuzhiyun 	u32	code;
55*4882a593Smuzhiyun 	/* Bits per pixel */
56*4882a593Smuzhiyun 	u8	bpp;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* buffer for one video frame */
60*4882a593Smuzhiyun struct cal_buffer {
61*4882a593Smuzhiyun 	/* common v4l buffer stuff -- must be first */
62*4882a593Smuzhiyun 	struct vb2_v4l2_buffer	vb;
63*4882a593Smuzhiyun 	struct list_head	list;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun struct cal_dmaqueue {
67*4882a593Smuzhiyun 	struct list_head	active;
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct cal_camerarx_data {
71*4882a593Smuzhiyun 	struct {
72*4882a593Smuzhiyun 		unsigned int lsb;
73*4882a593Smuzhiyun 		unsigned int msb;
74*4882a593Smuzhiyun 	} fields[F_MAX_FIELDS];
75*4882a593Smuzhiyun 	unsigned int num_lanes;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun struct cal_data {
79*4882a593Smuzhiyun 	const struct cal_camerarx_data *camerarx;
80*4882a593Smuzhiyun 	unsigned int num_csi2_phy;
81*4882a593Smuzhiyun 	unsigned int flags;
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun  * The Camera Adaptation Layer (CAL) module is paired with one or more complex
86*4882a593Smuzhiyun  * I/O PHYs (CAMERARX). It contains multiple instances of CSI-2, processing and
87*4882a593Smuzhiyun  * DMA contexts.
88*4882a593Smuzhiyun  *
89*4882a593Smuzhiyun  * The cal_dev structure represents the whole subsystem, including the CAL and
90*4882a593Smuzhiyun  * the CAMERARX instances. Instances of struct cal_dev are named cal through the
91*4882a593Smuzhiyun  * driver.
92*4882a593Smuzhiyun  *
93*4882a593Smuzhiyun  * The cal_camerarx structure represents one CAMERARX instance. Instances of
94*4882a593Smuzhiyun  * cal_camerarx are named phy through the driver.
95*4882a593Smuzhiyun  *
96*4882a593Smuzhiyun  * The cal_ctx structure represents the combination of one CSI-2 context, one
97*4882a593Smuzhiyun  * processing context and one DMA context. Instance of struct cal_ctx are named
98*4882a593Smuzhiyun  * ctx through the driver.
99*4882a593Smuzhiyun  */
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct cal_camerarx {
102*4882a593Smuzhiyun 	void __iomem		*base;
103*4882a593Smuzhiyun 	struct resource		*res;
104*4882a593Smuzhiyun 	struct device		*dev;
105*4882a593Smuzhiyun 	struct regmap_field	*fields[F_MAX_FIELDS];
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	struct cal_dev		*cal;
108*4882a593Smuzhiyun 	unsigned int		instance;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint	endpoint;
111*4882a593Smuzhiyun 	struct device_node	*sensor_node;
112*4882a593Smuzhiyun 	struct v4l2_subdev	*sensor;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct cal_dev {
116*4882a593Smuzhiyun 	struct clk		*fclk;
117*4882a593Smuzhiyun 	int			irq;
118*4882a593Smuzhiyun 	void __iomem		*base;
119*4882a593Smuzhiyun 	struct resource		*res;
120*4882a593Smuzhiyun 	struct device		*dev;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	const struct cal_data	*data;
123*4882a593Smuzhiyun 	u32			revision;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	/* Control Module handle */
126*4882a593Smuzhiyun 	struct regmap		*syscon_camerrx;
127*4882a593Smuzhiyun 	u32			syscon_camerrx_offset;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* Camera Core Module handle */
130*4882a593Smuzhiyun 	struct cal_camerarx	*phy[CAL_NUM_CSI2_PORTS];
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	struct cal_ctx		*ctx[CAL_NUM_CONTEXT];
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	struct media_device	mdev;
135*4882a593Smuzhiyun 	struct v4l2_device	v4l2_dev;
136*4882a593Smuzhiyun 	struct v4l2_async_notifier notifier;
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun  * There is one cal_ctx structure for each camera core context.
141*4882a593Smuzhiyun  */
142*4882a593Smuzhiyun struct cal_ctx {
143*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
144*4882a593Smuzhiyun 	struct video_device	vdev;
145*4882a593Smuzhiyun 	struct media_pad	pad;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	struct cal_dev		*cal;
148*4882a593Smuzhiyun 	struct cal_camerarx	*phy;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/* v4l2_ioctl mutex */
151*4882a593Smuzhiyun 	struct mutex		mutex;
152*4882a593Smuzhiyun 	/* v4l2 buffers lock */
153*4882a593Smuzhiyun 	spinlock_t		slock;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	struct cal_dmaqueue	vidq;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* video capture */
158*4882a593Smuzhiyun 	const struct cal_fmt	*fmt;
159*4882a593Smuzhiyun 	/* Used to store current pixel format */
160*4882a593Smuzhiyun 	struct v4l2_format		v_fmt;
161*4882a593Smuzhiyun 	/* Used to store current mbus frame format */
162*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt	m_fmt;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* Current subdev enumerated format */
165*4882a593Smuzhiyun 	const struct cal_fmt	**active_fmt;
166*4882a593Smuzhiyun 	unsigned int		num_active_fmt;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	unsigned int		sequence;
169*4882a593Smuzhiyun 	struct vb2_queue	vb_vidq;
170*4882a593Smuzhiyun 	unsigned int		index;
171*4882a593Smuzhiyun 	unsigned int		cport;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* Pointer pointing to current v4l2_buffer */
174*4882a593Smuzhiyun 	struct cal_buffer	*cur_frm;
175*4882a593Smuzhiyun 	/* Pointer pointing to next v4l2_buffer */
176*4882a593Smuzhiyun 	struct cal_buffer	*next_frm;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	bool dma_act;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun extern unsigned int cal_debug;
182*4882a593Smuzhiyun extern int cal_video_nr;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #define cal_dbg(level, cal, fmt, arg...)				\
185*4882a593Smuzhiyun 	do {								\
186*4882a593Smuzhiyun 		if (cal_debug >= (level))				\
187*4882a593Smuzhiyun 			dev_printk(KERN_DEBUG, (cal)->dev, fmt, ##arg);	\
188*4882a593Smuzhiyun 	} while (0)
189*4882a593Smuzhiyun #define cal_info(cal, fmt, arg...)					\
190*4882a593Smuzhiyun 	dev_info((cal)->dev, fmt, ##arg)
191*4882a593Smuzhiyun #define cal_err(cal, fmt, arg...)					\
192*4882a593Smuzhiyun 	dev_err((cal)->dev, fmt, ##arg)
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #define ctx_dbg(level, ctx, fmt, arg...)				\
195*4882a593Smuzhiyun 	cal_dbg(level, (ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
196*4882a593Smuzhiyun #define ctx_info(ctx, fmt, arg...)					\
197*4882a593Smuzhiyun 	cal_info((ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
198*4882a593Smuzhiyun #define ctx_err(ctx, fmt, arg...)					\
199*4882a593Smuzhiyun 	cal_err((ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun #define phy_dbg(level, phy, fmt, arg...)				\
202*4882a593Smuzhiyun 	cal_dbg(level, (phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
203*4882a593Smuzhiyun #define phy_info(phy, fmt, arg...)					\
204*4882a593Smuzhiyun 	cal_info((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
205*4882a593Smuzhiyun #define phy_err(phy, fmt, arg...)					\
206*4882a593Smuzhiyun 	cal_err((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
207*4882a593Smuzhiyun 
cal_read(struct cal_dev * cal,u32 offset)208*4882a593Smuzhiyun static inline u32 cal_read(struct cal_dev *cal, u32 offset)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	return ioread32(cal->base + offset);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun 
cal_write(struct cal_dev * cal,u32 offset,u32 val)213*4882a593Smuzhiyun static inline void cal_write(struct cal_dev *cal, u32 offset, u32 val)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	iowrite32(val, cal->base + offset);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
cal_read_field(struct cal_dev * cal,u32 offset,u32 mask)218*4882a593Smuzhiyun static inline u32 cal_read_field(struct cal_dev *cal, u32 offset, u32 mask)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	return FIELD_GET(mask, cal_read(cal, offset));
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
cal_write_field(struct cal_dev * cal,u32 offset,u32 value,u32 mask)223*4882a593Smuzhiyun static inline void cal_write_field(struct cal_dev *cal, u32 offset, u32 value,
224*4882a593Smuzhiyun 				   u32 mask)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	u32 val = cal_read(cal, offset);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	val &= ~mask;
229*4882a593Smuzhiyun 	val |= (value << __ffs(mask)) & mask;
230*4882a593Smuzhiyun 	cal_write(cal, offset, val);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
cal_set_field(u32 * valp,u32 field,u32 mask)233*4882a593Smuzhiyun static inline void cal_set_field(u32 *valp, u32 field, u32 mask)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	u32 val = *valp;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	val &= ~mask;
238*4882a593Smuzhiyun 	val |= (field << __ffs(mask)) & mask;
239*4882a593Smuzhiyun 	*valp = val;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun void cal_quickdump_regs(struct cal_dev *cal);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun void cal_camerarx_disable(struct cal_camerarx *phy);
245*4882a593Smuzhiyun int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt);
246*4882a593Smuzhiyun void cal_camerarx_stop(struct cal_camerarx *phy);
247*4882a593Smuzhiyun void cal_camerarx_enable_irqs(struct cal_camerarx *phy);
248*4882a593Smuzhiyun void cal_camerarx_disable_irqs(struct cal_camerarx *phy);
249*4882a593Smuzhiyun void cal_camerarx_ppi_enable(struct cal_camerarx *phy);
250*4882a593Smuzhiyun void cal_camerarx_ppi_disable(struct cal_camerarx *phy);
251*4882a593Smuzhiyun void cal_camerarx_i913_errata(struct cal_camerarx *phy);
252*4882a593Smuzhiyun struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
253*4882a593Smuzhiyun 					 unsigned int instance);
254*4882a593Smuzhiyun void cal_camerarx_destroy(struct cal_camerarx *phy);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun void cal_ctx_csi2_config(struct cal_ctx *ctx);
257*4882a593Smuzhiyun void cal_ctx_pix_proc_config(struct cal_ctx *ctx);
258*4882a593Smuzhiyun void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width,
259*4882a593Smuzhiyun 			   unsigned int height);
260*4882a593Smuzhiyun void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun int cal_ctx_v4l2_register(struct cal_ctx *ctx);
263*4882a593Smuzhiyun void cal_ctx_v4l2_unregister(struct cal_ctx *ctx);
264*4882a593Smuzhiyun int cal_ctx_v4l2_init(struct cal_ctx *ctx);
265*4882a593Smuzhiyun void cal_ctx_v4l2_cleanup(struct cal_ctx *ctx);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun #endif /* __TI_CAL_H__ */
268