xref: /OK3568_Linux_fs/kernel/drivers/media/platform/stm32/stm32-dcmi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for STM32 Digital Camera Memory Interface
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) STMicroelectronics SA 2017
6*4882a593Smuzhiyun  * Authors: Yannick Fertre <yannick.fertre@st.com>
7*4882a593Smuzhiyun  *          Hugues Fruchet <hugues.fruchet@st.com>
8*4882a593Smuzhiyun  *          for STMicroelectronics.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * This driver is based on atmel_isi.c
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/completion.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/dmaengine.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/of.h>
23*4882a593Smuzhiyun #include <linux/of_device.h>
24*4882a593Smuzhiyun #include <linux/of_graph.h>
25*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
26*4882a593Smuzhiyun #include <linux/platform_device.h>
27*4882a593Smuzhiyun #include <linux/pm_runtime.h>
28*4882a593Smuzhiyun #include <linux/reset.h>
29*4882a593Smuzhiyun #include <linux/videodev2.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
32*4882a593Smuzhiyun #include <media/v4l2-dev.h>
33*4882a593Smuzhiyun #include <media/v4l2-device.h>
34*4882a593Smuzhiyun #include <media/v4l2-event.h>
35*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
36*4882a593Smuzhiyun #include <media/v4l2-image-sizes.h>
37*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
38*4882a593Smuzhiyun #include <media/v4l2-rect.h>
39*4882a593Smuzhiyun #include <media/videobuf2-dma-contig.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define DRV_NAME "stm32-dcmi"
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* Registers offset for DCMI */
44*4882a593Smuzhiyun #define DCMI_CR		0x00 /* Control Register */
45*4882a593Smuzhiyun #define DCMI_SR		0x04 /* Status Register */
46*4882a593Smuzhiyun #define DCMI_RIS	0x08 /* Raw Interrupt Status register */
47*4882a593Smuzhiyun #define DCMI_IER	0x0C /* Interrupt Enable Register */
48*4882a593Smuzhiyun #define DCMI_MIS	0x10 /* Masked Interrupt Status register */
49*4882a593Smuzhiyun #define DCMI_ICR	0x14 /* Interrupt Clear Register */
50*4882a593Smuzhiyun #define DCMI_ESCR	0x18 /* Embedded Synchronization Code Register */
51*4882a593Smuzhiyun #define DCMI_ESUR	0x1C /* Embedded Synchronization Unmask Register */
52*4882a593Smuzhiyun #define DCMI_CWSTRT	0x20 /* Crop Window STaRT */
53*4882a593Smuzhiyun #define DCMI_CWSIZE	0x24 /* Crop Window SIZE */
54*4882a593Smuzhiyun #define DCMI_DR		0x28 /* Data Register */
55*4882a593Smuzhiyun #define DCMI_IDR	0x2C /* IDentifier Register */
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* Bits definition for control register (DCMI_CR) */
58*4882a593Smuzhiyun #define CR_CAPTURE	BIT(0)
59*4882a593Smuzhiyun #define CR_CM		BIT(1)
60*4882a593Smuzhiyun #define CR_CROP		BIT(2)
61*4882a593Smuzhiyun #define CR_JPEG		BIT(3)
62*4882a593Smuzhiyun #define CR_ESS		BIT(4)
63*4882a593Smuzhiyun #define CR_PCKPOL	BIT(5)
64*4882a593Smuzhiyun #define CR_HSPOL	BIT(6)
65*4882a593Smuzhiyun #define CR_VSPOL	BIT(7)
66*4882a593Smuzhiyun #define CR_FCRC_0	BIT(8)
67*4882a593Smuzhiyun #define CR_FCRC_1	BIT(9)
68*4882a593Smuzhiyun #define CR_EDM_0	BIT(10)
69*4882a593Smuzhiyun #define CR_EDM_1	BIT(11)
70*4882a593Smuzhiyun #define CR_ENABLE	BIT(14)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* Bits definition for status register (DCMI_SR) */
73*4882a593Smuzhiyun #define SR_HSYNC	BIT(0)
74*4882a593Smuzhiyun #define SR_VSYNC	BIT(1)
75*4882a593Smuzhiyun #define SR_FNE		BIT(2)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun  * Bits definition for interrupt registers
79*4882a593Smuzhiyun  * (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR)
80*4882a593Smuzhiyun  */
81*4882a593Smuzhiyun #define IT_FRAME	BIT(0)
82*4882a593Smuzhiyun #define IT_OVR		BIT(1)
83*4882a593Smuzhiyun #define IT_ERR		BIT(2)
84*4882a593Smuzhiyun #define IT_VSYNC	BIT(3)
85*4882a593Smuzhiyun #define IT_LINE		BIT(4)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun enum state {
88*4882a593Smuzhiyun 	STOPPED = 0,
89*4882a593Smuzhiyun 	WAIT_FOR_BUFFER,
90*4882a593Smuzhiyun 	RUNNING,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define MIN_WIDTH	16U
94*4882a593Smuzhiyun #define MAX_WIDTH	2592U
95*4882a593Smuzhiyun #define MIN_HEIGHT	16U
96*4882a593Smuzhiyun #define MAX_HEIGHT	2592U
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define TIMEOUT_MS	1000
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define OVERRUN_ERROR_THRESHOLD	3
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun struct dcmi_graph_entity {
103*4882a593Smuzhiyun 	struct v4l2_async_subdev asd;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	struct device_node *remote_node;
106*4882a593Smuzhiyun 	struct v4l2_subdev *source;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun struct dcmi_format {
110*4882a593Smuzhiyun 	u32	fourcc;
111*4882a593Smuzhiyun 	u32	mbus_code;
112*4882a593Smuzhiyun 	u8	bpp;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct dcmi_framesize {
116*4882a593Smuzhiyun 	u32	width;
117*4882a593Smuzhiyun 	u32	height;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun struct dcmi_buf {
121*4882a593Smuzhiyun 	struct vb2_v4l2_buffer	vb;
122*4882a593Smuzhiyun 	bool			prepared;
123*4882a593Smuzhiyun 	dma_addr_t		paddr;
124*4882a593Smuzhiyun 	size_t			size;
125*4882a593Smuzhiyun 	struct list_head	list;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun struct stm32_dcmi {
129*4882a593Smuzhiyun 	/* Protects the access of variables shared within the interrupt */
130*4882a593Smuzhiyun 	spinlock_t			irqlock;
131*4882a593Smuzhiyun 	struct device			*dev;
132*4882a593Smuzhiyun 	void __iomem			*regs;
133*4882a593Smuzhiyun 	struct resource			*res;
134*4882a593Smuzhiyun 	struct reset_control		*rstc;
135*4882a593Smuzhiyun 	int				sequence;
136*4882a593Smuzhiyun 	struct list_head		buffers;
137*4882a593Smuzhiyun 	struct dcmi_buf			*active;
138*4882a593Smuzhiyun 	int			irq;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	struct v4l2_device		v4l2_dev;
141*4882a593Smuzhiyun 	struct video_device		*vdev;
142*4882a593Smuzhiyun 	struct v4l2_async_notifier	notifier;
143*4882a593Smuzhiyun 	struct dcmi_graph_entity	entity;
144*4882a593Smuzhiyun 	struct v4l2_format		fmt;
145*4882a593Smuzhiyun 	struct v4l2_rect		crop;
146*4882a593Smuzhiyun 	bool				do_crop;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	const struct dcmi_format	**sd_formats;
149*4882a593Smuzhiyun 	unsigned int			num_of_sd_formats;
150*4882a593Smuzhiyun 	const struct dcmi_format	*sd_format;
151*4882a593Smuzhiyun 	struct dcmi_framesize		*sd_framesizes;
152*4882a593Smuzhiyun 	unsigned int			num_of_sd_framesizes;
153*4882a593Smuzhiyun 	struct dcmi_framesize		sd_framesize;
154*4882a593Smuzhiyun 	struct v4l2_rect		sd_bounds;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* Protect this data structure */
157*4882a593Smuzhiyun 	struct mutex			lock;
158*4882a593Smuzhiyun 	struct vb2_queue		queue;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	struct v4l2_fwnode_bus_parallel	bus;
161*4882a593Smuzhiyun 	struct completion		complete;
162*4882a593Smuzhiyun 	struct clk			*mclk;
163*4882a593Smuzhiyun 	enum state			state;
164*4882a593Smuzhiyun 	struct dma_chan			*dma_chan;
165*4882a593Smuzhiyun 	dma_cookie_t			dma_cookie;
166*4882a593Smuzhiyun 	u32				misr;
167*4882a593Smuzhiyun 	int				errors_count;
168*4882a593Smuzhiyun 	int				overrun_count;
169*4882a593Smuzhiyun 	int				buffers_count;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	/* Ensure DMA operations atomicity */
172*4882a593Smuzhiyun 	struct mutex			dma_lock;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	struct media_device		mdev;
175*4882a593Smuzhiyun 	struct media_pad		vid_cap_pad;
176*4882a593Smuzhiyun 	struct media_pipeline		pipeline;
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
notifier_to_dcmi(struct v4l2_async_notifier * n)179*4882a593Smuzhiyun static inline struct stm32_dcmi *notifier_to_dcmi(struct v4l2_async_notifier *n)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	return container_of(n, struct stm32_dcmi, notifier);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
reg_read(void __iomem * base,u32 reg)184*4882a593Smuzhiyun static inline u32 reg_read(void __iomem *base, u32 reg)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	return readl_relaxed(base + reg);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
reg_write(void __iomem * base,u32 reg,u32 val)189*4882a593Smuzhiyun static inline void reg_write(void __iomem *base, u32 reg, u32 val)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	writel_relaxed(val, base + reg);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
reg_set(void __iomem * base,u32 reg,u32 mask)194*4882a593Smuzhiyun static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	reg_write(base, reg, reg_read(base, reg) | mask);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
reg_clear(void __iomem * base,u32 reg,u32 mask)199*4882a593Smuzhiyun static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	reg_write(base, reg, reg_read(base, reg) & ~mask);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf);
205*4882a593Smuzhiyun 
dcmi_buffer_done(struct stm32_dcmi * dcmi,struct dcmi_buf * buf,size_t bytesused,int err)206*4882a593Smuzhiyun static void dcmi_buffer_done(struct stm32_dcmi *dcmi,
207*4882a593Smuzhiyun 			     struct dcmi_buf *buf,
208*4882a593Smuzhiyun 			     size_t bytesused,
209*4882a593Smuzhiyun 			     int err)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	if (!buf)
214*4882a593Smuzhiyun 		return;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	list_del_init(&buf->list);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	vbuf = &buf->vb;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	vbuf->sequence = dcmi->sequence++;
221*4882a593Smuzhiyun 	vbuf->field = V4L2_FIELD_NONE;
222*4882a593Smuzhiyun 	vbuf->vb2_buf.timestamp = ktime_get_ns();
223*4882a593Smuzhiyun 	vb2_set_plane_payload(&vbuf->vb2_buf, 0, bytesused);
224*4882a593Smuzhiyun 	vb2_buffer_done(&vbuf->vb2_buf,
225*4882a593Smuzhiyun 			err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
226*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "buffer[%d] done seq=%d, bytesused=%zu\n",
227*4882a593Smuzhiyun 		vbuf->vb2_buf.index, vbuf->sequence, bytesused);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	dcmi->buffers_count++;
230*4882a593Smuzhiyun 	dcmi->active = NULL;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
dcmi_restart_capture(struct stm32_dcmi * dcmi)233*4882a593Smuzhiyun static int dcmi_restart_capture(struct stm32_dcmi *dcmi)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	struct dcmi_buf *buf;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	if (dcmi->state != RUNNING) {
240*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
241*4882a593Smuzhiyun 		return -EINVAL;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* Restart a new DMA transfer with next buffer */
245*4882a593Smuzhiyun 	if (list_empty(&dcmi->buffers)) {
246*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n");
247*4882a593Smuzhiyun 		dcmi->state = WAIT_FOR_BUFFER;
248*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
249*4882a593Smuzhiyun 		return 0;
250*4882a593Smuzhiyun 	}
251*4882a593Smuzhiyun 	buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
252*4882a593Smuzhiyun 	dcmi->active = buf;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	return dcmi_start_capture(dcmi, buf);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
dcmi_dma_callback(void * param)259*4882a593Smuzhiyun static void dcmi_dma_callback(void *param)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param;
262*4882a593Smuzhiyun 	struct dma_tx_state state;
263*4882a593Smuzhiyun 	enum dma_status status;
264*4882a593Smuzhiyun 	struct dcmi_buf *buf = dcmi->active;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/* Check DMA status */
269*4882a593Smuzhiyun 	status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	switch (status) {
272*4882a593Smuzhiyun 	case DMA_IN_PROGRESS:
273*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__);
274*4882a593Smuzhiyun 		break;
275*4882a593Smuzhiyun 	case DMA_PAUSED:
276*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__);
277*4882a593Smuzhiyun 		break;
278*4882a593Smuzhiyun 	case DMA_ERROR:
279*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 		/* Return buffer to V4L2 in error state */
282*4882a593Smuzhiyun 		dcmi_buffer_done(dcmi, buf, 0, -EIO);
283*4882a593Smuzhiyun 		break;
284*4882a593Smuzhiyun 	case DMA_COMPLETE:
285*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 		/* Return buffer to V4L2 */
288*4882a593Smuzhiyun 		dcmi_buffer_done(dcmi, buf, buf->size, 0);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 		/* Restart capture */
293*4882a593Smuzhiyun 		if (dcmi_restart_capture(dcmi))
294*4882a593Smuzhiyun 			dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n",
295*4882a593Smuzhiyun 				__func__);
296*4882a593Smuzhiyun 		return;
297*4882a593Smuzhiyun 	default:
298*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Received unknown status\n", __func__);
299*4882a593Smuzhiyun 		break;
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
dcmi_start_dma(struct stm32_dcmi * dcmi,struct dcmi_buf * buf)305*4882a593Smuzhiyun static int dcmi_start_dma(struct stm32_dcmi *dcmi,
306*4882a593Smuzhiyun 			  struct dcmi_buf *buf)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	struct dma_async_tx_descriptor *desc = NULL;
309*4882a593Smuzhiyun 	struct dma_slave_config config;
310*4882a593Smuzhiyun 	int ret;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	memset(&config, 0, sizeof(config));
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR;
315*4882a593Smuzhiyun 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
316*4882a593Smuzhiyun 	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
317*4882a593Smuzhiyun 	config.dst_maxburst = 4;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	/* Configure DMA channel */
320*4882a593Smuzhiyun 	ret = dmaengine_slave_config(dcmi->dma_chan, &config);
321*4882a593Smuzhiyun 	if (ret < 0) {
322*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n",
323*4882a593Smuzhiyun 			__func__, ret);
324*4882a593Smuzhiyun 		return ret;
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	/*
328*4882a593Smuzhiyun 	 * Avoid call of dmaengine_terminate_all() between
329*4882a593Smuzhiyun 	 * dmaengine_prep_slave_single() and dmaengine_submit()
330*4882a593Smuzhiyun 	 * by locking the whole DMA submission sequence
331*4882a593Smuzhiyun 	 */
332*4882a593Smuzhiyun 	mutex_lock(&dcmi->dma_lock);
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	/* Prepare a DMA transaction */
335*4882a593Smuzhiyun 	desc = dmaengine_prep_slave_single(dcmi->dma_chan, buf->paddr,
336*4882a593Smuzhiyun 					   buf->size,
337*4882a593Smuzhiyun 					   DMA_DEV_TO_MEM,
338*4882a593Smuzhiyun 					   DMA_PREP_INTERRUPT);
339*4882a593Smuzhiyun 	if (!desc) {
340*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_single failed for buffer phy=%pad size=%zu\n",
341*4882a593Smuzhiyun 			__func__, &buf->paddr, buf->size);
342*4882a593Smuzhiyun 		mutex_unlock(&dcmi->dma_lock);
343*4882a593Smuzhiyun 		return -EINVAL;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	/* Set completion callback routine for notification */
347*4882a593Smuzhiyun 	desc->callback = dcmi_dma_callback;
348*4882a593Smuzhiyun 	desc->callback_param = dcmi;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	/* Push current DMA transaction in the pending queue */
351*4882a593Smuzhiyun 	dcmi->dma_cookie = dmaengine_submit(desc);
352*4882a593Smuzhiyun 	if (dma_submit_error(dcmi->dma_cookie)) {
353*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__);
354*4882a593Smuzhiyun 		mutex_unlock(&dcmi->dma_lock);
355*4882a593Smuzhiyun 		return -ENXIO;
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	mutex_unlock(&dcmi->dma_lock);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	dma_async_issue_pending(dcmi->dma_chan);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
dcmi_start_capture(struct stm32_dcmi * dcmi,struct dcmi_buf * buf)365*4882a593Smuzhiyun static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	int ret;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	if (!buf)
370*4882a593Smuzhiyun 		return -EINVAL;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	ret = dcmi_start_dma(dcmi, buf);
373*4882a593Smuzhiyun 	if (ret) {
374*4882a593Smuzhiyun 		dcmi->errors_count++;
375*4882a593Smuzhiyun 		return ret;
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	/* Enable capture */
379*4882a593Smuzhiyun 	reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	return 0;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
dcmi_set_crop(struct stm32_dcmi * dcmi)384*4882a593Smuzhiyun static void dcmi_set_crop(struct stm32_dcmi *dcmi)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	u32 size, start;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	/* Crop resolution */
389*4882a593Smuzhiyun 	size = ((dcmi->crop.height - 1) << 16) |
390*4882a593Smuzhiyun 		((dcmi->crop.width << 1) - 1);
391*4882a593Smuzhiyun 	reg_write(dcmi->regs, DCMI_CWSIZE, size);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/* Crop start point */
394*4882a593Smuzhiyun 	start = ((dcmi->crop.top) << 16) |
395*4882a593Smuzhiyun 		 ((dcmi->crop.left << 1));
396*4882a593Smuzhiyun 	reg_write(dcmi->regs, DCMI_CWSTRT, start);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Cropping to %ux%u@%u:%u\n",
399*4882a593Smuzhiyun 		dcmi->crop.width, dcmi->crop.height,
400*4882a593Smuzhiyun 		dcmi->crop.left, dcmi->crop.top);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	/* Enable crop */
403*4882a593Smuzhiyun 	reg_set(dcmi->regs, DCMI_CR, CR_CROP);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun 
dcmi_process_jpeg(struct stm32_dcmi * dcmi)406*4882a593Smuzhiyun static void dcmi_process_jpeg(struct stm32_dcmi *dcmi)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	struct dma_tx_state state;
409*4882a593Smuzhiyun 	enum dma_status status;
410*4882a593Smuzhiyun 	struct dcmi_buf *buf = dcmi->active;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	if (!buf)
413*4882a593Smuzhiyun 		return;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	/*
416*4882a593Smuzhiyun 	 * Because of variable JPEG buffer size sent by sensor,
417*4882a593Smuzhiyun 	 * DMA transfer never completes due to transfer size never reached.
418*4882a593Smuzhiyun 	 * In order to ensure that all the JPEG data are transferred
419*4882a593Smuzhiyun 	 * in active buffer memory, DMA is drained.
420*4882a593Smuzhiyun 	 * Then DMA tx status gives the amount of data transferred
421*4882a593Smuzhiyun 	 * to memory, which is then returned to V4L2 through the active
422*4882a593Smuzhiyun 	 * buffer payload.
423*4882a593Smuzhiyun 	 */
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	/* Drain DMA */
426*4882a593Smuzhiyun 	dmaengine_synchronize(dcmi->dma_chan);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	/* Get DMA residue to get JPEG size */
429*4882a593Smuzhiyun 	status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
430*4882a593Smuzhiyun 	if (status != DMA_ERROR && state.residue < buf->size) {
431*4882a593Smuzhiyun 		/* Return JPEG buffer to V4L2 with received JPEG buffer size */
432*4882a593Smuzhiyun 		dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0);
433*4882a593Smuzhiyun 	} else {
434*4882a593Smuzhiyun 		dcmi->errors_count++;
435*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n",
436*4882a593Smuzhiyun 			__func__);
437*4882a593Smuzhiyun 		/* Return JPEG buffer to V4L2 in ERROR state */
438*4882a593Smuzhiyun 		dcmi_buffer_done(dcmi, buf, 0, -EIO);
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	/* Abort DMA operation */
442*4882a593Smuzhiyun 	dmaengine_terminate_all(dcmi->dma_chan);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	/* Restart capture */
445*4882a593Smuzhiyun 	if (dcmi_restart_capture(dcmi))
446*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n",
447*4882a593Smuzhiyun 			__func__);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun 
dcmi_irq_thread(int irq,void * arg)450*4882a593Smuzhiyun static irqreturn_t dcmi_irq_thread(int irq, void *arg)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = arg;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	if (dcmi->misr & IT_OVR) {
457*4882a593Smuzhiyun 		dcmi->overrun_count++;
458*4882a593Smuzhiyun 		if (dcmi->overrun_count > OVERRUN_ERROR_THRESHOLD)
459*4882a593Smuzhiyun 			dcmi->errors_count++;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 	if (dcmi->misr & IT_ERR)
462*4882a593Smuzhiyun 		dcmi->errors_count++;
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG &&
465*4882a593Smuzhiyun 	    dcmi->misr & IT_FRAME) {
466*4882a593Smuzhiyun 		/* JPEG received */
467*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
468*4882a593Smuzhiyun 		dcmi_process_jpeg(dcmi);
469*4882a593Smuzhiyun 		return IRQ_HANDLED;
470*4882a593Smuzhiyun 	}
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
473*4882a593Smuzhiyun 	return IRQ_HANDLED;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun 
dcmi_irq_callback(int irq,void * arg)476*4882a593Smuzhiyun static irqreturn_t dcmi_irq_callback(int irq, void *arg)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = arg;
479*4882a593Smuzhiyun 	unsigned long flags;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	spin_lock_irqsave(&dcmi->irqlock, flags);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	dcmi->misr = reg_read(dcmi->regs, DCMI_MIS);
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	/* Clear interrupt */
486*4882a593Smuzhiyun 	reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dcmi->irqlock, flags);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	return IRQ_WAKE_THREAD;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun 
dcmi_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])493*4882a593Smuzhiyun static int dcmi_queue_setup(struct vb2_queue *vq,
494*4882a593Smuzhiyun 			    unsigned int *nbuffers,
495*4882a593Smuzhiyun 			    unsigned int *nplanes,
496*4882a593Smuzhiyun 			    unsigned int sizes[],
497*4882a593Smuzhiyun 			    struct device *alloc_devs[])
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
500*4882a593Smuzhiyun 	unsigned int size;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	size = dcmi->fmt.fmt.pix.sizeimage;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	/* Make sure the image size is large enough */
505*4882a593Smuzhiyun 	if (*nplanes)
506*4882a593Smuzhiyun 		return sizes[0] < size ? -EINVAL : 0;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	*nplanes = 1;
509*4882a593Smuzhiyun 	sizes[0] = size;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Setup queue, count=%d, size=%d\n",
512*4882a593Smuzhiyun 		*nbuffers, size);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	return 0;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun 
dcmi_buf_init(struct vb2_buffer * vb)517*4882a593Smuzhiyun static int dcmi_buf_init(struct vb2_buffer *vb)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
520*4882a593Smuzhiyun 	struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	INIT_LIST_HEAD(&buf->list);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return 0;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
dcmi_buf_prepare(struct vb2_buffer * vb)527*4882a593Smuzhiyun static int dcmi_buf_prepare(struct vb2_buffer *vb)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi =  vb2_get_drv_priv(vb->vb2_queue);
530*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
531*4882a593Smuzhiyun 	struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
532*4882a593Smuzhiyun 	unsigned long size;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	size = dcmi->fmt.fmt.pix.sizeimage;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	if (vb2_plane_size(vb, 0) < size) {
537*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s data will not fit into plane (%lu < %lu)\n",
538*4882a593Smuzhiyun 			__func__, vb2_plane_size(vb, 0), size);
539*4882a593Smuzhiyun 		return -EINVAL;
540*4882a593Smuzhiyun 	}
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	vb2_set_plane_payload(vb, 0, size);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	if (!buf->prepared) {
545*4882a593Smuzhiyun 		/* Get memory addresses */
546*4882a593Smuzhiyun 		buf->paddr =
547*4882a593Smuzhiyun 			vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
548*4882a593Smuzhiyun 		buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0);
549*4882a593Smuzhiyun 		buf->prepared = true;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 		vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size);
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n",
554*4882a593Smuzhiyun 			vb->index, &buf->paddr, buf->size);
555*4882a593Smuzhiyun 	}
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	return 0;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
dcmi_buf_queue(struct vb2_buffer * vb)560*4882a593Smuzhiyun static void dcmi_buf_queue(struct vb2_buffer *vb)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi =  vb2_get_drv_priv(vb->vb2_queue);
563*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
564*4882a593Smuzhiyun 	struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	/* Enqueue to video buffers list */
569*4882a593Smuzhiyun 	list_add_tail(&buf->list, &dcmi->buffers);
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	if (dcmi->state == WAIT_FOR_BUFFER) {
572*4882a593Smuzhiyun 		dcmi->state = RUNNING;
573*4882a593Smuzhiyun 		dcmi->active = buf;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n",
576*4882a593Smuzhiyun 			buf->vb.vb2_buf.index);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
579*4882a593Smuzhiyun 		if (dcmi_start_capture(dcmi, buf))
580*4882a593Smuzhiyun 			dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n",
581*4882a593Smuzhiyun 				__func__);
582*4882a593Smuzhiyun 		return;
583*4882a593Smuzhiyun 	}
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun 
dcmi_find_source(struct stm32_dcmi * dcmi)588*4882a593Smuzhiyun static struct media_entity *dcmi_find_source(struct stm32_dcmi *dcmi)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun 	struct media_entity *entity = &dcmi->vdev->entity;
591*4882a593Smuzhiyun 	struct media_pad *pad;
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	/* Walk searching for entity having no sink */
594*4882a593Smuzhiyun 	while (1) {
595*4882a593Smuzhiyun 		pad = &entity->pads[0];
596*4882a593Smuzhiyun 		if (!(pad->flags & MEDIA_PAD_FL_SINK))
597*4882a593Smuzhiyun 			break;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 		pad = media_entity_remote_pad(pad);
600*4882a593Smuzhiyun 		if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
601*4882a593Smuzhiyun 			break;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 		entity = pad->entity;
604*4882a593Smuzhiyun 	}
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	return entity;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
dcmi_pipeline_s_fmt(struct stm32_dcmi * dcmi,struct v4l2_subdev_pad_config * pad_cfg,struct v4l2_subdev_format * format)609*4882a593Smuzhiyun static int dcmi_pipeline_s_fmt(struct stm32_dcmi *dcmi,
610*4882a593Smuzhiyun 			       struct v4l2_subdev_pad_config *pad_cfg,
611*4882a593Smuzhiyun 			       struct v4l2_subdev_format *format)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun 	struct media_entity *entity = &dcmi->entity.source->entity;
614*4882a593Smuzhiyun 	struct v4l2_subdev *subdev;
615*4882a593Smuzhiyun 	struct media_pad *sink_pad = NULL;
616*4882a593Smuzhiyun 	struct media_pad *src_pad = NULL;
617*4882a593Smuzhiyun 	struct media_pad *pad = NULL;
618*4882a593Smuzhiyun 	struct v4l2_subdev_format fmt = *format;
619*4882a593Smuzhiyun 	bool found = false;
620*4882a593Smuzhiyun 	int ret;
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	/*
623*4882a593Smuzhiyun 	 * Starting from sensor subdevice, walk within
624*4882a593Smuzhiyun 	 * pipeline and set format on each subdevice
625*4882a593Smuzhiyun 	 */
626*4882a593Smuzhiyun 	while (1) {
627*4882a593Smuzhiyun 		unsigned int i;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 		/* Search if current entity has a source pad */
630*4882a593Smuzhiyun 		for (i = 0; i < entity->num_pads; i++) {
631*4882a593Smuzhiyun 			pad = &entity->pads[i];
632*4882a593Smuzhiyun 			if (pad->flags & MEDIA_PAD_FL_SOURCE) {
633*4882a593Smuzhiyun 				src_pad = pad;
634*4882a593Smuzhiyun 				found = true;
635*4882a593Smuzhiyun 				break;
636*4882a593Smuzhiyun 			}
637*4882a593Smuzhiyun 		}
638*4882a593Smuzhiyun 		if (!found)
639*4882a593Smuzhiyun 			break;
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 		subdev = media_entity_to_v4l2_subdev(entity);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 		/* Propagate format on sink pad if any, otherwise source pad */
644*4882a593Smuzhiyun 		if (sink_pad)
645*4882a593Smuzhiyun 			pad = sink_pad;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "\"%s\":%d pad format set to 0x%x %ux%u\n",
648*4882a593Smuzhiyun 			subdev->name, pad->index, format->format.code,
649*4882a593Smuzhiyun 			format->format.width, format->format.height);
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 		fmt.pad = pad->index;
652*4882a593Smuzhiyun 		ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt);
653*4882a593Smuzhiyun 		if (ret < 0) {
654*4882a593Smuzhiyun 			dev_err(dcmi->dev, "%s: Failed to set format 0x%x %ux%u on \"%s\":%d pad (%d)\n",
655*4882a593Smuzhiyun 				__func__, format->format.code,
656*4882a593Smuzhiyun 				format->format.width, format->format.height,
657*4882a593Smuzhiyun 				subdev->name, pad->index, ret);
658*4882a593Smuzhiyun 			return ret;
659*4882a593Smuzhiyun 		}
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 		if (fmt.format.code != format->format.code ||
662*4882a593Smuzhiyun 		    fmt.format.width != format->format.width ||
663*4882a593Smuzhiyun 		    fmt.format.height != format->format.height) {
664*4882a593Smuzhiyun 			dev_dbg(dcmi->dev, "\"%s\":%d pad format has been changed to 0x%x %ux%u\n",
665*4882a593Smuzhiyun 				subdev->name, pad->index, fmt.format.code,
666*4882a593Smuzhiyun 				fmt.format.width, fmt.format.height);
667*4882a593Smuzhiyun 		}
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 		/* Walk to next entity */
670*4882a593Smuzhiyun 		sink_pad = media_entity_remote_pad(src_pad);
671*4882a593Smuzhiyun 		if (!sink_pad || !is_media_entity_v4l2_subdev(sink_pad->entity))
672*4882a593Smuzhiyun 			break;
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 		entity = sink_pad->entity;
675*4882a593Smuzhiyun 	}
676*4882a593Smuzhiyun 	*format = fmt;
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	return 0;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun 
dcmi_pipeline_s_stream(struct stm32_dcmi * dcmi,int state)681*4882a593Smuzhiyun static int dcmi_pipeline_s_stream(struct stm32_dcmi *dcmi, int state)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun 	struct media_entity *entity = &dcmi->vdev->entity;
684*4882a593Smuzhiyun 	struct v4l2_subdev *subdev;
685*4882a593Smuzhiyun 	struct media_pad *pad;
686*4882a593Smuzhiyun 	int ret;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	/* Start/stop all entities within pipeline */
689*4882a593Smuzhiyun 	while (1) {
690*4882a593Smuzhiyun 		pad = &entity->pads[0];
691*4882a593Smuzhiyun 		if (!(pad->flags & MEDIA_PAD_FL_SINK))
692*4882a593Smuzhiyun 			break;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 		pad = media_entity_remote_pad(pad);
695*4882a593Smuzhiyun 		if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
696*4882a593Smuzhiyun 			break;
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun 		entity = pad->entity;
699*4882a593Smuzhiyun 		subdev = media_entity_to_v4l2_subdev(entity);
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 		ret = v4l2_subdev_call(subdev, video, s_stream, state);
702*4882a593Smuzhiyun 		if (ret < 0 && ret != -ENOIOCTLCMD) {
703*4882a593Smuzhiyun 			dev_err(dcmi->dev, "%s: \"%s\" failed to %s streaming (%d)\n",
704*4882a593Smuzhiyun 				__func__, subdev->name,
705*4882a593Smuzhiyun 				state ? "start" : "stop", ret);
706*4882a593Smuzhiyun 			return ret;
707*4882a593Smuzhiyun 		}
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "\"%s\" is %s\n",
710*4882a593Smuzhiyun 			subdev->name, state ? "started" : "stopped");
711*4882a593Smuzhiyun 	}
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	return 0;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun 
dcmi_pipeline_start(struct stm32_dcmi * dcmi)716*4882a593Smuzhiyun static int dcmi_pipeline_start(struct stm32_dcmi *dcmi)
717*4882a593Smuzhiyun {
718*4882a593Smuzhiyun 	return dcmi_pipeline_s_stream(dcmi, 1);
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun 
dcmi_pipeline_stop(struct stm32_dcmi * dcmi)721*4882a593Smuzhiyun static void dcmi_pipeline_stop(struct stm32_dcmi *dcmi)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun 	dcmi_pipeline_s_stream(dcmi, 0);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun 
dcmi_start_streaming(struct vb2_queue * vq,unsigned int count)726*4882a593Smuzhiyun static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
729*4882a593Smuzhiyun 	struct dcmi_buf *buf, *node;
730*4882a593Smuzhiyun 	u32 val = 0;
731*4882a593Smuzhiyun 	int ret;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(dcmi->dev);
734*4882a593Smuzhiyun 	if (ret < 0) {
735*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Failed to start streaming, cannot get sync (%d)\n",
736*4882a593Smuzhiyun 			__func__, ret);
737*4882a593Smuzhiyun 		goto err_pm_put;
738*4882a593Smuzhiyun 	}
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	ret = media_pipeline_start(&dcmi->vdev->entity, &dcmi->pipeline);
741*4882a593Smuzhiyun 	if (ret < 0) {
742*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Failed to start streaming, media pipeline start error (%d)\n",
743*4882a593Smuzhiyun 			__func__, ret);
744*4882a593Smuzhiyun 		goto err_pm_put;
745*4882a593Smuzhiyun 	}
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	ret = dcmi_pipeline_start(dcmi);
748*4882a593Smuzhiyun 	if (ret)
749*4882a593Smuzhiyun 		goto err_media_pipeline_stop;
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	/* Set bus width */
754*4882a593Smuzhiyun 	switch (dcmi->bus.bus_width) {
755*4882a593Smuzhiyun 	case 14:
756*4882a593Smuzhiyun 		val |= CR_EDM_0 | CR_EDM_1;
757*4882a593Smuzhiyun 		break;
758*4882a593Smuzhiyun 	case 12:
759*4882a593Smuzhiyun 		val |= CR_EDM_1;
760*4882a593Smuzhiyun 		break;
761*4882a593Smuzhiyun 	case 10:
762*4882a593Smuzhiyun 		val |= CR_EDM_0;
763*4882a593Smuzhiyun 		break;
764*4882a593Smuzhiyun 	default:
765*4882a593Smuzhiyun 		/* Set bus width to 8 bits by default */
766*4882a593Smuzhiyun 		break;
767*4882a593Smuzhiyun 	}
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	/* Set vertical synchronization polarity */
770*4882a593Smuzhiyun 	if (dcmi->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
771*4882a593Smuzhiyun 		val |= CR_VSPOL;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	/* Set horizontal synchronization polarity */
774*4882a593Smuzhiyun 	if (dcmi->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
775*4882a593Smuzhiyun 		val |= CR_HSPOL;
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	/* Set pixel clock polarity */
778*4882a593Smuzhiyun 	if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
779*4882a593Smuzhiyun 		val |= CR_PCKPOL;
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 	reg_write(dcmi->regs, DCMI_CR, val);
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 	/* Set crop */
784*4882a593Smuzhiyun 	if (dcmi->do_crop)
785*4882a593Smuzhiyun 		dcmi_set_crop(dcmi);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	/* Enable jpeg capture */
788*4882a593Smuzhiyun 	if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG)
789*4882a593Smuzhiyun 		reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 	/* Enable dcmi */
792*4882a593Smuzhiyun 	reg_set(dcmi->regs, DCMI_CR, CR_ENABLE);
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	dcmi->sequence = 0;
795*4882a593Smuzhiyun 	dcmi->errors_count = 0;
796*4882a593Smuzhiyun 	dcmi->overrun_count = 0;
797*4882a593Smuzhiyun 	dcmi->buffers_count = 0;
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	/*
800*4882a593Smuzhiyun 	 * Start transfer if at least one buffer has been queued,
801*4882a593Smuzhiyun 	 * otherwise transfer is deferred at buffer queueing
802*4882a593Smuzhiyun 	 */
803*4882a593Smuzhiyun 	if (list_empty(&dcmi->buffers)) {
804*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "Start streaming is deferred to next buffer queueing\n");
805*4882a593Smuzhiyun 		dcmi->state = WAIT_FOR_BUFFER;
806*4882a593Smuzhiyun 		spin_unlock_irq(&dcmi->irqlock);
807*4882a593Smuzhiyun 		return 0;
808*4882a593Smuzhiyun 	}
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
811*4882a593Smuzhiyun 	dcmi->active = buf;
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	dcmi->state = RUNNING;
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Start streaming, starting capture\n");
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
818*4882a593Smuzhiyun 	ret = dcmi_start_capture(dcmi, buf);
819*4882a593Smuzhiyun 	if (ret) {
820*4882a593Smuzhiyun 		dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n",
821*4882a593Smuzhiyun 			__func__);
822*4882a593Smuzhiyun 		goto err_pipeline_stop;
823*4882a593Smuzhiyun 	}
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	/* Enable interruptions */
826*4882a593Smuzhiyun 	if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG)
827*4882a593Smuzhiyun 		reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
828*4882a593Smuzhiyun 	else
829*4882a593Smuzhiyun 		reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR);
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	return 0;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun err_pipeline_stop:
834*4882a593Smuzhiyun 	dcmi_pipeline_stop(dcmi);
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun err_media_pipeline_stop:
837*4882a593Smuzhiyun 	media_pipeline_stop(&dcmi->vdev->entity);
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun err_pm_put:
840*4882a593Smuzhiyun 	pm_runtime_put(dcmi->dev);
841*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
842*4882a593Smuzhiyun 	/*
843*4882a593Smuzhiyun 	 * Return all buffers to vb2 in QUEUED state.
844*4882a593Smuzhiyun 	 * This will give ownership back to userspace
845*4882a593Smuzhiyun 	 */
846*4882a593Smuzhiyun 	list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
847*4882a593Smuzhiyun 		list_del_init(&buf->list);
848*4882a593Smuzhiyun 		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
849*4882a593Smuzhiyun 	}
850*4882a593Smuzhiyun 	dcmi->active = NULL;
851*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	return ret;
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun 
dcmi_stop_streaming(struct vb2_queue * vq)856*4882a593Smuzhiyun static void dcmi_stop_streaming(struct vb2_queue *vq)
857*4882a593Smuzhiyun {
858*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
859*4882a593Smuzhiyun 	struct dcmi_buf *buf, *node;
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun 	dcmi_pipeline_stop(dcmi);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	media_pipeline_stop(&dcmi->vdev->entity);
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	spin_lock_irq(&dcmi->irqlock);
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	/* Disable interruptions */
868*4882a593Smuzhiyun 	reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	/* Disable DCMI */
871*4882a593Smuzhiyun 	reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE);
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	/* Return all queued buffers to vb2 in ERROR state */
874*4882a593Smuzhiyun 	list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
875*4882a593Smuzhiyun 		list_del_init(&buf->list);
876*4882a593Smuzhiyun 		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
877*4882a593Smuzhiyun 	}
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	dcmi->active = NULL;
880*4882a593Smuzhiyun 	dcmi->state = STOPPED;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	spin_unlock_irq(&dcmi->irqlock);
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	/* Stop all pending DMA operations */
885*4882a593Smuzhiyun 	mutex_lock(&dcmi->dma_lock);
886*4882a593Smuzhiyun 	dmaengine_terminate_all(dcmi->dma_chan);
887*4882a593Smuzhiyun 	mutex_unlock(&dcmi->dma_lock);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	pm_runtime_put(dcmi->dev);
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	if (dcmi->errors_count)
892*4882a593Smuzhiyun 		dev_warn(dcmi->dev, "Some errors found while streaming: errors=%d (overrun=%d), buffers=%d\n",
893*4882a593Smuzhiyun 			 dcmi->errors_count, dcmi->overrun_count,
894*4882a593Smuzhiyun 			 dcmi->buffers_count);
895*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Stop streaming, errors=%d (overrun=%d), buffers=%d\n",
896*4882a593Smuzhiyun 		dcmi->errors_count, dcmi->overrun_count,
897*4882a593Smuzhiyun 		dcmi->buffers_count);
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun static const struct vb2_ops dcmi_video_qops = {
901*4882a593Smuzhiyun 	.queue_setup		= dcmi_queue_setup,
902*4882a593Smuzhiyun 	.buf_init		= dcmi_buf_init,
903*4882a593Smuzhiyun 	.buf_prepare		= dcmi_buf_prepare,
904*4882a593Smuzhiyun 	.buf_queue		= dcmi_buf_queue,
905*4882a593Smuzhiyun 	.start_streaming	= dcmi_start_streaming,
906*4882a593Smuzhiyun 	.stop_streaming		= dcmi_stop_streaming,
907*4882a593Smuzhiyun 	.wait_prepare		= vb2_ops_wait_prepare,
908*4882a593Smuzhiyun 	.wait_finish		= vb2_ops_wait_finish,
909*4882a593Smuzhiyun };
910*4882a593Smuzhiyun 
dcmi_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * fmt)911*4882a593Smuzhiyun static int dcmi_g_fmt_vid_cap(struct file *file, void *priv,
912*4882a593Smuzhiyun 			      struct v4l2_format *fmt)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun 	*fmt = dcmi->fmt;
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 	return 0;
919*4882a593Smuzhiyun }
920*4882a593Smuzhiyun 
find_format_by_fourcc(struct stm32_dcmi * dcmi,unsigned int fourcc)921*4882a593Smuzhiyun static const struct dcmi_format *find_format_by_fourcc(struct stm32_dcmi *dcmi,
922*4882a593Smuzhiyun 						       unsigned int fourcc)
923*4882a593Smuzhiyun {
924*4882a593Smuzhiyun 	unsigned int num_formats = dcmi->num_of_sd_formats;
925*4882a593Smuzhiyun 	const struct dcmi_format *fmt;
926*4882a593Smuzhiyun 	unsigned int i;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 	for (i = 0; i < num_formats; i++) {
929*4882a593Smuzhiyun 		fmt = dcmi->sd_formats[i];
930*4882a593Smuzhiyun 		if (fmt->fourcc == fourcc)
931*4882a593Smuzhiyun 			return fmt;
932*4882a593Smuzhiyun 	}
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	return NULL;
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun 
__find_outer_frame_size(struct stm32_dcmi * dcmi,struct v4l2_pix_format * pix,struct dcmi_framesize * framesize)937*4882a593Smuzhiyun static void __find_outer_frame_size(struct stm32_dcmi *dcmi,
938*4882a593Smuzhiyun 				    struct v4l2_pix_format *pix,
939*4882a593Smuzhiyun 				    struct dcmi_framesize *framesize)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun 	struct dcmi_framesize *match = NULL;
942*4882a593Smuzhiyun 	unsigned int i;
943*4882a593Smuzhiyun 	unsigned int min_err = UINT_MAX;
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
946*4882a593Smuzhiyun 		struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
947*4882a593Smuzhiyun 		int w_err = (fsize->width - pix->width);
948*4882a593Smuzhiyun 		int h_err = (fsize->height - pix->height);
949*4882a593Smuzhiyun 		int err = w_err + h_err;
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 		if (w_err >= 0 && h_err >= 0 && err < min_err) {
952*4882a593Smuzhiyun 			min_err = err;
953*4882a593Smuzhiyun 			match = fsize;
954*4882a593Smuzhiyun 		}
955*4882a593Smuzhiyun 	}
956*4882a593Smuzhiyun 	if (!match)
957*4882a593Smuzhiyun 		match = &dcmi->sd_framesizes[0];
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	*framesize = *match;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun 
dcmi_try_fmt(struct stm32_dcmi * dcmi,struct v4l2_format * f,const struct dcmi_format ** sd_format,struct dcmi_framesize * sd_framesize)962*4882a593Smuzhiyun static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f,
963*4882a593Smuzhiyun 			const struct dcmi_format **sd_format,
964*4882a593Smuzhiyun 			struct dcmi_framesize *sd_framesize)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun 	const struct dcmi_format *sd_fmt;
967*4882a593Smuzhiyun 	struct dcmi_framesize sd_fsize;
968*4882a593Smuzhiyun 	struct v4l2_pix_format *pix = &f->fmt.pix;
969*4882a593Smuzhiyun 	struct v4l2_subdev_pad_config pad_cfg;
970*4882a593Smuzhiyun 	struct v4l2_subdev_format format = {
971*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_TRY,
972*4882a593Smuzhiyun 	};
973*4882a593Smuzhiyun 	bool do_crop;
974*4882a593Smuzhiyun 	int ret;
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
977*4882a593Smuzhiyun 	if (!sd_fmt) {
978*4882a593Smuzhiyun 		if (!dcmi->num_of_sd_formats)
979*4882a593Smuzhiyun 			return -ENODATA;
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 		sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
982*4882a593Smuzhiyun 		pix->pixelformat = sd_fmt->fourcc;
983*4882a593Smuzhiyun 	}
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	/* Limit to hardware capabilities */
986*4882a593Smuzhiyun 	pix->width = clamp(pix->width, MIN_WIDTH, MAX_WIDTH);
987*4882a593Smuzhiyun 	pix->height = clamp(pix->height, MIN_HEIGHT, MAX_HEIGHT);
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	/* No crop if JPEG is requested */
990*4882a593Smuzhiyun 	do_crop = dcmi->do_crop && (pix->pixelformat != V4L2_PIX_FMT_JPEG);
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	if (do_crop && dcmi->num_of_sd_framesizes) {
993*4882a593Smuzhiyun 		struct dcmi_framesize outer_sd_fsize;
994*4882a593Smuzhiyun 		/*
995*4882a593Smuzhiyun 		 * If crop is requested and sensor have discrete frame sizes,
996*4882a593Smuzhiyun 		 * select the frame size that is just larger than request
997*4882a593Smuzhiyun 		 */
998*4882a593Smuzhiyun 		__find_outer_frame_size(dcmi, pix, &outer_sd_fsize);
999*4882a593Smuzhiyun 		pix->width = outer_sd_fsize.width;
1000*4882a593Smuzhiyun 		pix->height = outer_sd_fsize.height;
1001*4882a593Smuzhiyun 	}
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
1004*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad, set_fmt,
1005*4882a593Smuzhiyun 			       &pad_cfg, &format);
1006*4882a593Smuzhiyun 	if (ret < 0)
1007*4882a593Smuzhiyun 		return ret;
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	/* Update pix regarding to what sensor can do */
1010*4882a593Smuzhiyun 	v4l2_fill_pix_format(pix, &format.format);
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun 	/* Save resolution that sensor can actually do */
1013*4882a593Smuzhiyun 	sd_fsize.width = pix->width;
1014*4882a593Smuzhiyun 	sd_fsize.height = pix->height;
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	if (do_crop) {
1017*4882a593Smuzhiyun 		struct v4l2_rect c = dcmi->crop;
1018*4882a593Smuzhiyun 		struct v4l2_rect max_rect;
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 		/*
1021*4882a593Smuzhiyun 		 * Adjust crop by making the intersection between
1022*4882a593Smuzhiyun 		 * format resolution request and crop request
1023*4882a593Smuzhiyun 		 */
1024*4882a593Smuzhiyun 		max_rect.top = 0;
1025*4882a593Smuzhiyun 		max_rect.left = 0;
1026*4882a593Smuzhiyun 		max_rect.width = pix->width;
1027*4882a593Smuzhiyun 		max_rect.height = pix->height;
1028*4882a593Smuzhiyun 		v4l2_rect_map_inside(&c, &max_rect);
1029*4882a593Smuzhiyun 		c.top  = clamp_t(s32, c.top, 0, pix->height - c.height);
1030*4882a593Smuzhiyun 		c.left = clamp_t(s32, c.left, 0, pix->width - c.width);
1031*4882a593Smuzhiyun 		dcmi->crop = c;
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 		/* Adjust format resolution request to crop */
1034*4882a593Smuzhiyun 		pix->width = dcmi->crop.width;
1035*4882a593Smuzhiyun 		pix->height = dcmi->crop.height;
1036*4882a593Smuzhiyun 	}
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun 	pix->field = V4L2_FIELD_NONE;
1039*4882a593Smuzhiyun 	pix->bytesperline = pix->width * sd_fmt->bpp;
1040*4882a593Smuzhiyun 	pix->sizeimage = pix->bytesperline * pix->height;
1041*4882a593Smuzhiyun 
1042*4882a593Smuzhiyun 	if (sd_format)
1043*4882a593Smuzhiyun 		*sd_format = sd_fmt;
1044*4882a593Smuzhiyun 	if (sd_framesize)
1045*4882a593Smuzhiyun 		*sd_framesize = sd_fsize;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	return 0;
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun 
dcmi_set_fmt(struct stm32_dcmi * dcmi,struct v4l2_format * f)1050*4882a593Smuzhiyun static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f)
1051*4882a593Smuzhiyun {
1052*4882a593Smuzhiyun 	struct v4l2_subdev_format format = {
1053*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1054*4882a593Smuzhiyun 	};
1055*4882a593Smuzhiyun 	const struct dcmi_format *sd_format;
1056*4882a593Smuzhiyun 	struct dcmi_framesize sd_framesize;
1057*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format.format;
1058*4882a593Smuzhiyun 	struct v4l2_pix_format *pix = &f->fmt.pix;
1059*4882a593Smuzhiyun 	int ret;
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	/*
1062*4882a593Smuzhiyun 	 * Try format, fmt.width/height could have been changed
1063*4882a593Smuzhiyun 	 * to match sensor capability or crop request
1064*4882a593Smuzhiyun 	 * sd_format & sd_framesize will contain what subdev
1065*4882a593Smuzhiyun 	 * can do for this request.
1066*4882a593Smuzhiyun 	 */
1067*4882a593Smuzhiyun 	ret = dcmi_try_fmt(dcmi, f, &sd_format, &sd_framesize);
1068*4882a593Smuzhiyun 	if (ret)
1069*4882a593Smuzhiyun 		return ret;
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	/* Disable crop if JPEG is requested */
1072*4882a593Smuzhiyun 	if (pix->pixelformat == V4L2_PIX_FMT_JPEG)
1073*4882a593Smuzhiyun 		dcmi->do_crop = false;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	/* pix to mbus format */
1076*4882a593Smuzhiyun 	v4l2_fill_mbus_format(mf, pix,
1077*4882a593Smuzhiyun 			      sd_format->mbus_code);
1078*4882a593Smuzhiyun 	mf->width = sd_framesize.width;
1079*4882a593Smuzhiyun 	mf->height = sd_framesize.height;
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	ret = dcmi_pipeline_s_fmt(dcmi, NULL, &format);
1082*4882a593Smuzhiyun 	if (ret < 0)
1083*4882a593Smuzhiyun 		return ret;
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Sensor format set to 0x%x %ux%u\n",
1086*4882a593Smuzhiyun 		mf->code, mf->width, mf->height);
1087*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Buffer format set to %4.4s %ux%u\n",
1088*4882a593Smuzhiyun 		(char *)&pix->pixelformat,
1089*4882a593Smuzhiyun 		pix->width, pix->height);
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	dcmi->fmt = *f;
1092*4882a593Smuzhiyun 	dcmi->sd_format = sd_format;
1093*4882a593Smuzhiyun 	dcmi->sd_framesize = sd_framesize;
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 	return 0;
1096*4882a593Smuzhiyun }
1097*4882a593Smuzhiyun 
dcmi_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1098*4882a593Smuzhiyun static int dcmi_s_fmt_vid_cap(struct file *file, void *priv,
1099*4882a593Smuzhiyun 			      struct v4l2_format *f)
1100*4882a593Smuzhiyun {
1101*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	if (vb2_is_streaming(&dcmi->queue))
1104*4882a593Smuzhiyun 		return -EBUSY;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	return dcmi_set_fmt(dcmi, f);
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun 
dcmi_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1109*4882a593Smuzhiyun static int dcmi_try_fmt_vid_cap(struct file *file, void *priv,
1110*4882a593Smuzhiyun 				struct v4l2_format *f)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	return dcmi_try_fmt(dcmi, f, NULL, NULL);
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun 
dcmi_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)1117*4882a593Smuzhiyun static int dcmi_enum_fmt_vid_cap(struct file *file, void  *priv,
1118*4882a593Smuzhiyun 				 struct v4l2_fmtdesc *f)
1119*4882a593Smuzhiyun {
1120*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	if (f->index >= dcmi->num_of_sd_formats)
1123*4882a593Smuzhiyun 		return -EINVAL;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	f->pixelformat = dcmi->sd_formats[f->index]->fourcc;
1126*4882a593Smuzhiyun 	return 0;
1127*4882a593Smuzhiyun }
1128*4882a593Smuzhiyun 
dcmi_get_sensor_format(struct stm32_dcmi * dcmi,struct v4l2_pix_format * pix)1129*4882a593Smuzhiyun static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi,
1130*4882a593Smuzhiyun 				  struct v4l2_pix_format *pix)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun 	struct v4l2_subdev_format fmt = {
1133*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1134*4882a593Smuzhiyun 	};
1135*4882a593Smuzhiyun 	int ret;
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad, get_fmt, NULL, &fmt);
1138*4882a593Smuzhiyun 	if (ret)
1139*4882a593Smuzhiyun 		return ret;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	v4l2_fill_pix_format(pix, &fmt.format);
1142*4882a593Smuzhiyun 
1143*4882a593Smuzhiyun 	return 0;
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun 
dcmi_set_sensor_format(struct stm32_dcmi * dcmi,struct v4l2_pix_format * pix)1146*4882a593Smuzhiyun static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi,
1147*4882a593Smuzhiyun 				  struct v4l2_pix_format *pix)
1148*4882a593Smuzhiyun {
1149*4882a593Smuzhiyun 	const struct dcmi_format *sd_fmt;
1150*4882a593Smuzhiyun 	struct v4l2_subdev_format format = {
1151*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_TRY,
1152*4882a593Smuzhiyun 	};
1153*4882a593Smuzhiyun 	struct v4l2_subdev_pad_config pad_cfg;
1154*4882a593Smuzhiyun 	int ret;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
1157*4882a593Smuzhiyun 	if (!sd_fmt) {
1158*4882a593Smuzhiyun 		if (!dcmi->num_of_sd_formats)
1159*4882a593Smuzhiyun 			return -ENODATA;
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 		sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
1162*4882a593Smuzhiyun 		pix->pixelformat = sd_fmt->fourcc;
1163*4882a593Smuzhiyun 	}
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
1166*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad, set_fmt,
1167*4882a593Smuzhiyun 			       &pad_cfg, &format);
1168*4882a593Smuzhiyun 	if (ret < 0)
1169*4882a593Smuzhiyun 		return ret;
1170*4882a593Smuzhiyun 
1171*4882a593Smuzhiyun 	return 0;
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun 
dcmi_get_sensor_bounds(struct stm32_dcmi * dcmi,struct v4l2_rect * r)1174*4882a593Smuzhiyun static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi,
1175*4882a593Smuzhiyun 				  struct v4l2_rect *r)
1176*4882a593Smuzhiyun {
1177*4882a593Smuzhiyun 	struct v4l2_subdev_selection bounds = {
1178*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1179*4882a593Smuzhiyun 		.target = V4L2_SEL_TGT_CROP_BOUNDS,
1180*4882a593Smuzhiyun 	};
1181*4882a593Smuzhiyun 	unsigned int max_width, max_height, max_pixsize;
1182*4882a593Smuzhiyun 	struct v4l2_pix_format pix;
1183*4882a593Smuzhiyun 	unsigned int i;
1184*4882a593Smuzhiyun 	int ret;
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	/*
1187*4882a593Smuzhiyun 	 * Get sensor bounds first
1188*4882a593Smuzhiyun 	 */
1189*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad, get_selection,
1190*4882a593Smuzhiyun 			       NULL, &bounds);
1191*4882a593Smuzhiyun 	if (!ret)
1192*4882a593Smuzhiyun 		*r = bounds.r;
1193*4882a593Smuzhiyun 	if (ret != -ENOIOCTLCMD)
1194*4882a593Smuzhiyun 		return ret;
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	/*
1197*4882a593Smuzhiyun 	 * If selection is not implemented,
1198*4882a593Smuzhiyun 	 * fallback by enumerating sensor frame sizes
1199*4882a593Smuzhiyun 	 * and take the largest one
1200*4882a593Smuzhiyun 	 */
1201*4882a593Smuzhiyun 	max_width = 0;
1202*4882a593Smuzhiyun 	max_height = 0;
1203*4882a593Smuzhiyun 	max_pixsize = 0;
1204*4882a593Smuzhiyun 	for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1205*4882a593Smuzhiyun 		struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
1206*4882a593Smuzhiyun 		unsigned int pixsize = fsize->width * fsize->height;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 		if (pixsize > max_pixsize) {
1209*4882a593Smuzhiyun 			max_pixsize = pixsize;
1210*4882a593Smuzhiyun 			max_width = fsize->width;
1211*4882a593Smuzhiyun 			max_height = fsize->height;
1212*4882a593Smuzhiyun 		}
1213*4882a593Smuzhiyun 	}
1214*4882a593Smuzhiyun 	if (max_pixsize > 0) {
1215*4882a593Smuzhiyun 		r->top = 0;
1216*4882a593Smuzhiyun 		r->left = 0;
1217*4882a593Smuzhiyun 		r->width = max_width;
1218*4882a593Smuzhiyun 		r->height = max_height;
1219*4882a593Smuzhiyun 		return 0;
1220*4882a593Smuzhiyun 	}
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	/*
1223*4882a593Smuzhiyun 	 * If frame sizes enumeration is not implemented,
1224*4882a593Smuzhiyun 	 * fallback by getting current sensor frame size
1225*4882a593Smuzhiyun 	 */
1226*4882a593Smuzhiyun 	ret = dcmi_get_sensor_format(dcmi, &pix);
1227*4882a593Smuzhiyun 	if (ret)
1228*4882a593Smuzhiyun 		return ret;
1229*4882a593Smuzhiyun 
1230*4882a593Smuzhiyun 	r->top = 0;
1231*4882a593Smuzhiyun 	r->left = 0;
1232*4882a593Smuzhiyun 	r->width = pix.width;
1233*4882a593Smuzhiyun 	r->height = pix.height;
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	return 0;
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun 
dcmi_g_selection(struct file * file,void * fh,struct v4l2_selection * s)1238*4882a593Smuzhiyun static int dcmi_g_selection(struct file *file, void *fh,
1239*4882a593Smuzhiyun 			    struct v4l2_selection *s)
1240*4882a593Smuzhiyun {
1241*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1244*4882a593Smuzhiyun 		return -EINVAL;
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	switch (s->target) {
1247*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_DEFAULT:
1248*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_BOUNDS:
1249*4882a593Smuzhiyun 		s->r = dcmi->sd_bounds;
1250*4882a593Smuzhiyun 		return 0;
1251*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP:
1252*4882a593Smuzhiyun 		if (dcmi->do_crop) {
1253*4882a593Smuzhiyun 			s->r = dcmi->crop;
1254*4882a593Smuzhiyun 		} else {
1255*4882a593Smuzhiyun 			s->r.top = 0;
1256*4882a593Smuzhiyun 			s->r.left = 0;
1257*4882a593Smuzhiyun 			s->r.width = dcmi->fmt.fmt.pix.width;
1258*4882a593Smuzhiyun 			s->r.height = dcmi->fmt.fmt.pix.height;
1259*4882a593Smuzhiyun 		}
1260*4882a593Smuzhiyun 		break;
1261*4882a593Smuzhiyun 	default:
1262*4882a593Smuzhiyun 		return -EINVAL;
1263*4882a593Smuzhiyun 	}
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	return 0;
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun 
dcmi_s_selection(struct file * file,void * priv,struct v4l2_selection * s)1268*4882a593Smuzhiyun static int dcmi_s_selection(struct file *file, void *priv,
1269*4882a593Smuzhiyun 			    struct v4l2_selection *s)
1270*4882a593Smuzhiyun {
1271*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1272*4882a593Smuzhiyun 	struct v4l2_rect r = s->r;
1273*4882a593Smuzhiyun 	struct v4l2_rect max_rect;
1274*4882a593Smuzhiyun 	struct v4l2_pix_format pix;
1275*4882a593Smuzhiyun 
1276*4882a593Smuzhiyun 	if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE ||
1277*4882a593Smuzhiyun 	    s->target != V4L2_SEL_TGT_CROP)
1278*4882a593Smuzhiyun 		return -EINVAL;
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	/* Reset sensor resolution to max resolution */
1281*4882a593Smuzhiyun 	pix.pixelformat = dcmi->fmt.fmt.pix.pixelformat;
1282*4882a593Smuzhiyun 	pix.width = dcmi->sd_bounds.width;
1283*4882a593Smuzhiyun 	pix.height = dcmi->sd_bounds.height;
1284*4882a593Smuzhiyun 	dcmi_set_sensor_format(dcmi, &pix);
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	/*
1287*4882a593Smuzhiyun 	 * Make the intersection between
1288*4882a593Smuzhiyun 	 * sensor resolution
1289*4882a593Smuzhiyun 	 * and crop request
1290*4882a593Smuzhiyun 	 */
1291*4882a593Smuzhiyun 	max_rect.top = 0;
1292*4882a593Smuzhiyun 	max_rect.left = 0;
1293*4882a593Smuzhiyun 	max_rect.width = pix.width;
1294*4882a593Smuzhiyun 	max_rect.height = pix.height;
1295*4882a593Smuzhiyun 	v4l2_rect_map_inside(&r, &max_rect);
1296*4882a593Smuzhiyun 	r.top  = clamp_t(s32, r.top, 0, pix.height - r.height);
1297*4882a593Smuzhiyun 	r.left = clamp_t(s32, r.left, 0, pix.width - r.width);
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	if (!(r.top == dcmi->sd_bounds.top &&
1300*4882a593Smuzhiyun 	      r.left == dcmi->sd_bounds.left &&
1301*4882a593Smuzhiyun 	      r.width == dcmi->sd_bounds.width &&
1302*4882a593Smuzhiyun 	      r.height == dcmi->sd_bounds.height)) {
1303*4882a593Smuzhiyun 		/* Crop if request is different than sensor resolution */
1304*4882a593Smuzhiyun 		dcmi->do_crop = true;
1305*4882a593Smuzhiyun 		dcmi->crop = r;
1306*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "s_selection: crop %ux%u@(%u,%u) from %ux%u\n",
1307*4882a593Smuzhiyun 			r.width, r.height, r.left, r.top,
1308*4882a593Smuzhiyun 			pix.width, pix.height);
1309*4882a593Smuzhiyun 	} else {
1310*4882a593Smuzhiyun 		/* Disable crop */
1311*4882a593Smuzhiyun 		dcmi->do_crop = false;
1312*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "s_selection: crop is disabled\n");
1313*4882a593Smuzhiyun 	}
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	s->r = r;
1316*4882a593Smuzhiyun 	return 0;
1317*4882a593Smuzhiyun }
1318*4882a593Smuzhiyun 
dcmi_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1319*4882a593Smuzhiyun static int dcmi_querycap(struct file *file, void *priv,
1320*4882a593Smuzhiyun 			 struct v4l2_capability *cap)
1321*4882a593Smuzhiyun {
1322*4882a593Smuzhiyun 	strscpy(cap->driver, DRV_NAME, sizeof(cap->driver));
1323*4882a593Smuzhiyun 	strscpy(cap->card, "STM32 Camera Memory Interface",
1324*4882a593Smuzhiyun 		sizeof(cap->card));
1325*4882a593Smuzhiyun 	strscpy(cap->bus_info, "platform:dcmi", sizeof(cap->bus_info));
1326*4882a593Smuzhiyun 	return 0;
1327*4882a593Smuzhiyun }
1328*4882a593Smuzhiyun 
dcmi_enum_input(struct file * file,void * priv,struct v4l2_input * i)1329*4882a593Smuzhiyun static int dcmi_enum_input(struct file *file, void *priv,
1330*4882a593Smuzhiyun 			   struct v4l2_input *i)
1331*4882a593Smuzhiyun {
1332*4882a593Smuzhiyun 	if (i->index != 0)
1333*4882a593Smuzhiyun 		return -EINVAL;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	i->type = V4L2_INPUT_TYPE_CAMERA;
1336*4882a593Smuzhiyun 	strscpy(i->name, "Camera", sizeof(i->name));
1337*4882a593Smuzhiyun 	return 0;
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun 
dcmi_g_input(struct file * file,void * priv,unsigned int * i)1340*4882a593Smuzhiyun static int dcmi_g_input(struct file *file, void *priv, unsigned int *i)
1341*4882a593Smuzhiyun {
1342*4882a593Smuzhiyun 	*i = 0;
1343*4882a593Smuzhiyun 	return 0;
1344*4882a593Smuzhiyun }
1345*4882a593Smuzhiyun 
dcmi_s_input(struct file * file,void * priv,unsigned int i)1346*4882a593Smuzhiyun static int dcmi_s_input(struct file *file, void *priv, unsigned int i)
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun 	if (i > 0)
1349*4882a593Smuzhiyun 		return -EINVAL;
1350*4882a593Smuzhiyun 	return 0;
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun 
dcmi_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1353*4882a593Smuzhiyun static int dcmi_enum_framesizes(struct file *file, void *fh,
1354*4882a593Smuzhiyun 				struct v4l2_frmsizeenum *fsize)
1355*4882a593Smuzhiyun {
1356*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1357*4882a593Smuzhiyun 	const struct dcmi_format *sd_fmt;
1358*4882a593Smuzhiyun 	struct v4l2_subdev_frame_size_enum fse = {
1359*4882a593Smuzhiyun 		.index = fsize->index,
1360*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1361*4882a593Smuzhiyun 	};
1362*4882a593Smuzhiyun 	int ret;
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun 	sd_fmt = find_format_by_fourcc(dcmi, fsize->pixel_format);
1365*4882a593Smuzhiyun 	if (!sd_fmt)
1366*4882a593Smuzhiyun 		return -EINVAL;
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	fse.code = sd_fmt->mbus_code;
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad, enum_frame_size,
1371*4882a593Smuzhiyun 			       NULL, &fse);
1372*4882a593Smuzhiyun 	if (ret)
1373*4882a593Smuzhiyun 		return ret;
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1376*4882a593Smuzhiyun 	fsize->discrete.width = fse.max_width;
1377*4882a593Smuzhiyun 	fsize->discrete.height = fse.max_height;
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	return 0;
1380*4882a593Smuzhiyun }
1381*4882a593Smuzhiyun 
dcmi_g_parm(struct file * file,void * priv,struct v4l2_streamparm * p)1382*4882a593Smuzhiyun static int dcmi_g_parm(struct file *file, void *priv,
1383*4882a593Smuzhiyun 		       struct v4l2_streamparm *p)
1384*4882a593Smuzhiyun {
1385*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1386*4882a593Smuzhiyun 
1387*4882a593Smuzhiyun 	return v4l2_g_parm_cap(video_devdata(file), dcmi->entity.source, p);
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun 
dcmi_s_parm(struct file * file,void * priv,struct v4l2_streamparm * p)1390*4882a593Smuzhiyun static int dcmi_s_parm(struct file *file, void *priv,
1391*4882a593Smuzhiyun 		       struct v4l2_streamparm *p)
1392*4882a593Smuzhiyun {
1393*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	return v4l2_s_parm_cap(video_devdata(file), dcmi->entity.source, p);
1396*4882a593Smuzhiyun }
1397*4882a593Smuzhiyun 
dcmi_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)1398*4882a593Smuzhiyun static int dcmi_enum_frameintervals(struct file *file, void *fh,
1399*4882a593Smuzhiyun 				    struct v4l2_frmivalenum *fival)
1400*4882a593Smuzhiyun {
1401*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1402*4882a593Smuzhiyun 	const struct dcmi_format *sd_fmt;
1403*4882a593Smuzhiyun 	struct v4l2_subdev_frame_interval_enum fie = {
1404*4882a593Smuzhiyun 		.index = fival->index,
1405*4882a593Smuzhiyun 		.width = fival->width,
1406*4882a593Smuzhiyun 		.height = fival->height,
1407*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1408*4882a593Smuzhiyun 	};
1409*4882a593Smuzhiyun 	int ret;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	sd_fmt = find_format_by_fourcc(dcmi, fival->pixel_format);
1412*4882a593Smuzhiyun 	if (!sd_fmt)
1413*4882a593Smuzhiyun 		return -EINVAL;
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	fie.code = sd_fmt->mbus_code;
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun 	ret = v4l2_subdev_call(dcmi->entity.source, pad,
1418*4882a593Smuzhiyun 			       enum_frame_interval, NULL, &fie);
1419*4882a593Smuzhiyun 	if (ret)
1420*4882a593Smuzhiyun 		return ret;
1421*4882a593Smuzhiyun 
1422*4882a593Smuzhiyun 	fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1423*4882a593Smuzhiyun 	fival->discrete = fie.interval;
1424*4882a593Smuzhiyun 
1425*4882a593Smuzhiyun 	return 0;
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun 
1428*4882a593Smuzhiyun static const struct of_device_id stm32_dcmi_of_match[] = {
1429*4882a593Smuzhiyun 	{ .compatible = "st,stm32-dcmi"},
1430*4882a593Smuzhiyun 	{ /* end node */ },
1431*4882a593Smuzhiyun };
1432*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match);
1433*4882a593Smuzhiyun 
dcmi_open(struct file * file)1434*4882a593Smuzhiyun static int dcmi_open(struct file *file)
1435*4882a593Smuzhiyun {
1436*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1437*4882a593Smuzhiyun 	struct v4l2_subdev *sd = dcmi->entity.source;
1438*4882a593Smuzhiyun 	int ret;
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	if (mutex_lock_interruptible(&dcmi->lock))
1441*4882a593Smuzhiyun 		return -ERESTARTSYS;
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	ret = v4l2_fh_open(file);
1444*4882a593Smuzhiyun 	if (ret < 0)
1445*4882a593Smuzhiyun 		goto unlock;
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 	if (!v4l2_fh_is_singular_file(file))
1448*4882a593Smuzhiyun 		goto fh_rel;
1449*4882a593Smuzhiyun 
1450*4882a593Smuzhiyun 	ret = v4l2_subdev_call(sd, core, s_power, 1);
1451*4882a593Smuzhiyun 	if (ret < 0 && ret != -ENOIOCTLCMD)
1452*4882a593Smuzhiyun 		goto fh_rel;
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 	ret = dcmi_set_fmt(dcmi, &dcmi->fmt);
1455*4882a593Smuzhiyun 	if (ret)
1456*4882a593Smuzhiyun 		v4l2_subdev_call(sd, core, s_power, 0);
1457*4882a593Smuzhiyun fh_rel:
1458*4882a593Smuzhiyun 	if (ret)
1459*4882a593Smuzhiyun 		v4l2_fh_release(file);
1460*4882a593Smuzhiyun unlock:
1461*4882a593Smuzhiyun 	mutex_unlock(&dcmi->lock);
1462*4882a593Smuzhiyun 	return ret;
1463*4882a593Smuzhiyun }
1464*4882a593Smuzhiyun 
dcmi_release(struct file * file)1465*4882a593Smuzhiyun static int dcmi_release(struct file *file)
1466*4882a593Smuzhiyun {
1467*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = video_drvdata(file);
1468*4882a593Smuzhiyun 	struct v4l2_subdev *sd = dcmi->entity.source;
1469*4882a593Smuzhiyun 	bool fh_singular;
1470*4882a593Smuzhiyun 	int ret;
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	mutex_lock(&dcmi->lock);
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	fh_singular = v4l2_fh_is_singular_file(file);
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	ret = _vb2_fop_release(file, NULL);
1477*4882a593Smuzhiyun 
1478*4882a593Smuzhiyun 	if (fh_singular)
1479*4882a593Smuzhiyun 		v4l2_subdev_call(sd, core, s_power, 0);
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	mutex_unlock(&dcmi->lock);
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun 	return ret;
1484*4882a593Smuzhiyun }
1485*4882a593Smuzhiyun 
1486*4882a593Smuzhiyun static const struct v4l2_ioctl_ops dcmi_ioctl_ops = {
1487*4882a593Smuzhiyun 	.vidioc_querycap		= dcmi_querycap,
1488*4882a593Smuzhiyun 
1489*4882a593Smuzhiyun 	.vidioc_try_fmt_vid_cap		= dcmi_try_fmt_vid_cap,
1490*4882a593Smuzhiyun 	.vidioc_g_fmt_vid_cap		= dcmi_g_fmt_vid_cap,
1491*4882a593Smuzhiyun 	.vidioc_s_fmt_vid_cap		= dcmi_s_fmt_vid_cap,
1492*4882a593Smuzhiyun 	.vidioc_enum_fmt_vid_cap	= dcmi_enum_fmt_vid_cap,
1493*4882a593Smuzhiyun 	.vidioc_g_selection		= dcmi_g_selection,
1494*4882a593Smuzhiyun 	.vidioc_s_selection		= dcmi_s_selection,
1495*4882a593Smuzhiyun 
1496*4882a593Smuzhiyun 	.vidioc_enum_input		= dcmi_enum_input,
1497*4882a593Smuzhiyun 	.vidioc_g_input			= dcmi_g_input,
1498*4882a593Smuzhiyun 	.vidioc_s_input			= dcmi_s_input,
1499*4882a593Smuzhiyun 
1500*4882a593Smuzhiyun 	.vidioc_g_parm			= dcmi_g_parm,
1501*4882a593Smuzhiyun 	.vidioc_s_parm			= dcmi_s_parm,
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun 	.vidioc_enum_framesizes		= dcmi_enum_framesizes,
1504*4882a593Smuzhiyun 	.vidioc_enum_frameintervals	= dcmi_enum_frameintervals,
1505*4882a593Smuzhiyun 
1506*4882a593Smuzhiyun 	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
1507*4882a593Smuzhiyun 	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
1508*4882a593Smuzhiyun 	.vidioc_querybuf		= vb2_ioctl_querybuf,
1509*4882a593Smuzhiyun 	.vidioc_qbuf			= vb2_ioctl_qbuf,
1510*4882a593Smuzhiyun 	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
1511*4882a593Smuzhiyun 	.vidioc_expbuf			= vb2_ioctl_expbuf,
1512*4882a593Smuzhiyun 	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
1513*4882a593Smuzhiyun 	.vidioc_streamon		= vb2_ioctl_streamon,
1514*4882a593Smuzhiyun 	.vidioc_streamoff		= vb2_ioctl_streamoff,
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	.vidioc_log_status		= v4l2_ctrl_log_status,
1517*4882a593Smuzhiyun 	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
1518*4882a593Smuzhiyun 	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
1519*4882a593Smuzhiyun };
1520*4882a593Smuzhiyun 
1521*4882a593Smuzhiyun static const struct v4l2_file_operations dcmi_fops = {
1522*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
1523*4882a593Smuzhiyun 	.unlocked_ioctl	= video_ioctl2,
1524*4882a593Smuzhiyun 	.open		= dcmi_open,
1525*4882a593Smuzhiyun 	.release	= dcmi_release,
1526*4882a593Smuzhiyun 	.poll		= vb2_fop_poll,
1527*4882a593Smuzhiyun 	.mmap		= vb2_fop_mmap,
1528*4882a593Smuzhiyun #ifndef CONFIG_MMU
1529*4882a593Smuzhiyun 	.get_unmapped_area = vb2_fop_get_unmapped_area,
1530*4882a593Smuzhiyun #endif
1531*4882a593Smuzhiyun 	.read		= vb2_fop_read,
1532*4882a593Smuzhiyun };
1533*4882a593Smuzhiyun 
dcmi_set_default_fmt(struct stm32_dcmi * dcmi)1534*4882a593Smuzhiyun static int dcmi_set_default_fmt(struct stm32_dcmi *dcmi)
1535*4882a593Smuzhiyun {
1536*4882a593Smuzhiyun 	struct v4l2_format f = {
1537*4882a593Smuzhiyun 		.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1538*4882a593Smuzhiyun 		.fmt.pix = {
1539*4882a593Smuzhiyun 			.width		= CIF_WIDTH,
1540*4882a593Smuzhiyun 			.height		= CIF_HEIGHT,
1541*4882a593Smuzhiyun 			.field		= V4L2_FIELD_NONE,
1542*4882a593Smuzhiyun 			.pixelformat	= dcmi->sd_formats[0]->fourcc,
1543*4882a593Smuzhiyun 		},
1544*4882a593Smuzhiyun 	};
1545*4882a593Smuzhiyun 	int ret;
1546*4882a593Smuzhiyun 
1547*4882a593Smuzhiyun 	ret = dcmi_try_fmt(dcmi, &f, NULL, NULL);
1548*4882a593Smuzhiyun 	if (ret)
1549*4882a593Smuzhiyun 		return ret;
1550*4882a593Smuzhiyun 	dcmi->sd_format = dcmi->sd_formats[0];
1551*4882a593Smuzhiyun 	dcmi->fmt = f;
1552*4882a593Smuzhiyun 	return 0;
1553*4882a593Smuzhiyun }
1554*4882a593Smuzhiyun 
1555*4882a593Smuzhiyun /*
1556*4882a593Smuzhiyun  * FIXME: For the time being we only support subdevices
1557*4882a593Smuzhiyun  * which expose RGB & YUV "parallel form" mbus code (_2X8).
1558*4882a593Smuzhiyun  * Nevertheless, this allows to support serial source subdevices
1559*4882a593Smuzhiyun  * and serial to parallel bridges which conform to this.
1560*4882a593Smuzhiyun  */
1561*4882a593Smuzhiyun static const struct dcmi_format dcmi_formats[] = {
1562*4882a593Smuzhiyun 	{
1563*4882a593Smuzhiyun 		.fourcc = V4L2_PIX_FMT_RGB565,
1564*4882a593Smuzhiyun 		.mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
1565*4882a593Smuzhiyun 		.bpp = 2,
1566*4882a593Smuzhiyun 	}, {
1567*4882a593Smuzhiyun 		.fourcc = V4L2_PIX_FMT_YUYV,
1568*4882a593Smuzhiyun 		.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
1569*4882a593Smuzhiyun 		.bpp = 2,
1570*4882a593Smuzhiyun 	}, {
1571*4882a593Smuzhiyun 		.fourcc = V4L2_PIX_FMT_UYVY,
1572*4882a593Smuzhiyun 		.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
1573*4882a593Smuzhiyun 		.bpp = 2,
1574*4882a593Smuzhiyun 	}, {
1575*4882a593Smuzhiyun 		.fourcc = V4L2_PIX_FMT_JPEG,
1576*4882a593Smuzhiyun 		.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
1577*4882a593Smuzhiyun 		.bpp = 1,
1578*4882a593Smuzhiyun 	},
1579*4882a593Smuzhiyun };
1580*4882a593Smuzhiyun 
dcmi_formats_init(struct stm32_dcmi * dcmi)1581*4882a593Smuzhiyun static int dcmi_formats_init(struct stm32_dcmi *dcmi)
1582*4882a593Smuzhiyun {
1583*4882a593Smuzhiyun 	const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)];
1584*4882a593Smuzhiyun 	unsigned int num_fmts = 0, i, j;
1585*4882a593Smuzhiyun 	struct v4l2_subdev *subdev = dcmi->entity.source;
1586*4882a593Smuzhiyun 	struct v4l2_subdev_mbus_code_enum mbus_code = {
1587*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1588*4882a593Smuzhiyun 	};
1589*4882a593Smuzhiyun 
1590*4882a593Smuzhiyun 	while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1591*4882a593Smuzhiyun 				 NULL, &mbus_code)) {
1592*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(dcmi_formats); i++) {
1593*4882a593Smuzhiyun 			if (dcmi_formats[i].mbus_code != mbus_code.code)
1594*4882a593Smuzhiyun 				continue;
1595*4882a593Smuzhiyun 
1596*4882a593Smuzhiyun 			/* Code supported, have we got this fourcc yet? */
1597*4882a593Smuzhiyun 			for (j = 0; j < num_fmts; j++)
1598*4882a593Smuzhiyun 				if (sd_fmts[j]->fourcc ==
1599*4882a593Smuzhiyun 						dcmi_formats[i].fourcc) {
1600*4882a593Smuzhiyun 					/* Already available */
1601*4882a593Smuzhiyun 					dev_dbg(dcmi->dev, "Skipping fourcc/code: %4.4s/0x%x\n",
1602*4882a593Smuzhiyun 						(char *)&sd_fmts[j]->fourcc,
1603*4882a593Smuzhiyun 						mbus_code.code);
1604*4882a593Smuzhiyun 					break;
1605*4882a593Smuzhiyun 				}
1606*4882a593Smuzhiyun 			if (j == num_fmts) {
1607*4882a593Smuzhiyun 				/* New */
1608*4882a593Smuzhiyun 				sd_fmts[num_fmts++] = dcmi_formats + i;
1609*4882a593Smuzhiyun 				dev_dbg(dcmi->dev, "Supported fourcc/code: %4.4s/0x%x\n",
1610*4882a593Smuzhiyun 					(char *)&sd_fmts[num_fmts - 1]->fourcc,
1611*4882a593Smuzhiyun 					sd_fmts[num_fmts - 1]->mbus_code);
1612*4882a593Smuzhiyun 			}
1613*4882a593Smuzhiyun 		}
1614*4882a593Smuzhiyun 		mbus_code.index++;
1615*4882a593Smuzhiyun 	}
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun 	if (!num_fmts)
1618*4882a593Smuzhiyun 		return -ENXIO;
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 	dcmi->num_of_sd_formats = num_fmts;
1621*4882a593Smuzhiyun 	dcmi->sd_formats = devm_kcalloc(dcmi->dev,
1622*4882a593Smuzhiyun 					num_fmts, sizeof(struct dcmi_format *),
1623*4882a593Smuzhiyun 					GFP_KERNEL);
1624*4882a593Smuzhiyun 	if (!dcmi->sd_formats) {
1625*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Could not allocate memory\n");
1626*4882a593Smuzhiyun 		return -ENOMEM;
1627*4882a593Smuzhiyun 	}
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	memcpy(dcmi->sd_formats, sd_fmts,
1630*4882a593Smuzhiyun 	       num_fmts * sizeof(struct dcmi_format *));
1631*4882a593Smuzhiyun 	dcmi->sd_format = dcmi->sd_formats[0];
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun 	return 0;
1634*4882a593Smuzhiyun }
1635*4882a593Smuzhiyun 
dcmi_framesizes_init(struct stm32_dcmi * dcmi)1636*4882a593Smuzhiyun static int dcmi_framesizes_init(struct stm32_dcmi *dcmi)
1637*4882a593Smuzhiyun {
1638*4882a593Smuzhiyun 	unsigned int num_fsize = 0;
1639*4882a593Smuzhiyun 	struct v4l2_subdev *subdev = dcmi->entity.source;
1640*4882a593Smuzhiyun 	struct v4l2_subdev_frame_size_enum fse = {
1641*4882a593Smuzhiyun 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1642*4882a593Smuzhiyun 		.code = dcmi->sd_format->mbus_code,
1643*4882a593Smuzhiyun 	};
1644*4882a593Smuzhiyun 	unsigned int ret;
1645*4882a593Smuzhiyun 	unsigned int i;
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 	/* Allocate discrete framesizes array */
1648*4882a593Smuzhiyun 	while (!v4l2_subdev_call(subdev, pad, enum_frame_size,
1649*4882a593Smuzhiyun 				 NULL, &fse))
1650*4882a593Smuzhiyun 		fse.index++;
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	num_fsize = fse.index;
1653*4882a593Smuzhiyun 	if (!num_fsize)
1654*4882a593Smuzhiyun 		return 0;
1655*4882a593Smuzhiyun 
1656*4882a593Smuzhiyun 	dcmi->num_of_sd_framesizes = num_fsize;
1657*4882a593Smuzhiyun 	dcmi->sd_framesizes = devm_kcalloc(dcmi->dev, num_fsize,
1658*4882a593Smuzhiyun 					   sizeof(struct dcmi_framesize),
1659*4882a593Smuzhiyun 					   GFP_KERNEL);
1660*4882a593Smuzhiyun 	if (!dcmi->sd_framesizes) {
1661*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Could not allocate memory\n");
1662*4882a593Smuzhiyun 		return -ENOMEM;
1663*4882a593Smuzhiyun 	}
1664*4882a593Smuzhiyun 
1665*4882a593Smuzhiyun 	/* Fill array with sensor supported framesizes */
1666*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Sensor supports %u frame sizes:\n", num_fsize);
1667*4882a593Smuzhiyun 	for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1668*4882a593Smuzhiyun 		fse.index = i;
1669*4882a593Smuzhiyun 		ret = v4l2_subdev_call(subdev, pad, enum_frame_size,
1670*4882a593Smuzhiyun 				       NULL, &fse);
1671*4882a593Smuzhiyun 		if (ret)
1672*4882a593Smuzhiyun 			return ret;
1673*4882a593Smuzhiyun 		dcmi->sd_framesizes[fse.index].width = fse.max_width;
1674*4882a593Smuzhiyun 		dcmi->sd_framesizes[fse.index].height = fse.max_height;
1675*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "%ux%u\n", fse.max_width, fse.max_height);
1676*4882a593Smuzhiyun 	}
1677*4882a593Smuzhiyun 
1678*4882a593Smuzhiyun 	return 0;
1679*4882a593Smuzhiyun }
1680*4882a593Smuzhiyun 
dcmi_graph_notify_complete(struct v4l2_async_notifier * notifier)1681*4882a593Smuzhiyun static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier)
1682*4882a593Smuzhiyun {
1683*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1684*4882a593Smuzhiyun 	int ret;
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	/*
1687*4882a593Smuzhiyun 	 * Now that the graph is complete,
1688*4882a593Smuzhiyun 	 * we search for the source subdevice
1689*4882a593Smuzhiyun 	 * in order to expose it through V4L2 interface
1690*4882a593Smuzhiyun 	 */
1691*4882a593Smuzhiyun 	dcmi->entity.source =
1692*4882a593Smuzhiyun 		media_entity_to_v4l2_subdev(dcmi_find_source(dcmi));
1693*4882a593Smuzhiyun 	if (!dcmi->entity.source) {
1694*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Source subdevice not found\n");
1695*4882a593Smuzhiyun 		return -ENODEV;
1696*4882a593Smuzhiyun 	}
1697*4882a593Smuzhiyun 
1698*4882a593Smuzhiyun 	dcmi->vdev->ctrl_handler = dcmi->entity.source->ctrl_handler;
1699*4882a593Smuzhiyun 
1700*4882a593Smuzhiyun 	ret = dcmi_formats_init(dcmi);
1701*4882a593Smuzhiyun 	if (ret) {
1702*4882a593Smuzhiyun 		dev_err(dcmi->dev, "No supported mediabus format found\n");
1703*4882a593Smuzhiyun 		return ret;
1704*4882a593Smuzhiyun 	}
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun 	ret = dcmi_framesizes_init(dcmi);
1707*4882a593Smuzhiyun 	if (ret) {
1708*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Could not initialize framesizes\n");
1709*4882a593Smuzhiyun 		return ret;
1710*4882a593Smuzhiyun 	}
1711*4882a593Smuzhiyun 
1712*4882a593Smuzhiyun 	ret = dcmi_get_sensor_bounds(dcmi, &dcmi->sd_bounds);
1713*4882a593Smuzhiyun 	if (ret) {
1714*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Could not get sensor bounds\n");
1715*4882a593Smuzhiyun 		return ret;
1716*4882a593Smuzhiyun 	}
1717*4882a593Smuzhiyun 
1718*4882a593Smuzhiyun 	ret = dcmi_set_default_fmt(dcmi);
1719*4882a593Smuzhiyun 	if (ret) {
1720*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Could not set default format\n");
1721*4882a593Smuzhiyun 		return ret;
1722*4882a593Smuzhiyun 	}
1723*4882a593Smuzhiyun 
1724*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(dcmi->dev, dcmi->irq, dcmi_irq_callback,
1725*4882a593Smuzhiyun 					dcmi_irq_thread, IRQF_ONESHOT,
1726*4882a593Smuzhiyun 					dev_name(dcmi->dev), dcmi);
1727*4882a593Smuzhiyun 	if (ret) {
1728*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Unable to request irq %d\n", dcmi->irq);
1729*4882a593Smuzhiyun 		return ret;
1730*4882a593Smuzhiyun 	}
1731*4882a593Smuzhiyun 
1732*4882a593Smuzhiyun 	return 0;
1733*4882a593Smuzhiyun }
1734*4882a593Smuzhiyun 
dcmi_graph_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1735*4882a593Smuzhiyun static void dcmi_graph_notify_unbind(struct v4l2_async_notifier *notifier,
1736*4882a593Smuzhiyun 				     struct v4l2_subdev *sd,
1737*4882a593Smuzhiyun 				     struct v4l2_async_subdev *asd)
1738*4882a593Smuzhiyun {
1739*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1740*4882a593Smuzhiyun 
1741*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Removing %s\n", video_device_node_name(dcmi->vdev));
1742*4882a593Smuzhiyun 
1743*4882a593Smuzhiyun 	/* Checks internally if vdev has been init or not */
1744*4882a593Smuzhiyun 	video_unregister_device(dcmi->vdev);
1745*4882a593Smuzhiyun }
1746*4882a593Smuzhiyun 
dcmi_graph_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1747*4882a593Smuzhiyun static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier,
1748*4882a593Smuzhiyun 				   struct v4l2_subdev *subdev,
1749*4882a593Smuzhiyun 				   struct v4l2_async_subdev *asd)
1750*4882a593Smuzhiyun {
1751*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1752*4882a593Smuzhiyun 	unsigned int ret;
1753*4882a593Smuzhiyun 	int src_pad;
1754*4882a593Smuzhiyun 
1755*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Subdev \"%s\" bound\n", subdev->name);
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 	/*
1758*4882a593Smuzhiyun 	 * Link this sub-device to DCMI, it could be
1759*4882a593Smuzhiyun 	 * a parallel camera sensor or a bridge
1760*4882a593Smuzhiyun 	 */
1761*4882a593Smuzhiyun 	src_pad = media_entity_get_fwnode_pad(&subdev->entity,
1762*4882a593Smuzhiyun 					      subdev->fwnode,
1763*4882a593Smuzhiyun 					      MEDIA_PAD_FL_SOURCE);
1764*4882a593Smuzhiyun 
1765*4882a593Smuzhiyun 	ret = media_create_pad_link(&subdev->entity, src_pad,
1766*4882a593Smuzhiyun 				    &dcmi->vdev->entity, 0,
1767*4882a593Smuzhiyun 				    MEDIA_LNK_FL_IMMUTABLE |
1768*4882a593Smuzhiyun 				    MEDIA_LNK_FL_ENABLED);
1769*4882a593Smuzhiyun 	if (ret)
1770*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to create media pad link with subdev \"%s\"\n",
1771*4882a593Smuzhiyun 			subdev->name);
1772*4882a593Smuzhiyun 	else
1773*4882a593Smuzhiyun 		dev_dbg(dcmi->dev, "DCMI is now linked to \"%s\"\n",
1774*4882a593Smuzhiyun 			subdev->name);
1775*4882a593Smuzhiyun 
1776*4882a593Smuzhiyun 	return ret;
1777*4882a593Smuzhiyun }
1778*4882a593Smuzhiyun 
1779*4882a593Smuzhiyun static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = {
1780*4882a593Smuzhiyun 	.bound = dcmi_graph_notify_bound,
1781*4882a593Smuzhiyun 	.unbind = dcmi_graph_notify_unbind,
1782*4882a593Smuzhiyun 	.complete = dcmi_graph_notify_complete,
1783*4882a593Smuzhiyun };
1784*4882a593Smuzhiyun 
dcmi_graph_parse(struct stm32_dcmi * dcmi,struct device_node * node)1785*4882a593Smuzhiyun static int dcmi_graph_parse(struct stm32_dcmi *dcmi, struct device_node *node)
1786*4882a593Smuzhiyun {
1787*4882a593Smuzhiyun 	struct device_node *ep = NULL;
1788*4882a593Smuzhiyun 	struct device_node *remote;
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 	ep = of_graph_get_next_endpoint(node, ep);
1791*4882a593Smuzhiyun 	if (!ep)
1792*4882a593Smuzhiyun 		return -EINVAL;
1793*4882a593Smuzhiyun 
1794*4882a593Smuzhiyun 	remote = of_graph_get_remote_port_parent(ep);
1795*4882a593Smuzhiyun 	of_node_put(ep);
1796*4882a593Smuzhiyun 	if (!remote)
1797*4882a593Smuzhiyun 		return -EINVAL;
1798*4882a593Smuzhiyun 
1799*4882a593Smuzhiyun 	/* Remote node to connect */
1800*4882a593Smuzhiyun 	dcmi->entity.remote_node = remote;
1801*4882a593Smuzhiyun 	dcmi->entity.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1802*4882a593Smuzhiyun 	dcmi->entity.asd.match.fwnode = of_fwnode_handle(remote);
1803*4882a593Smuzhiyun 	return 0;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun 
dcmi_graph_init(struct stm32_dcmi * dcmi)1806*4882a593Smuzhiyun static int dcmi_graph_init(struct stm32_dcmi *dcmi)
1807*4882a593Smuzhiyun {
1808*4882a593Smuzhiyun 	int ret;
1809*4882a593Smuzhiyun 
1810*4882a593Smuzhiyun 	/* Parse the graph to extract a list of subdevice DT nodes. */
1811*4882a593Smuzhiyun 	ret = dcmi_graph_parse(dcmi, dcmi->dev->of_node);
1812*4882a593Smuzhiyun 	if (ret < 0) {
1813*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to parse graph\n");
1814*4882a593Smuzhiyun 		return ret;
1815*4882a593Smuzhiyun 	}
1816*4882a593Smuzhiyun 
1817*4882a593Smuzhiyun 	v4l2_async_notifier_init(&dcmi->notifier);
1818*4882a593Smuzhiyun 
1819*4882a593Smuzhiyun 	ret = v4l2_async_notifier_add_subdev(&dcmi->notifier,
1820*4882a593Smuzhiyun 					     &dcmi->entity.asd);
1821*4882a593Smuzhiyun 	if (ret) {
1822*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to add subdev notifier\n");
1823*4882a593Smuzhiyun 		of_node_put(dcmi->entity.remote_node);
1824*4882a593Smuzhiyun 		return ret;
1825*4882a593Smuzhiyun 	}
1826*4882a593Smuzhiyun 
1827*4882a593Smuzhiyun 	dcmi->notifier.ops = &dcmi_graph_notify_ops;
1828*4882a593Smuzhiyun 
1829*4882a593Smuzhiyun 	ret = v4l2_async_notifier_register(&dcmi->v4l2_dev, &dcmi->notifier);
1830*4882a593Smuzhiyun 	if (ret < 0) {
1831*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to register notifier\n");
1832*4882a593Smuzhiyun 		v4l2_async_notifier_cleanup(&dcmi->notifier);
1833*4882a593Smuzhiyun 		return ret;
1834*4882a593Smuzhiyun 	}
1835*4882a593Smuzhiyun 
1836*4882a593Smuzhiyun 	return 0;
1837*4882a593Smuzhiyun }
1838*4882a593Smuzhiyun 
dcmi_probe(struct platform_device * pdev)1839*4882a593Smuzhiyun static int dcmi_probe(struct platform_device *pdev)
1840*4882a593Smuzhiyun {
1841*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
1842*4882a593Smuzhiyun 	const struct of_device_id *match = NULL;
1843*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
1844*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi;
1845*4882a593Smuzhiyun 	struct vb2_queue *q;
1846*4882a593Smuzhiyun 	struct dma_chan *chan;
1847*4882a593Smuzhiyun 	struct clk *mclk;
1848*4882a593Smuzhiyun 	int irq;
1849*4882a593Smuzhiyun 	int ret = 0;
1850*4882a593Smuzhiyun 
1851*4882a593Smuzhiyun 	match = of_match_device(of_match_ptr(stm32_dcmi_of_match), &pdev->dev);
1852*4882a593Smuzhiyun 	if (!match) {
1853*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not find a match in devicetree\n");
1854*4882a593Smuzhiyun 		return -ENODEV;
1855*4882a593Smuzhiyun 	}
1856*4882a593Smuzhiyun 
1857*4882a593Smuzhiyun 	dcmi = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dcmi), GFP_KERNEL);
1858*4882a593Smuzhiyun 	if (!dcmi)
1859*4882a593Smuzhiyun 		return -ENOMEM;
1860*4882a593Smuzhiyun 
1861*4882a593Smuzhiyun 	dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1862*4882a593Smuzhiyun 	if (IS_ERR(dcmi->rstc)) {
1863*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not get reset control\n");
1864*4882a593Smuzhiyun 		return PTR_ERR(dcmi->rstc);
1865*4882a593Smuzhiyun 	}
1866*4882a593Smuzhiyun 
1867*4882a593Smuzhiyun 	/* Get bus characteristics from devicetree */
1868*4882a593Smuzhiyun 	np = of_graph_get_next_endpoint(np, NULL);
1869*4882a593Smuzhiyun 	if (!np) {
1870*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not find the endpoint\n");
1871*4882a593Smuzhiyun 		return -ENODEV;
1872*4882a593Smuzhiyun 	}
1873*4882a593Smuzhiyun 
1874*4882a593Smuzhiyun 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
1875*4882a593Smuzhiyun 	of_node_put(np);
1876*4882a593Smuzhiyun 	if (ret) {
1877*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not parse the endpoint\n");
1878*4882a593Smuzhiyun 		return ret;
1879*4882a593Smuzhiyun 	}
1880*4882a593Smuzhiyun 
1881*4882a593Smuzhiyun 	if (ep.bus_type == V4L2_MBUS_CSI2_DPHY) {
1882*4882a593Smuzhiyun 		dev_err(&pdev->dev, "CSI bus not supported\n");
1883*4882a593Smuzhiyun 		return -ENODEV;
1884*4882a593Smuzhiyun 	}
1885*4882a593Smuzhiyun 	dcmi->bus.flags = ep.bus.parallel.flags;
1886*4882a593Smuzhiyun 	dcmi->bus.bus_width = ep.bus.parallel.bus_width;
1887*4882a593Smuzhiyun 	dcmi->bus.data_shift = ep.bus.parallel.data_shift;
1888*4882a593Smuzhiyun 
1889*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
1890*4882a593Smuzhiyun 	if (irq <= 0)
1891*4882a593Smuzhiyun 		return irq ? irq : -ENXIO;
1892*4882a593Smuzhiyun 
1893*4882a593Smuzhiyun 	dcmi->irq = irq;
1894*4882a593Smuzhiyun 
1895*4882a593Smuzhiyun 	dcmi->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1896*4882a593Smuzhiyun 	if (!dcmi->res) {
1897*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not get resource\n");
1898*4882a593Smuzhiyun 		return -ENODEV;
1899*4882a593Smuzhiyun 	}
1900*4882a593Smuzhiyun 
1901*4882a593Smuzhiyun 	dcmi->regs = devm_ioremap_resource(&pdev->dev, dcmi->res);
1902*4882a593Smuzhiyun 	if (IS_ERR(dcmi->regs)) {
1903*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not map registers\n");
1904*4882a593Smuzhiyun 		return PTR_ERR(dcmi->regs);
1905*4882a593Smuzhiyun 	}
1906*4882a593Smuzhiyun 
1907*4882a593Smuzhiyun 	mclk = devm_clk_get(&pdev->dev, "mclk");
1908*4882a593Smuzhiyun 	if (IS_ERR(mclk)) {
1909*4882a593Smuzhiyun 		if (PTR_ERR(mclk) != -EPROBE_DEFER)
1910*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Unable to get mclk\n");
1911*4882a593Smuzhiyun 		return PTR_ERR(mclk);
1912*4882a593Smuzhiyun 	}
1913*4882a593Smuzhiyun 
1914*4882a593Smuzhiyun 	chan = dma_request_chan(&pdev->dev, "tx");
1915*4882a593Smuzhiyun 	if (IS_ERR(chan)) {
1916*4882a593Smuzhiyun 		ret = PTR_ERR(chan);
1917*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
1918*4882a593Smuzhiyun 			dev_err(&pdev->dev,
1919*4882a593Smuzhiyun 				"Failed to request DMA channel: %d\n", ret);
1920*4882a593Smuzhiyun 		return ret;
1921*4882a593Smuzhiyun 	}
1922*4882a593Smuzhiyun 
1923*4882a593Smuzhiyun 	spin_lock_init(&dcmi->irqlock);
1924*4882a593Smuzhiyun 	mutex_init(&dcmi->lock);
1925*4882a593Smuzhiyun 	mutex_init(&dcmi->dma_lock);
1926*4882a593Smuzhiyun 	init_completion(&dcmi->complete);
1927*4882a593Smuzhiyun 	INIT_LIST_HEAD(&dcmi->buffers);
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 	dcmi->dev = &pdev->dev;
1930*4882a593Smuzhiyun 	dcmi->mclk = mclk;
1931*4882a593Smuzhiyun 	dcmi->state = STOPPED;
1932*4882a593Smuzhiyun 	dcmi->dma_chan = chan;
1933*4882a593Smuzhiyun 
1934*4882a593Smuzhiyun 	q = &dcmi->queue;
1935*4882a593Smuzhiyun 
1936*4882a593Smuzhiyun 	dcmi->v4l2_dev.mdev = &dcmi->mdev;
1937*4882a593Smuzhiyun 
1938*4882a593Smuzhiyun 	/* Initialize media device */
1939*4882a593Smuzhiyun 	strscpy(dcmi->mdev.model, DRV_NAME, sizeof(dcmi->mdev.model));
1940*4882a593Smuzhiyun 	snprintf(dcmi->mdev.bus_info, sizeof(dcmi->mdev.bus_info),
1941*4882a593Smuzhiyun 		 "platform:%s", DRV_NAME);
1942*4882a593Smuzhiyun 	dcmi->mdev.dev = &pdev->dev;
1943*4882a593Smuzhiyun 	media_device_init(&dcmi->mdev);
1944*4882a593Smuzhiyun 
1945*4882a593Smuzhiyun 	/* Initialize the top-level structure */
1946*4882a593Smuzhiyun 	ret = v4l2_device_register(&pdev->dev, &dcmi->v4l2_dev);
1947*4882a593Smuzhiyun 	if (ret)
1948*4882a593Smuzhiyun 		goto err_media_device_cleanup;
1949*4882a593Smuzhiyun 
1950*4882a593Smuzhiyun 	dcmi->vdev = video_device_alloc();
1951*4882a593Smuzhiyun 	if (!dcmi->vdev) {
1952*4882a593Smuzhiyun 		ret = -ENOMEM;
1953*4882a593Smuzhiyun 		goto err_device_unregister;
1954*4882a593Smuzhiyun 	}
1955*4882a593Smuzhiyun 
1956*4882a593Smuzhiyun 	/* Video node */
1957*4882a593Smuzhiyun 	dcmi->vdev->fops = &dcmi_fops;
1958*4882a593Smuzhiyun 	dcmi->vdev->v4l2_dev = &dcmi->v4l2_dev;
1959*4882a593Smuzhiyun 	dcmi->vdev->queue = &dcmi->queue;
1960*4882a593Smuzhiyun 	strscpy(dcmi->vdev->name, KBUILD_MODNAME, sizeof(dcmi->vdev->name));
1961*4882a593Smuzhiyun 	dcmi->vdev->release = video_device_release;
1962*4882a593Smuzhiyun 	dcmi->vdev->ioctl_ops = &dcmi_ioctl_ops;
1963*4882a593Smuzhiyun 	dcmi->vdev->lock = &dcmi->lock;
1964*4882a593Smuzhiyun 	dcmi->vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1965*4882a593Smuzhiyun 				  V4L2_CAP_READWRITE;
1966*4882a593Smuzhiyun 	video_set_drvdata(dcmi->vdev, dcmi);
1967*4882a593Smuzhiyun 
1968*4882a593Smuzhiyun 	/* Media entity pads */
1969*4882a593Smuzhiyun 	dcmi->vid_cap_pad.flags = MEDIA_PAD_FL_SINK;
1970*4882a593Smuzhiyun 	ret = media_entity_pads_init(&dcmi->vdev->entity,
1971*4882a593Smuzhiyun 				     1, &dcmi->vid_cap_pad);
1972*4882a593Smuzhiyun 	if (ret) {
1973*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to init media entity pad\n");
1974*4882a593Smuzhiyun 		goto err_device_release;
1975*4882a593Smuzhiyun 	}
1976*4882a593Smuzhiyun 	dcmi->vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
1977*4882a593Smuzhiyun 
1978*4882a593Smuzhiyun 	ret = video_register_device(dcmi->vdev, VFL_TYPE_VIDEO, -1);
1979*4882a593Smuzhiyun 	if (ret) {
1980*4882a593Smuzhiyun 		dev_err(dcmi->dev, "Failed to register video device\n");
1981*4882a593Smuzhiyun 		goto err_media_entity_cleanup;
1982*4882a593Smuzhiyun 	}
1983*4882a593Smuzhiyun 
1984*4882a593Smuzhiyun 	dev_dbg(dcmi->dev, "Device registered as %s\n",
1985*4882a593Smuzhiyun 		video_device_node_name(dcmi->vdev));
1986*4882a593Smuzhiyun 
1987*4882a593Smuzhiyun 	/* Buffer queue */
1988*4882a593Smuzhiyun 	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1989*4882a593Smuzhiyun 	q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1990*4882a593Smuzhiyun 	q->lock = &dcmi->lock;
1991*4882a593Smuzhiyun 	q->drv_priv = dcmi;
1992*4882a593Smuzhiyun 	q->buf_struct_size = sizeof(struct dcmi_buf);
1993*4882a593Smuzhiyun 	q->ops = &dcmi_video_qops;
1994*4882a593Smuzhiyun 	q->mem_ops = &vb2_dma_contig_memops;
1995*4882a593Smuzhiyun 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1996*4882a593Smuzhiyun 	q->min_buffers_needed = 2;
1997*4882a593Smuzhiyun 	q->dev = &pdev->dev;
1998*4882a593Smuzhiyun 
1999*4882a593Smuzhiyun 	ret = vb2_queue_init(q);
2000*4882a593Smuzhiyun 	if (ret < 0) {
2001*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to initialize vb2 queue\n");
2002*4882a593Smuzhiyun 		goto err_media_entity_cleanup;
2003*4882a593Smuzhiyun 	}
2004*4882a593Smuzhiyun 
2005*4882a593Smuzhiyun 	ret = dcmi_graph_init(dcmi);
2006*4882a593Smuzhiyun 	if (ret < 0)
2007*4882a593Smuzhiyun 		goto err_media_entity_cleanup;
2008*4882a593Smuzhiyun 
2009*4882a593Smuzhiyun 	/* Reset device */
2010*4882a593Smuzhiyun 	ret = reset_control_assert(dcmi->rstc);
2011*4882a593Smuzhiyun 	if (ret) {
2012*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to assert the reset line\n");
2013*4882a593Smuzhiyun 		goto err_cleanup;
2014*4882a593Smuzhiyun 	}
2015*4882a593Smuzhiyun 
2016*4882a593Smuzhiyun 	usleep_range(3000, 5000);
2017*4882a593Smuzhiyun 
2018*4882a593Smuzhiyun 	ret = reset_control_deassert(dcmi->rstc);
2019*4882a593Smuzhiyun 	if (ret) {
2020*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to deassert the reset line\n");
2021*4882a593Smuzhiyun 		goto err_cleanup;
2022*4882a593Smuzhiyun 	}
2023*4882a593Smuzhiyun 
2024*4882a593Smuzhiyun 	dev_info(&pdev->dev, "Probe done\n");
2025*4882a593Smuzhiyun 
2026*4882a593Smuzhiyun 	platform_set_drvdata(pdev, dcmi);
2027*4882a593Smuzhiyun 
2028*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
2029*4882a593Smuzhiyun 
2030*4882a593Smuzhiyun 	return 0;
2031*4882a593Smuzhiyun 
2032*4882a593Smuzhiyun err_cleanup:
2033*4882a593Smuzhiyun 	v4l2_async_notifier_cleanup(&dcmi->notifier);
2034*4882a593Smuzhiyun err_media_entity_cleanup:
2035*4882a593Smuzhiyun 	media_entity_cleanup(&dcmi->vdev->entity);
2036*4882a593Smuzhiyun err_device_release:
2037*4882a593Smuzhiyun 	video_device_release(dcmi->vdev);
2038*4882a593Smuzhiyun err_device_unregister:
2039*4882a593Smuzhiyun 	v4l2_device_unregister(&dcmi->v4l2_dev);
2040*4882a593Smuzhiyun err_media_device_cleanup:
2041*4882a593Smuzhiyun 	media_device_cleanup(&dcmi->mdev);
2042*4882a593Smuzhiyun 	dma_release_channel(dcmi->dma_chan);
2043*4882a593Smuzhiyun 
2044*4882a593Smuzhiyun 	return ret;
2045*4882a593Smuzhiyun }
2046*4882a593Smuzhiyun 
dcmi_remove(struct platform_device * pdev)2047*4882a593Smuzhiyun static int dcmi_remove(struct platform_device *pdev)
2048*4882a593Smuzhiyun {
2049*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = platform_get_drvdata(pdev);
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
2052*4882a593Smuzhiyun 
2053*4882a593Smuzhiyun 	v4l2_async_notifier_unregister(&dcmi->notifier);
2054*4882a593Smuzhiyun 	v4l2_async_notifier_cleanup(&dcmi->notifier);
2055*4882a593Smuzhiyun 	media_entity_cleanup(&dcmi->vdev->entity);
2056*4882a593Smuzhiyun 	v4l2_device_unregister(&dcmi->v4l2_dev);
2057*4882a593Smuzhiyun 	media_device_cleanup(&dcmi->mdev);
2058*4882a593Smuzhiyun 
2059*4882a593Smuzhiyun 	dma_release_channel(dcmi->dma_chan);
2060*4882a593Smuzhiyun 
2061*4882a593Smuzhiyun 	return 0;
2062*4882a593Smuzhiyun }
2063*4882a593Smuzhiyun 
dcmi_runtime_suspend(struct device * dev)2064*4882a593Smuzhiyun static __maybe_unused int dcmi_runtime_suspend(struct device *dev)
2065*4882a593Smuzhiyun {
2066*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = dev_get_drvdata(dev);
2067*4882a593Smuzhiyun 
2068*4882a593Smuzhiyun 	clk_disable_unprepare(dcmi->mclk);
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	return 0;
2071*4882a593Smuzhiyun }
2072*4882a593Smuzhiyun 
dcmi_runtime_resume(struct device * dev)2073*4882a593Smuzhiyun static __maybe_unused int dcmi_runtime_resume(struct device *dev)
2074*4882a593Smuzhiyun {
2075*4882a593Smuzhiyun 	struct stm32_dcmi *dcmi = dev_get_drvdata(dev);
2076*4882a593Smuzhiyun 	int ret;
2077*4882a593Smuzhiyun 
2078*4882a593Smuzhiyun 	ret = clk_prepare_enable(dcmi->mclk);
2079*4882a593Smuzhiyun 	if (ret)
2080*4882a593Smuzhiyun 		dev_err(dev, "%s: Failed to prepare_enable clock\n", __func__);
2081*4882a593Smuzhiyun 
2082*4882a593Smuzhiyun 	return ret;
2083*4882a593Smuzhiyun }
2084*4882a593Smuzhiyun 
dcmi_suspend(struct device * dev)2085*4882a593Smuzhiyun static __maybe_unused int dcmi_suspend(struct device *dev)
2086*4882a593Smuzhiyun {
2087*4882a593Smuzhiyun 	/* disable clock */
2088*4882a593Smuzhiyun 	pm_runtime_force_suspend(dev);
2089*4882a593Smuzhiyun 
2090*4882a593Smuzhiyun 	/* change pinctrl state */
2091*4882a593Smuzhiyun 	pinctrl_pm_select_sleep_state(dev);
2092*4882a593Smuzhiyun 
2093*4882a593Smuzhiyun 	return 0;
2094*4882a593Smuzhiyun }
2095*4882a593Smuzhiyun 
dcmi_resume(struct device * dev)2096*4882a593Smuzhiyun static __maybe_unused int dcmi_resume(struct device *dev)
2097*4882a593Smuzhiyun {
2098*4882a593Smuzhiyun 	/* restore pinctl default state */
2099*4882a593Smuzhiyun 	pinctrl_pm_select_default_state(dev);
2100*4882a593Smuzhiyun 
2101*4882a593Smuzhiyun 	/* clock enable */
2102*4882a593Smuzhiyun 	pm_runtime_force_resume(dev);
2103*4882a593Smuzhiyun 
2104*4882a593Smuzhiyun 	return 0;
2105*4882a593Smuzhiyun }
2106*4882a593Smuzhiyun 
2107*4882a593Smuzhiyun static const struct dev_pm_ops dcmi_pm_ops = {
2108*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(dcmi_suspend, dcmi_resume)
2109*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(dcmi_runtime_suspend,
2110*4882a593Smuzhiyun 			   dcmi_runtime_resume, NULL)
2111*4882a593Smuzhiyun };
2112*4882a593Smuzhiyun 
2113*4882a593Smuzhiyun static struct platform_driver stm32_dcmi_driver = {
2114*4882a593Smuzhiyun 	.probe		= dcmi_probe,
2115*4882a593Smuzhiyun 	.remove		= dcmi_remove,
2116*4882a593Smuzhiyun 	.driver		= {
2117*4882a593Smuzhiyun 		.name = DRV_NAME,
2118*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(stm32_dcmi_of_match),
2119*4882a593Smuzhiyun 		.pm = &dcmi_pm_ops,
2120*4882a593Smuzhiyun 	},
2121*4882a593Smuzhiyun };
2122*4882a593Smuzhiyun 
2123*4882a593Smuzhiyun module_platform_driver(stm32_dcmi_driver);
2124*4882a593Smuzhiyun 
2125*4882a593Smuzhiyun MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
2126*4882a593Smuzhiyun MODULE_AUTHOR("Hugues Fruchet <hugues.fruchet@st.com>");
2127*4882a593Smuzhiyun MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface driver");
2128*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2129*4882a593Smuzhiyun MODULE_SUPPORTED_DEVICE("video");
2130