1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register definition file for Samsung MFC V8.x Interface (FIMV) driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * http://www.samsung.com/ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _REGS_MFC_V8_H 10*4882a593Smuzhiyun #define _REGS_MFC_V8_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/sizes.h> 13*4882a593Smuzhiyun #include "regs-mfc-v7.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Additional registers for v8 */ 16*4882a593Smuzhiyun #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104 17*4882a593Smuzhiyun #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108 18*4882a593Smuzhiyun #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 19*4882a593Smuzhiyun #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 20*4882a593Smuzhiyun #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138 23*4882a593Smuzhiyun #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160 26*4882a593Smuzhiyun #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260 27*4882a593Smuzhiyun #define S5P_FIMV_D_MV_BUFFER_V8 0xf460 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define S5P_FIMV_D_NUM_MV_V8 0xf134 30*4882a593Smuzhiyun #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560 33*4882a593Smuzhiyun #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0 36*4882a593Smuzhiyun #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4 37*4882a593Smuzhiyun #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc 38*4882a593Smuzhiyun #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0 39*4882a593Smuzhiyun #define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4 40*4882a593Smuzhiyun #define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Display information register */ 43*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600 44*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Display status */ 47*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c 50*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618 53*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c 54*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620 55*4882a593Smuzhiyun #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Decoded picture information register */ 58*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_STATUS_V8 0xf644 59*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648 60*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c 61*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650 62*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654 63*4882a593Smuzhiyun #define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Returned value register for specific setting */ 66*4882a593Smuzhiyun #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674 67*4882a593Smuzhiyun #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678 68*4882a593Smuzhiyun #define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SEI related information */ 71*4882a593Smuzhiyun #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Encoder Registers */ 74*4882a593Smuzhiyun #define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf794 75*4882a593Smuzhiyun #define S5P_FIMV_E_RC_CONFIG_V8 0xf798 76*4882a593Smuzhiyun #define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c 77*4882a593Smuzhiyun #define S5P_FIMV_E_RC_RPARAM_V8 0xf7a4 78*4882a593Smuzhiyun #define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a8 79*4882a593Smuzhiyun #define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac 80*4882a593Smuzhiyun #define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b4 81*4882a593Smuzhiyun #define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b8 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c 84*4882a593Smuzhiyun #define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790 85*4882a593Smuzhiyun #define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf894 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c 88*4882a593Smuzhiyun #define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50 89*4882a593Smuzhiyun #define S5P_FIMV_E_H264_OPTIONS_V8 0xfb54 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* MFCv8 Context buffer sizes */ 92*4882a593Smuzhiyun #define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */ 93*4882a593Smuzhiyun #define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */ 94*4882a593Smuzhiyun #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */ 95*4882a593Smuzhiyun #define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */ 96*4882a593Smuzhiyun #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Buffer size defines */ 99*4882a593Smuzhiyun #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176) 102*4882a593Smuzhiyun #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \ 103*4882a593Smuzhiyun (((w) * 576 + (h) * 128) + 4128) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \ 106*4882a593Smuzhiyun (((w) * 592) + 2336) 107*4882a593Smuzhiyun #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \ 108*4882a593Smuzhiyun (((w) * 576) + 10512 + \ 109*4882a593Smuzhiyun ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4)) 110*4882a593Smuzhiyun #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \ 111*4882a593Smuzhiyun ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \ 112*4882a593Smuzhiyun + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* BUffer alignment defines */ 115*4882a593Smuzhiyun #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* MFCv8 variant defines */ 118*4882a593Smuzhiyun #define MAX_FW_SIZE_V8 (SZ_512K) /* 512KB */ 119*4882a593Smuzhiyun #define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */ 120*4882a593Smuzhiyun #define MFC_VERSION_V8 0x80 121*4882a593Smuzhiyun #define MFC_NUM_PORTS_V8 1 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /*_REGS_MFC_V8_H*/ 124