1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2017 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com/ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Register definition file for Samsung MFC V10.x Interface (FIMV) driver 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _REGS_MFC_V10_H 12*4882a593Smuzhiyun #define _REGS_MFC_V10_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/sizes.h> 15*4882a593Smuzhiyun #include "regs-mfc-v8.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MFCv10 register definitions*/ 18*4882a593Smuzhiyun #define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120 19*4882a593Smuzhiyun #define S5P_FIMV_MFC_STATE_V10 0x7124 20*4882a593Smuzhiyun #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10 0xF570 21*4882a593Smuzhiyun #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10 0xF574 22*4882a593Smuzhiyun #define S5P_FIMV_E_NUM_T_LAYER_V10 0xFBAC 23*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10 0xFBB0 24*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10 0xFBB4 25*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10 0xFBB8 26*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10 0xFBBC 27*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10 0xFBC0 28*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10 0xFBC4 29*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10 0xFBC8 30*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10 0xFD18 31*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10 0xFD1C 32*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10 0xFD20 33*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10 0xFD24 34*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10 0xFD28 35*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10 0xFD2C 36*4882a593Smuzhiyun #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10 0xFD30 37*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_OPTIONS_V10 0xFDD4 38*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10 0xFDD8 39*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10 0xFDDC 40*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10 0xFDE0 41*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10 0xFDE4 42*4882a593Smuzhiyun #define S5P_FIMV_E_HEVC_NAL_CONTROL_V10 0xFDE8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* MFCv10 Context buffer sizes */ 45*4882a593Smuzhiyun #define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K) 46*4882a593Smuzhiyun #define MFC_H264_DEC_CTX_BUF_SIZE_V10 (2 * SZ_1M) 47*4882a593Smuzhiyun #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10 (20 * SZ_1K) 48*4882a593Smuzhiyun #define MFC_H264_ENC_CTX_BUF_SIZE_V10 (100 * SZ_1K) 49*4882a593Smuzhiyun #define MFC_HEVC_ENC_CTX_BUF_SIZE_V10 (30 * SZ_1K) 50*4882a593Smuzhiyun #define MFC_OTHER_ENC_CTX_BUF_SIZE_V10 (15 * SZ_1K) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* MFCv10 variant defines */ 53*4882a593Smuzhiyun #define MAX_FW_SIZE_V10 (SZ_1M) 54*4882a593Smuzhiyun #define MAX_CPB_SIZE_V10 (3 * SZ_1M) 55*4882a593Smuzhiyun #define MFC_VERSION_V10 0xA0 56*4882a593Smuzhiyun #define MFC_NUM_PORTS_V10 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* MFCv10 codec defines*/ 59*4882a593Smuzhiyun #define S5P_FIMV_CODEC_HEVC_DEC 17 60*4882a593Smuzhiyun #define S5P_FIMV_CODEC_VP9_DEC 18 61*4882a593Smuzhiyun #define S5P_FIMV_CODEC_HEVC_ENC 26 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Decoder buffer size for MFC v10 */ 64*4882a593Smuzhiyun #define DEC_VP9_STATIC_BUFFER_SIZE 20480 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Encoder buffer size for MFC v10.0 */ 67*4882a593Smuzhiyun #define ENC_V100_BASE_SIZE(x, y) \ 68*4882a593Smuzhiyun (((x + 3) * (y + 3) * 8) \ 69*4882a593Smuzhiyun + ((y * 64) + 1280) * DIV_ROUND_UP(x, 8)) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define ENC_V100_H264_ME_SIZE(x, y) \ 72*4882a593Smuzhiyun (ENC_V100_BASE_SIZE(x, y) \ 73*4882a593Smuzhiyun + (DIV_ROUND_UP(x * y, 64) * 32)) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define ENC_V100_MPEG4_ME_SIZE(x, y) \ 76*4882a593Smuzhiyun (ENC_V100_BASE_SIZE(x, y) \ 77*4882a593Smuzhiyun + (DIV_ROUND_UP(x * y, 128) * 16)) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define ENC_V100_VP8_ME_SIZE(x, y) \ 80*4882a593Smuzhiyun ENC_V100_BASE_SIZE(x, y) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define ENC_V100_HEVC_ME_SIZE(x, y) \ 83*4882a593Smuzhiyun (((x + 3) * (y + 3) * 32) \ 84*4882a593Smuzhiyun + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4)) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /*_REGS_MFC_V10_H*/ 87*4882a593Smuzhiyun 88