1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun * Author: Jacob Chen <jacob-chen@iotwrt.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #ifndef __RGA_H__
7*4882a593Smuzhiyun #define __RGA_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
11*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
12*4882a593Smuzhiyun #include <media/v4l2-device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define RGA_NAME "rockchip-rga"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct rga_fmt {
17*4882a593Smuzhiyun u32 fourcc;
18*4882a593Smuzhiyun int depth;
19*4882a593Smuzhiyun u8 uv_factor;
20*4882a593Smuzhiyun u8 y_div;
21*4882a593Smuzhiyun u8 x_div;
22*4882a593Smuzhiyun u8 color_swap;
23*4882a593Smuzhiyun u8 hw_format;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct rga_frame {
27*4882a593Smuzhiyun /* Original dimensions */
28*4882a593Smuzhiyun u32 width;
29*4882a593Smuzhiyun u32 height;
30*4882a593Smuzhiyun u32 colorspace;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Crop */
33*4882a593Smuzhiyun struct v4l2_rect crop;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Image format */
36*4882a593Smuzhiyun struct rga_fmt *fmt;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Variables that can calculated once and reused */
39*4882a593Smuzhiyun u32 stride;
40*4882a593Smuzhiyun u32 size;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct rockchip_rga_version {
44*4882a593Smuzhiyun u32 major;
45*4882a593Smuzhiyun u32 minor;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct rga_ctx {
49*4882a593Smuzhiyun struct v4l2_fh fh;
50*4882a593Smuzhiyun struct rockchip_rga *rga;
51*4882a593Smuzhiyun struct rga_frame in;
52*4882a593Smuzhiyun struct rga_frame out;
53*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Control values */
56*4882a593Smuzhiyun u32 op;
57*4882a593Smuzhiyun u32 hflip;
58*4882a593Smuzhiyun u32 vflip;
59*4882a593Smuzhiyun u32 rotate;
60*4882a593Smuzhiyun u32 fill_color;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct rockchip_rga {
64*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
65*4882a593Smuzhiyun struct v4l2_m2m_dev *m2m_dev;
66*4882a593Smuzhiyun struct video_device *vfd;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun struct device *dev;
69*4882a593Smuzhiyun struct regmap *grf;
70*4882a593Smuzhiyun void __iomem *regs;
71*4882a593Smuzhiyun struct clk *sclk;
72*4882a593Smuzhiyun struct clk *aclk;
73*4882a593Smuzhiyun struct clk *hclk;
74*4882a593Smuzhiyun struct rockchip_rga_version version;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* vfd lock */
77*4882a593Smuzhiyun struct mutex mutex;
78*4882a593Smuzhiyun /* ctrl parm lock */
79*4882a593Smuzhiyun spinlock_t ctrl_lock;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct rga_ctx *curr;
82*4882a593Smuzhiyun dma_addr_t cmdbuf_phy;
83*4882a593Smuzhiyun void *cmdbuf_virt;
84*4882a593Smuzhiyun unsigned int *src_mmu_pages;
85*4882a593Smuzhiyun unsigned int *dst_mmu_pages;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* RGA Buffers Manage */
91*4882a593Smuzhiyun extern const struct vb2_ops rga_qops;
92*4882a593Smuzhiyun void rga_buf_map(struct vb2_buffer *vb);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* RGA Hardware */
rga_write(struct rockchip_rga * rga,u32 reg,u32 value)95*4882a593Smuzhiyun static inline void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun writel(value, rga->regs + reg);
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
rga_read(struct rockchip_rga * rga,u32 reg)100*4882a593Smuzhiyun static inline u32 rga_read(struct rockchip_rga *rga, u32 reg)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun return readl(rga->regs + reg);
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
rga_mod(struct rockchip_rga * rga,u32 reg,u32 val,u32 mask)105*4882a593Smuzhiyun static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun u32 temp = rga_read(rga, reg) & ~(mask);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun temp |= val & mask;
110*4882a593Smuzhiyun rga_write(rga, reg, temp);
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun void rga_hw_start(struct rockchip_rga *rga);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #endif
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