1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _RKISPP_ISPP_H 5*4882a593Smuzhiyun #define _RKISPP_ISPP_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "common.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GRP_ID_ISPP BIT(0) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum rkispp_pad { 12*4882a593Smuzhiyun RKISPP_PAD_SINK, 13*4882a593Smuzhiyun RKISPP_PAD_SINK_PARAMS, 14*4882a593Smuzhiyun RKISPP_PAD_SOURCE, 15*4882a593Smuzhiyun RKISPP_PAD_SOURCE_STATS, 16*4882a593Smuzhiyun RKISPP_PAD_MAX 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum rkispp_state { 20*4882a593Smuzhiyun ISPP_STOP = 0, 21*4882a593Smuzhiyun ISPP_START, 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct isppsd_fmt { 25*4882a593Smuzhiyun u32 mbus_code; 26*4882a593Smuzhiyun u32 fourcc; 27*4882a593Smuzhiyun u32 width; 28*4882a593Smuzhiyun u32 height; 29*4882a593Smuzhiyun u8 wr_fmt; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct rkispp_subdev { 33*4882a593Smuzhiyun struct rkispp_device *dev; 34*4882a593Smuzhiyun struct v4l2_subdev sd; 35*4882a593Smuzhiyun struct v4l2_subdev *remote_sd; 36*4882a593Smuzhiyun struct media_pad pads[RKISPP_PAD_MAX]; 37*4882a593Smuzhiyun struct v4l2_mbus_framefmt in_fmt; 38*4882a593Smuzhiyun struct isppsd_fmt out_fmt; 39*4882a593Smuzhiyun u32 frm_sync_seq; 40*4882a593Smuzhiyun /* timestamp in ns */ 41*4882a593Smuzhiyun u64 frame_timestamp; 42*4882a593Smuzhiyun enum rkispp_state state; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun u32 cal_fec_mesh(u32 width, u32 height, u32 mode); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun int rkispp_register_subdev(struct rkispp_device *dev, 48*4882a593Smuzhiyun struct v4l2_device *v4l2_dev); 49*4882a593Smuzhiyun void rkispp_unregister_subdev(struct rkispp_device *dev); 50*4882a593Smuzhiyun #endif 51