1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2020 Rockchip Electronics Co., Ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _RKISPP_HW_H 5*4882a593Smuzhiyun #define _RKISPP_HW_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "common.h" 8*4882a593Smuzhiyun #include "fec.h" 9*4882a593Smuzhiyun #include "../isp/isp_ispp.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ISPP_MAX_BUS_CLK 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct ispp_clk_info { 14*4882a593Smuzhiyun u32 clk_rate; 15*4882a593Smuzhiyun u32 refer_data; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct ispp_match_data { 19*4882a593Smuzhiyun int clks_num; 20*4882a593Smuzhiyun const char * const *clks; 21*4882a593Smuzhiyun int clk_rate_tbl_num; 22*4882a593Smuzhiyun const struct ispp_clk_info *clk_rate_tbl; 23*4882a593Smuzhiyun enum rkispp_ver ispp_ver; 24*4882a593Smuzhiyun struct irqs_data *irqs; 25*4882a593Smuzhiyun int num_irqs; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct rkispp_hw_dev { 29*4882a593Smuzhiyun struct device *dev; 30*4882a593Smuzhiyun void __iomem *base_addr; 31*4882a593Smuzhiyun const struct ispp_match_data *match_data; 32*4882a593Smuzhiyun const struct ispp_clk_info *clk_rate_tbl; 33*4882a593Smuzhiyun struct reset_control *reset; 34*4882a593Smuzhiyun struct clk *clks[ISPP_MAX_BUS_CLK]; 35*4882a593Smuzhiyun struct rkispp_device *ispp[DEV_MAX]; 36*4882a593Smuzhiyun struct rkispp_isp_buf_pool pool[RKISPP_BUF_POOL_MAX]; 37*4882a593Smuzhiyun struct rkispp_dummy_buffer dummy_buf; 38*4882a593Smuzhiyun struct rkispp_fec_dev fec_dev; 39*4882a593Smuzhiyun struct max_input max_in; 40*4882a593Smuzhiyun struct list_head list; 41*4882a593Smuzhiyun int clk_rate_tbl_num; 42*4882a593Smuzhiyun int clks_num; 43*4882a593Smuzhiyun int dev_num; 44*4882a593Smuzhiyun int cur_dev_id; 45*4882a593Smuzhiyun unsigned long core_clk_min; 46*4882a593Smuzhiyun unsigned long core_clk_max; 47*4882a593Smuzhiyun enum rkispp_ver ispp_ver; 48*4882a593Smuzhiyun /* lock for irq */ 49*4882a593Smuzhiyun spinlock_t irq_lock; 50*4882a593Smuzhiyun /* lock for multi dev */ 51*4882a593Smuzhiyun struct mutex dev_lock; 52*4882a593Smuzhiyun spinlock_t buf_lock; 53*4882a593Smuzhiyun atomic_t refcnt; 54*4882a593Smuzhiyun const struct vb2_mem_ops *mem_ops; 55*4882a593Smuzhiyun struct rkisp_ispp_reg *reg_buf; 56*4882a593Smuzhiyun bool is_mmu; 57*4882a593Smuzhiyun bool is_idle; 58*4882a593Smuzhiyun bool is_single; 59*4882a593Smuzhiyun bool is_fec_ext; 60*4882a593Smuzhiyun bool is_dma_contig; 61*4882a593Smuzhiyun bool is_dma_sg_ops; 62*4882a593Smuzhiyun bool is_shutdown; 63*4882a593Smuzhiyun bool is_first; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun void rkispp_soft_reset(struct rkispp_hw_dev *hw_dev); 67*4882a593Smuzhiyun #endif 68