1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2020 Rockchip Electronics Co., Ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _RKISP_HW_H 5*4882a593Smuzhiyun #define _RKISP_HW_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "bridge.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define RKISP_MAX_BUS_CLK 10 10*4882a593Smuzhiyun #define RKISP_MAX_RETRY_CNT 5 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct isp_clk_info { 13*4882a593Smuzhiyun u32 clk_rate; 14*4882a593Smuzhiyun u32 refer_data; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct isp_match_data { 18*4882a593Smuzhiyun const char * const *clks; 19*4882a593Smuzhiyun int num_clks; 20*4882a593Smuzhiyun enum rkisp_isp_ver isp_ver; 21*4882a593Smuzhiyun const struct isp_clk_info *clk_rate_tbl; 22*4882a593Smuzhiyun int num_clk_rate_tbl; 23*4882a593Smuzhiyun struct isp_irqs_data *irqs; 24*4882a593Smuzhiyun int num_irqs; 25*4882a593Smuzhiyun bool unite; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct rkisp_monitor { 29*4882a593Smuzhiyun struct rkisp_hw_dev *dev; 30*4882a593Smuzhiyun struct work_struct work; 31*4882a593Smuzhiyun struct completion cmpl; 32*4882a593Smuzhiyun int (*reset_handle)(struct rkisp_device *dev); 33*4882a593Smuzhiyun u32 state; 34*4882a593Smuzhiyun u8 retry; 35*4882a593Smuzhiyun bool is_en; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct rkisp_sram { 39*4882a593Smuzhiyun dma_addr_t dma_addr; 40*4882a593Smuzhiyun u32 size; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct rkisp_size_info { 44*4882a593Smuzhiyun u32 w; 45*4882a593Smuzhiyun u32 h; 46*4882a593Smuzhiyun u32 size; 47*4882a593Smuzhiyun u32 fps; 48*4882a593Smuzhiyun bool is_on; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct rkisp_hw_dev { 52*4882a593Smuzhiyun const struct isp_match_data *match_data; 53*4882a593Smuzhiyun struct platform_device *pdev; 54*4882a593Smuzhiyun struct device *dev; 55*4882a593Smuzhiyun struct regmap *grf; 56*4882a593Smuzhiyun void __iomem *base_addr; 57*4882a593Smuzhiyun void __iomem *base_next_addr; 58*4882a593Smuzhiyun struct clk *clks[RKISP_MAX_BUS_CLK]; 59*4882a593Smuzhiyun int num_clks; 60*4882a593Smuzhiyun const struct isp_clk_info *clk_rate_tbl; 61*4882a593Smuzhiyun int num_clk_rate_tbl; 62*4882a593Smuzhiyun struct reset_control *reset; 63*4882a593Smuzhiyun int mipi_irq; 64*4882a593Smuzhiyun enum rkisp_isp_ver isp_ver; 65*4882a593Smuzhiyun struct rkisp_device *isp[DEV_MAX]; 66*4882a593Smuzhiyun struct rkisp_size_info isp_size[DEV_MAX]; 67*4882a593Smuzhiyun int dev_num; 68*4882a593Smuzhiyun int dev_link_num; 69*4882a593Smuzhiyun int cur_dev_id; 70*4882a593Smuzhiyun int pre_dev_id; 71*4882a593Smuzhiyun int mipi_dev_id; 72*4882a593Smuzhiyun struct max_input max_in; 73*4882a593Smuzhiyun /* lock for multi dev */ 74*4882a593Smuzhiyun struct mutex dev_lock; 75*4882a593Smuzhiyun spinlock_t rdbk_lock; 76*4882a593Smuzhiyun atomic_t refcnt; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct rkisp_sram sram; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* share buf for multi dev */ 81*4882a593Smuzhiyun spinlock_t buf_lock; 82*4882a593Smuzhiyun struct rkisp_bridge_buf bufs[BRIDGE_BUF_MAX]; 83*4882a593Smuzhiyun struct rkisp_ispp_buf *cur_buf; 84*4882a593Smuzhiyun struct rkisp_ispp_buf *nxt_buf; 85*4882a593Smuzhiyun struct list_head list; 86*4882a593Smuzhiyun struct list_head rpt_list; 87*4882a593Smuzhiyun struct rkisp_dummy_buffer dummy_buf; 88*4882a593Smuzhiyun const struct vb2_mem_ops *mem_ops; 89*4882a593Smuzhiyun struct rkisp_monitor monitor; 90*4882a593Smuzhiyun u64 iq_feature; 91*4882a593Smuzhiyun int buf_init_cnt; 92*4882a593Smuzhiyun bool is_feature_on; 93*4882a593Smuzhiyun bool is_dma_contig; 94*4882a593Smuzhiyun bool is_dma_sg_ops; 95*4882a593Smuzhiyun bool is_mmu; 96*4882a593Smuzhiyun bool is_idle; 97*4882a593Smuzhiyun bool is_single; 98*4882a593Smuzhiyun bool is_mi_update; 99*4882a593Smuzhiyun bool is_thunderboot; 100*4882a593Smuzhiyun bool is_buf_init; 101*4882a593Smuzhiyun bool is_shutdown; 102*4882a593Smuzhiyun bool is_unite; 103*4882a593Smuzhiyun bool is_multi_overflow; 104*4882a593Smuzhiyun bool is_runing; 105*4882a593Smuzhiyun bool is_frm_buf; 106*4882a593Smuzhiyun bool is_dvfs; 107*4882a593Smuzhiyun bool is_assigned_clk; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun int rkisp_register_irq(struct rkisp_hw_dev *dev); 111*4882a593Smuzhiyun void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure); 112*4882a593Smuzhiyun void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev); 113*4882a593Smuzhiyun #endif 114