1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _RKISP_DMARX_H 5*4882a593Smuzhiyun #define _RKISP_DMARX_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "capture.h" 8*4882a593Smuzhiyun #include "common.h" 9*4882a593Smuzhiyun #include "isp_external.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define DMA_VDEV_NAME DRIVER_NAME "_dmapath" 12*4882a593Smuzhiyun #define DMARX0_VDEV_NAME DRIVER_NAME "_rawrd0_m" 13*4882a593Smuzhiyun #define DMARX1_VDEV_NAME DRIVER_NAME "_rawrd1_l" 14*4882a593Smuzhiyun #define DMARX2_VDEV_NAME DRIVER_NAME "_rawrd2_s" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct rkisp_dmarx_device; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum { 19*4882a593Smuzhiyun RKISP_STREAM_DMARX, 20*4882a593Smuzhiyun RKISP_STREAM_RAWRD0, 21*4882a593Smuzhiyun RKISP_STREAM_RAWRD1, 22*4882a593Smuzhiyun RKISP_STREAM_RAWRD2, 23*4882a593Smuzhiyun RKISP_MAX_DMARX_STREAM, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum rkisp_dmarx_pad { 27*4882a593Smuzhiyun RKISP_DMARX_PAD_SINK, 28*4882a593Smuzhiyun RKISP_DMARX_PAD_SOURCE, 29*4882a593Smuzhiyun RKISP_DMARX_PAD_MAX 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun enum rkisp_dmarx_trigger { 33*4882a593Smuzhiyun T_AUTO = 0, 34*4882a593Smuzhiyun T_MANUAL, 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct rkisp_dmarx_frame { 38*4882a593Smuzhiyun u64 sof_timestamp; 39*4882a593Smuzhiyun u64 timestamp; 40*4882a593Smuzhiyun u32 id; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct rkisp_rx_buf_pool { 44*4882a593Smuzhiyun struct rkisp_buffer buf; 45*4882a593Smuzhiyun struct rkisp_rx_buf *dbufs; 46*4882a593Smuzhiyun void *mem_priv; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * struct rkisp_dmarx_device 51*4882a593Smuzhiyun * trigger: read back mode 52*4882a593Smuzhiyun * cur_frame: current frame id and timestamp in ns 53*4882a593Smuzhiyun * pre_frame: previous frame id and timestamp in ns 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct rkisp_dmarx_device { 56*4882a593Smuzhiyun struct rkisp_device *ispdev; 57*4882a593Smuzhiyun struct rkisp_stream stream[RKISP_MAX_DMARX_STREAM]; 58*4882a593Smuzhiyun enum rkisp_dmarx_trigger trigger; 59*4882a593Smuzhiyun struct rkisp_dmarx_frame cur_frame; 60*4882a593Smuzhiyun struct rkisp_dmarx_frame pre_frame; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void rkisp_dmarx_isr(u32 mis_val, struct rkisp_device *dev); 64*4882a593Smuzhiyun void rkisp2_rawrd_isr(u32 mis_val, struct rkisp_device *dev); 65*4882a593Smuzhiyun void rkisp_dmarx_set_fmt(struct rkisp_stream *stream, 66*4882a593Smuzhiyun struct v4l2_pix_format_mplane pixm); 67*4882a593Smuzhiyun void rkisp_rawrd_set_pic_size(struct rkisp_device *dev, 68*4882a593Smuzhiyun u32 width, u32 height); 69*4882a593Smuzhiyun void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id, 70*4882a593Smuzhiyun u64 *sof_timestamp, u64 *timestamp, 71*4882a593Smuzhiyun bool sync); 72*4882a593Smuzhiyun void rkisp_unregister_dmarx_vdev(struct rkisp_device *dev); 73*4882a593Smuzhiyun int rkisp_register_dmarx_vdev(struct rkisp_device *dev); 74*4882a593Smuzhiyun #endif /* _RKISP_DMARX_H */ 75