1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Rockchip isp1 driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This software is available to you under a choice of one of two 7*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 8*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 9*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 10*4882a593Smuzhiyun * OpenIB.org BSD license below: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 13*4882a593Smuzhiyun * without modification, are permitted provided that the following 14*4882a593Smuzhiyun * conditions are met: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * - Redistributions of source code must retain the above 17*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 18*4882a593Smuzhiyun * disclaimer. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 21*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 22*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 23*4882a593Smuzhiyun * provided with the distribution. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32*4882a593Smuzhiyun * SOFTWARE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef _RKISP_PATH_VIDEO_H 36*4882a593Smuzhiyun #define _RKISP_PATH_VIDEO_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include <linux/interrupt.h> 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #include "common.h" 41*4882a593Smuzhiyun #include "capture_v1x.h" 42*4882a593Smuzhiyun #include "capture_v2x.h" 43*4882a593Smuzhiyun #include "capture_v3x.h" 44*4882a593Smuzhiyun #include "isp_ispp.h" 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define SP_VDEV_NAME DRIVER_NAME "_selfpath" 47*4882a593Smuzhiyun #define MP_VDEV_NAME DRIVER_NAME "_mainpath" 48*4882a593Smuzhiyun #define FBC_VDEV_NAME DRIVER_NAME "_fbcpath" 49*4882a593Smuzhiyun #define BP_VDEV_NAME DRIVER_NAME "_bypasspath" 50*4882a593Smuzhiyun #define MPDS_VDEV_NAME DRIVER_NAME "_mainpath_4x4sampling" 51*4882a593Smuzhiyun #define BPDS_VDEV_NAME DRIVER_NAME "_bypasspath_4x4sampling" 52*4882a593Smuzhiyun #define LUMA_VDEV_NAME DRIVER_NAME "_lumapath" 53*4882a593Smuzhiyun #define VIR_VDEV_NAME DRIVER_NAME "_iqtool" 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define DMATX0_VDEV_NAME DRIVER_NAME "_rawwr0" 56*4882a593Smuzhiyun #define DMATX1_VDEV_NAME DRIVER_NAME "_rawwr1" 57*4882a593Smuzhiyun #define DMATX2_VDEV_NAME DRIVER_NAME "_rawwr2" 58*4882a593Smuzhiyun #define DMATX3_VDEV_NAME DRIVER_NAME "_rawwr3" 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct rkisp_stream; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum { 63*4882a593Smuzhiyun ROCKIT_DVBM_END, 64*4882a593Smuzhiyun ROCKIT_DVBM_START, 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun enum { 68*4882a593Smuzhiyun RDBK_L, 69*4882a593Smuzhiyun RDBK_M, 70*4882a593Smuzhiyun RDBK_S, 71*4882a593Smuzhiyun RDBK_MAX, 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun enum { 75*4882a593Smuzhiyun RKISP_STREAM_MP, 76*4882a593Smuzhiyun RKISP_STREAM_SP, 77*4882a593Smuzhiyun RKISP_STREAM_DMATX0, 78*4882a593Smuzhiyun RKISP_STREAM_DMATX1, 79*4882a593Smuzhiyun RKISP_STREAM_DMATX2, 80*4882a593Smuzhiyun RKISP_STREAM_DMATX3, 81*4882a593Smuzhiyun RKISP_STREAM_FBC, 82*4882a593Smuzhiyun RKISP_STREAM_BP, 83*4882a593Smuzhiyun RKISP_STREAM_MPDS, 84*4882a593Smuzhiyun RKISP_STREAM_BPDS, 85*4882a593Smuzhiyun RKISP_STREAM_LUMA, 86*4882a593Smuzhiyun RKISP_STREAM_VIR, 87*4882a593Smuzhiyun RKISP_MAX_STREAM, 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * @fourcc: pixel format 92*4882a593Smuzhiyun * @mbus_code: pixel format over bus 93*4882a593Smuzhiyun * @fmt_type: helper filed for pixel format 94*4882a593Smuzhiyun * @bpp: bits per pixel 95*4882a593Smuzhiyun * @bayer_pat: bayer patten type 96*4882a593Smuzhiyun * @cplanes: number of colour planes 97*4882a593Smuzhiyun * @mplanes: number of stored memory planes 98*4882a593Smuzhiyun * @uv_swap: if cb cr swaped, for yuv 99*4882a593Smuzhiyun * @write_format: defines how YCbCr self picture data is written to memory 100*4882a593Smuzhiyun * @input_format: defines sp input format 101*4882a593Smuzhiyun * @output_format: defines sp output format 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun struct capture_fmt { 104*4882a593Smuzhiyun u32 fourcc; 105*4882a593Smuzhiyun u32 mbus_code; 106*4882a593Smuzhiyun u8 fmt_type; 107*4882a593Smuzhiyun u8 cplanes; 108*4882a593Smuzhiyun u8 mplanes; 109*4882a593Smuzhiyun u8 uv_swap; 110*4882a593Smuzhiyun u32 write_format; 111*4882a593Smuzhiyun u32 output_format; 112*4882a593Smuzhiyun u8 bpp[VIDEO_MAX_PLANES]; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun enum rkisp_sp_inp { 116*4882a593Smuzhiyun RKISP_SP_INP_ISP, 117*4882a593Smuzhiyun RKISP_SP_INP_DMA_SP, 118*4882a593Smuzhiyun RKISP_SP_INP_MAX 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun enum rkisp_field { 122*4882a593Smuzhiyun RKISP_FIELD_ODD, 123*4882a593Smuzhiyun RKISP_FIELD_EVEN, 124*4882a593Smuzhiyun RKISP_FIELD_INVAL, 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct rkisp_stream_sp { 128*4882a593Smuzhiyun int y_stride; 129*4882a593Smuzhiyun int vir_offs; 130*4882a593Smuzhiyun enum rkisp_sp_inp input_sel; 131*4882a593Smuzhiyun enum rkisp_field field; 132*4882a593Smuzhiyun enum rkisp_field field_rec; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct rkisp_stream_mp { 136*4882a593Smuzhiyun bool raw_enable; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct rkisp_stream_dmatx { 140*4882a593Smuzhiyun u8 pre_stop; 141*4882a593Smuzhiyun u8 is_config; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct rkisp_stream_dmarx { 145*4882a593Smuzhiyun int y_stride; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Different config between selfpath and mainpath */ 149*4882a593Smuzhiyun struct stream_config { 150*4882a593Smuzhiyun const struct capture_fmt *fmts; 151*4882a593Smuzhiyun int fmt_size; 152*4882a593Smuzhiyun int max_rsz_width; 153*4882a593Smuzhiyun int max_rsz_height; 154*4882a593Smuzhiyun int min_rsz_width; 155*4882a593Smuzhiyun int min_rsz_height; 156*4882a593Smuzhiyun const int frame_end_id; 157*4882a593Smuzhiyun /* registers */ 158*4882a593Smuzhiyun struct { 159*4882a593Smuzhiyun u32 ctrl; 160*4882a593Smuzhiyun u32 ctrl_shd; 161*4882a593Smuzhiyun u32 scale_hy; 162*4882a593Smuzhiyun u32 scale_hcr; 163*4882a593Smuzhiyun u32 scale_hcb; 164*4882a593Smuzhiyun u32 scale_vy; 165*4882a593Smuzhiyun u32 scale_vc; 166*4882a593Smuzhiyun u32 scale_lut; 167*4882a593Smuzhiyun u32 scale_lut_addr; 168*4882a593Smuzhiyun u32 scale_hy_shd; 169*4882a593Smuzhiyun u32 scale_hcr_shd; 170*4882a593Smuzhiyun u32 scale_hcb_shd; 171*4882a593Smuzhiyun u32 scale_vy_shd; 172*4882a593Smuzhiyun u32 scale_vc_shd; 173*4882a593Smuzhiyun u32 phase_hy; 174*4882a593Smuzhiyun u32 phase_hc; 175*4882a593Smuzhiyun u32 phase_vy; 176*4882a593Smuzhiyun u32 phase_vc; 177*4882a593Smuzhiyun u32 phase_hy_shd; 178*4882a593Smuzhiyun u32 phase_hc_shd; 179*4882a593Smuzhiyun u32 phase_vy_shd; 180*4882a593Smuzhiyun u32 phase_vc_shd; 181*4882a593Smuzhiyun } rsz; 182*4882a593Smuzhiyun struct { 183*4882a593Smuzhiyun u32 ctrl; 184*4882a593Smuzhiyun u32 yuvmode_mask; 185*4882a593Smuzhiyun u32 rawmode_mask; 186*4882a593Smuzhiyun u32 h_offset; 187*4882a593Smuzhiyun u32 v_offset; 188*4882a593Smuzhiyun u32 h_size; 189*4882a593Smuzhiyun u32 v_size; 190*4882a593Smuzhiyun } dual_crop; 191*4882a593Smuzhiyun struct { 192*4882a593Smuzhiyun u32 y_size_init; 193*4882a593Smuzhiyun u32 cb_size_init; 194*4882a593Smuzhiyun u32 cr_size_init; 195*4882a593Smuzhiyun u32 y_base_ad_init; 196*4882a593Smuzhiyun u32 cb_base_ad_init; 197*4882a593Smuzhiyun u32 cr_base_ad_init; 198*4882a593Smuzhiyun u32 y_offs_cnt_init; 199*4882a593Smuzhiyun u32 cb_offs_cnt_init; 200*4882a593Smuzhiyun u32 cr_offs_cnt_init; 201*4882a593Smuzhiyun u32 y_base_ad_shd; 202*4882a593Smuzhiyun u32 length; 203*4882a593Smuzhiyun u32 ctrl; 204*4882a593Smuzhiyun u32 y_pic_size; 205*4882a593Smuzhiyun } mi; 206*4882a593Smuzhiyun struct { 207*4882a593Smuzhiyun u32 ctrl; 208*4882a593Smuzhiyun u32 pic_size; 209*4882a593Smuzhiyun u32 pic_offs; 210*4882a593Smuzhiyun } dma; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* Different reg ops between selfpath and mainpath */ 214*4882a593Smuzhiyun struct streams_ops { 215*4882a593Smuzhiyun int (*config_mi)(struct rkisp_stream *stream); 216*4882a593Smuzhiyun void (*stop_mi)(struct rkisp_stream *stream); 217*4882a593Smuzhiyun void (*enable_mi)(struct rkisp_stream *stream); 218*4882a593Smuzhiyun void (*disable_mi)(struct rkisp_stream *stream); 219*4882a593Smuzhiyun void (*set_data_path)(struct rkisp_stream *stream); 220*4882a593Smuzhiyun bool (*is_stream_stopped)(struct rkisp_stream *stream); 221*4882a593Smuzhiyun void (*update_mi)(struct rkisp_stream *stream); 222*4882a593Smuzhiyun int (*frame_end)(struct rkisp_stream *stream, u32 state); 223*4882a593Smuzhiyun int (*frame_start)(struct rkisp_stream *stream, u32 mis); 224*4882a593Smuzhiyun int (*set_wrap)(struct rkisp_stream *stream, int line); 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun struct rockit_isp_ops { 228*4882a593Smuzhiyun int (*rkisp_stream_start)(struct rkisp_stream *stream); 229*4882a593Smuzhiyun void (*rkisp_stream_stop)(struct rkisp_stream *stream); 230*4882a593Smuzhiyun int (*rkisp_set_fmt)(struct rkisp_stream *stream, 231*4882a593Smuzhiyun struct v4l2_pix_format_mplane *pixm, 232*4882a593Smuzhiyun bool try); 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* 236*4882a593Smuzhiyun * struct rkisp_stream - ISP capture video device 237*4882a593Smuzhiyun * 238*4882a593Smuzhiyun * @id: stream video identify 239*4882a593Smuzhiyun * @interlaced: selfpath interlaced flag 240*4882a593Smuzhiyun * @out_isp_fmt: output isp format 241*4882a593Smuzhiyun * @out_fmt: output buffer size 242*4882a593Smuzhiyun * @dcrop: coordinates of dual-crop 243*4882a593Smuzhiyun * 244*4882a593Smuzhiyun * @vbq_lock: lock to protect buf_queue 245*4882a593Smuzhiyun * @buf_queue: queued buffer list 246*4882a593Smuzhiyun * 247*4882a593Smuzhiyun * rkisp use shadowsock registers, so it need two buffer at a time 248*4882a593Smuzhiyun * @curr_buf: the buffer used for current frame 249*4882a593Smuzhiyun * @next_buf: the buffer used for next frame 250*4882a593Smuzhiyun * @linked: stream link to isp 251*4882a593Smuzhiyun * @done: wait frame end event queue 252*4882a593Smuzhiyun * @burst: burst length for Y and CB/CR 253*4882a593Smuzhiyun * @sequence: damtx video frame sequence 254*4882a593Smuzhiyun */ 255*4882a593Smuzhiyun struct rkisp_stream { 256*4882a593Smuzhiyun unsigned int id; 257*4882a593Smuzhiyun unsigned interlaced:1; 258*4882a593Smuzhiyun struct rkisp_device *ispdev; 259*4882a593Smuzhiyun struct rkisp_vdev_node vnode; 260*4882a593Smuzhiyun struct capture_fmt out_isp_fmt; 261*4882a593Smuzhiyun struct v4l2_pix_format_mplane out_fmt; 262*4882a593Smuzhiyun struct v4l2_rect dcrop; 263*4882a593Smuzhiyun struct streams_ops *ops; 264*4882a593Smuzhiyun struct stream_config *config; 265*4882a593Smuzhiyun spinlock_t vbq_lock; 266*4882a593Smuzhiyun struct list_head buf_queue; 267*4882a593Smuzhiyun struct rkisp_buffer *curr_buf; 268*4882a593Smuzhiyun struct rkisp_buffer *next_buf; 269*4882a593Smuzhiyun struct rkisp_dummy_buffer dummy_buf; 270*4882a593Smuzhiyun struct mutex apilock; 271*4882a593Smuzhiyun struct tasklet_struct buf_done_tasklet; 272*4882a593Smuzhiyun struct list_head buf_done_list; 273*4882a593Smuzhiyun bool streaming; 274*4882a593Smuzhiyun bool stopping; 275*4882a593Smuzhiyun bool frame_end; 276*4882a593Smuzhiyun bool linked; 277*4882a593Smuzhiyun bool start_stream; 278*4882a593Smuzhiyun bool is_mf_upd; 279*4882a593Smuzhiyun bool is_flip; 280*4882a593Smuzhiyun bool is_pause; 281*4882a593Smuzhiyun bool is_crop_upd; 282*4882a593Smuzhiyun bool is_using_resmem; 283*4882a593Smuzhiyun bool frame_early; 284*4882a593Smuzhiyun wait_queue_head_t done; 285*4882a593Smuzhiyun unsigned int burst; 286*4882a593Smuzhiyun atomic_t sequence; 287*4882a593Smuzhiyun struct frame_debug_info dbg; 288*4882a593Smuzhiyun int conn_id; 289*4882a593Smuzhiyun u32 memory; 290*4882a593Smuzhiyun u32 skip_frame; 291*4882a593Smuzhiyun union { 292*4882a593Smuzhiyun struct rkisp_stream_sp sp; 293*4882a593Smuzhiyun struct rkisp_stream_mp mp; 294*4882a593Smuzhiyun struct rkisp_stream_dmarx dmarx; 295*4882a593Smuzhiyun struct rkisp_stream_dmatx dmatx; 296*4882a593Smuzhiyun } u; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun struct rkisp_vir_cpy { 300*4882a593Smuzhiyun struct work_struct work; 301*4882a593Smuzhiyun struct completion cmpl; 302*4882a593Smuzhiyun struct list_head queue; 303*4882a593Smuzhiyun struct rkisp_stream *stream; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun struct rkisp_capture_device { 307*4882a593Smuzhiyun struct rkisp_device *ispdev; 308*4882a593Smuzhiyun struct rkisp_stream stream[RKISP_MAX_STREAM]; 309*4882a593Smuzhiyun struct rkisp_buffer *rdbk_buf[RDBK_MAX]; 310*4882a593Smuzhiyun struct rkisp_vir_cpy vir_cpy; 311*4882a593Smuzhiyun struct tasklet_struct rd_tasklet; 312*4882a593Smuzhiyun atomic_t refcnt; 313*4882a593Smuzhiyun u32 wait_line; 314*4882a593Smuzhiyun u32 wrap_width; 315*4882a593Smuzhiyun u32 wrap_line; 316*4882a593Smuzhiyun bool is_done_early; 317*4882a593Smuzhiyun bool is_mirror; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun struct work_struct fast_work; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun extern struct stream_config rkisp_mp_stream_config; 323*4882a593Smuzhiyun extern struct stream_config rkisp_sp_stream_config; 324*4882a593Smuzhiyun extern struct rockit_isp_ops rockit_isp_ops; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun void rkisp_stream_buf_done_early(struct rkisp_device *dev); 327*4882a593Smuzhiyun void rkisp_stream_buf_done(struct rkisp_stream *stream, 328*4882a593Smuzhiyun struct rkisp_buffer *buf); 329*4882a593Smuzhiyun void rkisp_unregister_stream_vdev(struct rkisp_stream *stream); 330*4882a593Smuzhiyun int rkisp_register_stream_vdev(struct rkisp_stream *stream); 331*4882a593Smuzhiyun void rkisp_unregister_stream_vdevs(struct rkisp_device *dev); 332*4882a593Smuzhiyun int rkisp_register_stream_vdevs(struct rkisp_device *dev); 333*4882a593Smuzhiyun void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev); 334*4882a593Smuzhiyun void rkisp_set_stream_def_fmt(struct rkisp_device *dev, u32 id, 335*4882a593Smuzhiyun u32 width, u32 height, u32 pixelformat); 336*4882a593Smuzhiyun int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis); 337*4882a593Smuzhiyun int rkisp_fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs); 338*4882a593Smuzhiyun int rkisp_mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs); 339*4882a593Smuzhiyun int rkisp_fh_open(struct file *filp); 340*4882a593Smuzhiyun int rkisp_fop_release(struct file *file); 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun int rkisp_get_tb_stream_info(struct rkisp_stream *stream, 343*4882a593Smuzhiyun struct rkisp_tb_stream_info *info); 344*4882a593Smuzhiyun int rkisp_free_tb_stream_buf(struct rkisp_stream *stream); 345*4882a593Smuzhiyun #endif /* _RKISP_PATH_VIDEO_H */ 346