1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include "dev.h"
13 #include "regs.h"
14 #include "rkisp_tb_helper.h"
15
16 #define STREAM_MAX_MP_RSZ_OUTPUT_WIDTH 4416
17 #define STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT 3312
18 #define STREAM_MAX_SP_RSZ_OUTPUT_WIDTH 1920
19 #define STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT 1080
20 #define STREAM_MIN_RSZ_OUTPUT_WIDTH 32
21 #define STREAM_MIN_RSZ_OUTPUT_HEIGHT 32
22 #define STREAM_OUTPUT_STEP_WISE 8
23
24 #define STREAM_MIN_MP_SP_INPUT_WIDTH STREAM_MIN_RSZ_OUTPUT_WIDTH
25 #define STREAM_MIN_MP_SP_INPUT_HEIGHT STREAM_MIN_RSZ_OUTPUT_HEIGHT
26
hdr_dma_frame(struct rkisp_device * dev)27 static int hdr_dma_frame(struct rkisp_device *dev)
28 {
29 int max_dma;
30
31 switch (dev->hdr.op_mode) {
32 case HDR_FRAMEX2_DDR:
33 case HDR_LINEX2_DDR:
34 case HDR_RDBK_FRAME1:
35 max_dma = 1;
36 break;
37 case HDR_FRAMEX3_DDR:
38 case HDR_LINEX3_DDR:
39 case HDR_RDBK_FRAME2:
40 max_dma = 2;
41 break;
42 case HDR_RDBK_FRAME3:
43 max_dma = HDR_DMA_MAX;
44 break;
45 case HDR_LINEX2_NO_DDR:
46 case HDR_NORMAL:
47 default:
48 max_dma = 0;
49 }
50 return max_dma;
51 }
52
rkisp_create_hdr_buf(struct rkisp_device * dev)53 static int rkisp_create_hdr_buf(struct rkisp_device *dev)
54 {
55 int i, j, max_dma, max_buf = 1;
56 struct rkisp_dummy_buffer *buf;
57 struct rkisp_stream *stream;
58 u32 size;
59
60 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
61 size = stream->out_fmt.plane_fmt[0].sizeimage;
62 max_dma = hdr_dma_frame(dev);
63 /* hdr read back mode using base and shd address
64 * this support multi-buffer
65 */
66 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
67 if (!dev->dmarx_dev.trigger)
68 max_buf = HDR_MAX_DUMMY_BUF;
69 else
70 max_buf = 0;
71 }
72 for (i = 0; i < max_dma; i++) {
73 for (j = 0; j < max_buf; j++) {
74 buf = &dev->hdr.dummy_buf[i][j];
75 buf->size = size;
76 if (rkisp_alloc_buffer(dev, buf) < 0) {
77 v4l2_err(&dev->v4l2_dev,
78 "Failed to allocate the memory for hdr buffer\n");
79 return -ENOMEM;
80 }
81 hdr_qbuf(&dev->hdr.q_tx[i], buf);
82 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
83 "hdr buf[%d][%d]:0x%x\n",
84 i, j, (u32)buf->dma_addr);
85 }
86 dev->hdr.index[i] = i;
87 }
88 /*
89 * normal: q_tx[0] to dma0
90 * q_tx[1] to dma1
91 * rdbk1: using dma2
92 q_tx[0] to dma2
93 * rdbk2: using dma0 (as M), dma2 (as S)
94 * q_tx[0] to dma0
95 * q_tx[1] to dma2
96 * rdbk3: using dma0 (as M), dam1 (as L), dma2 (as S)
97 * q_tx[0] to dma0
98 * q_tx[1] to dma1
99 * q_tx[2] to dma2
100 */
101 if (dev->hdr.op_mode == HDR_RDBK_FRAME1) {
102 dev->hdr.index[HDR_DMA2] = 0;
103 dev->hdr.index[HDR_DMA0] = 1;
104 dev->hdr.index[HDR_DMA1] = 2;
105 } else if (dev->hdr.op_mode == HDR_RDBK_FRAME2) {
106 dev->hdr.index[HDR_DMA0] = 0;
107 dev->hdr.index[HDR_DMA2] = 1;
108 dev->hdr.index[HDR_DMA1] = 2;
109 }
110
111 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
112 "hdr:%d buf index dma0:%d dma1:%d dma2:%d\n",
113 max_dma,
114 dev->hdr.index[HDR_DMA0],
115 dev->hdr.index[HDR_DMA1],
116 dev->hdr.index[HDR_DMA2]);
117 return 0;
118 }
119
hdr_destroy_buf(struct rkisp_device * dev)120 void hdr_destroy_buf(struct rkisp_device *dev)
121 {
122 int i, j;
123 struct rkisp_dummy_buffer *buf;
124
125 if (atomic_read(&dev->cap_dev.refcnt) > 1 ||
126 !dev->active_sensor ||
127 (dev->active_sensor &&
128 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
129 (dev->isp_inp & INP_CIF) ||
130 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
131 return;
132
133 atomic_set(&dev->hdr.refcnt, 0);
134 for (i = 0; i < HDR_DMA_MAX; i++) {
135 buf = dev->hdr.rx_cur_buf[i];
136 if (buf) {
137 rkisp_free_buffer(dev, buf);
138 dev->hdr.rx_cur_buf[i] = NULL;
139 }
140
141 for (j = 0; j < HDR_MAX_DUMMY_BUF; j++) {
142 buf = hdr_dqbuf(&dev->hdr.q_tx[i]);
143 if (buf)
144 rkisp_free_buffer(dev, buf);
145 buf = hdr_dqbuf(&dev->hdr.q_rx[i]);
146 if (buf)
147 rkisp_free_buffer(dev, buf);
148 }
149 }
150 }
151
hdr_update_dmatx_buf(struct rkisp_device * dev)152 int hdr_update_dmatx_buf(struct rkisp_device *dev)
153 {
154 void __iomem *base = dev->base_addr;
155 struct rkisp_stream *dmatx;
156 struct rkisp_dummy_buffer *buf;
157 u8 i, index;
158
159 if (!dev->active_sensor ||
160 (dev->active_sensor &&
161 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
162 (dev->isp_inp & INP_CIF) ||
163 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
164 return 0;
165
166 for (i = RKISP_STREAM_DMATX0; i <= RKISP_STREAM_DMATX2; i++) {
167 dmatx = &dev->cap_dev.stream[i];
168 if (dmatx->ops && dmatx->ops->frame_end)
169 dmatx->ops->frame_end(dmatx, FRAME_INIT);
170 }
171
172 if (dev->dmarx_dev.trigger)
173 goto end;
174
175 /* for rawrd auto trigger mode, config first buf */
176 index = dev->hdr.index[HDR_DMA0];
177 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
178 if (buf) {
179 mi_raw0_rd_set_addr(base, buf->dma_addr);
180 dev->hdr.rx_cur_buf[index] = buf;
181 } else {
182 mi_raw0_rd_set_addr(base,
183 readl(base + MI_RAW0_WR_BASE_SHD));
184 }
185
186 index = dev->hdr.index[HDR_DMA1];
187 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
188 if (buf) {
189 mi_raw1_rd_set_addr(base, buf->dma_addr);
190 dev->hdr.rx_cur_buf[index] = buf;
191 } else {
192 mi_raw1_rd_set_addr(base,
193 readl(base + MI_RAW1_WR_BASE_SHD));
194 }
195
196 index = dev->hdr.index[HDR_DMA2];
197 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
198 if (buf) {
199 mi_raw2_rd_set_addr(base, buf->dma_addr);
200 dev->hdr.rx_cur_buf[index] = buf;
201 } else {
202 mi_raw2_rd_set_addr(base,
203 readl(base + MI_RAW2_WR_BASE_SHD));
204 }
205
206 end:
207 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
208 "CSI2RX CTRL0:0x%x CTRL1:0x%x\n"
209 "WR CTRL RAW0:0x%x RAW1:0x%x RAW2:0x%x\n"
210 "RD CTRL:0x%x\n",
211 readl(base + CSI2RX_CTRL0),
212 readl(base + CSI2RX_CTRL1),
213 readl(base + CSI2RX_RAW0_WR_CTRL),
214 readl(base + CSI2RX_RAW1_WR_CTRL),
215 readl(base + CSI2RX_RAW2_WR_CTRL),
216 readl(base + CSI2RX_RAW_RD_CTRL));
217 return 0;
218 }
219
hdr_config_dmatx(struct rkisp_device * dev)220 int hdr_config_dmatx(struct rkisp_device *dev)
221 {
222 struct rkisp_stream *stream;
223 struct v4l2_pix_format_mplane pixm;
224 u32 memory = 0;
225
226 if (atomic_inc_return(&dev->hdr.refcnt) > 1 ||
227 !dev->active_sensor ||
228 (dev->active_sensor &&
229 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
230 (dev->isp_inp & INP_CIF) ||
231 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
232 return 0;
233
234 rkisp_create_hdr_buf(dev);
235 memset(&pixm, 0, sizeof(pixm));
236 if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
237 dev->hdr.op_mode == HDR_LINEX2_DDR ||
238 dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
239 dev->hdr.op_mode == HDR_LINEX3_DDR ||
240 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
241 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
242 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
243 if (stream->ops && stream->ops->config_mi)
244 stream->ops->config_mi(stream);
245
246 if (!dev->dmarx_dev.trigger) {
247 pixm = stream->out_fmt;
248 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
249 rkisp_dmarx_set_fmt(stream, pixm);
250 mi_raw_length(stream);
251 }
252 }
253 if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
254 dev->hdr.op_mode == HDR_LINEX3_DDR ||
255 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
256 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
257 if (stream->ops && stream->ops->config_mi)
258 stream->ops->config_mi(stream);
259
260 if (!dev->dmarx_dev.trigger) {
261 pixm = stream->out_fmt;
262 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
263 rkisp_dmarx_set_fmt(stream, pixm);
264 mi_raw_length(stream);
265 }
266 }
267 if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
268 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
269 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
270 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
271 if (stream->ops && stream->ops->config_mi)
272 stream->ops->config_mi(stream);
273
274 if (!dev->dmarx_dev.trigger) {
275 memory = stream->memory;
276 pixm = stream->out_fmt;
277 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
278 rkisp_dmarx_set_fmt(stream, pixm);
279 stream->ops->config_mi(stream);
280 }
281 }
282
283 if (dev->hdr.op_mode != HDR_NORMAL && !dev->dmarx_dev.trigger) {
284 raw_rd_ctrl(dev->base_addr, memory << 2);
285 if (pixm.width && pixm.height)
286 rkisp_rawrd_set_pic_size(dev, pixm.width, pixm.height);
287 }
288 return 0;
289 }
290
hdr_stop_dmatx(struct rkisp_device * dev)291 void hdr_stop_dmatx(struct rkisp_device *dev)
292 {
293 struct rkisp_stream *stream;
294
295 if (atomic_dec_return(&dev->hdr.refcnt) ||
296 !dev->active_sensor ||
297 (dev->active_sensor &&
298 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
299 (dev->isp_inp & INP_CIF) ||
300 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
301 return;
302
303 if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
304 dev->hdr.op_mode == HDR_LINEX2_DDR ||
305 dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
306 dev->hdr.op_mode == HDR_LINEX3_DDR ||
307 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
308 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
309 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
310 stream->ops->stop_mi(stream);
311 }
312 if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
313 dev->hdr.op_mode == HDR_LINEX3_DDR ||
314 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
315 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
316 stream->ops->stop_mi(stream);
317 }
318 if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
319 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
320 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
321 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
322 stream->ops->stop_mi(stream);
323 }
324 }
325
hdr_dqbuf(struct list_head * q)326 struct rkisp_dummy_buffer *hdr_dqbuf(struct list_head *q)
327 {
328 struct rkisp_dummy_buffer *buf = NULL;
329
330 if (!list_empty(q)) {
331 buf = list_first_entry(q,
332 struct rkisp_dummy_buffer, queue);
333 list_del(&buf->queue);
334 }
335 return buf;
336 }
337
hdr_qbuf(struct list_head * q,struct rkisp_dummy_buffer * buf)338 void hdr_qbuf(struct list_head *q,
339 struct rkisp_dummy_buffer *buf)
340 {
341 if (buf)
342 list_add_tail(&buf->queue, q);
343 }
344
rkisp_config_dmatx_valid_buf(struct rkisp_device * dev)345 void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev)
346 {
347 struct rkisp_hw_dev *hw = dev->hw_dev;
348 struct rkisp_stream *stream;
349 struct rkisp_device *isp;
350 u32 i, j;
351
352 if (!hw->dummy_buf.mem_priv ||
353 !dev->active_sensor ||
354 (dev->active_sensor &&
355 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
356 (dev->isp_inp & INP_CIF) ||
357 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
358 return;
359 /* dmatx buf update by mi force or oneself frame end,
360 * for async dmatx enable need to update to valid buf first.
361 */
362 for (i = 0; i < hw->dev_num; i++) {
363 isp = hw->isp[i];
364 if (!isp ||
365 (isp && !(isp->isp_inp & INP_CSI)))
366 continue;
367 for (j = RKISP_STREAM_DMATX0; j < RKISP_MAX_STREAM; j++) {
368 stream = &isp->cap_dev.stream[j];
369 if (!stream->linked || stream->curr_buf || stream->next_buf)
370 continue;
371 mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
372 }
373 }
374 }
375
376 /* Get xsubs and ysubs for fourcc formats
377 *
378 * @xsubs: horizontal color samples in a 4*4 matrix, for yuv
379 * @ysubs: vertical color samples in a 4*4 matrix, for yuv
380 */
rkisp_fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)381 int rkisp_fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
382 {
383 switch (fcc) {
384 case V4L2_PIX_FMT_GREY:
385 case V4L2_PIX_FMT_YUV444M:
386 *xsubs = 1;
387 *ysubs = 1;
388 break;
389 case V4L2_PIX_FMT_YUYV:
390 case V4L2_PIX_FMT_YVYU:
391 case V4L2_PIX_FMT_VYUY:
392 case V4L2_PIX_FMT_UYVY:
393 case V4L2_PIX_FMT_YUV422P:
394 case V4L2_PIX_FMT_NV16:
395 case V4L2_PIX_FMT_NV61:
396 case V4L2_PIX_FMT_YVU422M:
397 case V4L2_PIX_FMT_FBC2:
398 *xsubs = 2;
399 *ysubs = 1;
400 break;
401 case V4L2_PIX_FMT_NV21:
402 case V4L2_PIX_FMT_NV12:
403 case V4L2_PIX_FMT_NV21M:
404 case V4L2_PIX_FMT_NV12M:
405 case V4L2_PIX_FMT_YUV420:
406 case V4L2_PIX_FMT_YVU420:
407 case V4L2_PIX_FMT_FBCG:
408 case V4L2_PIX_FMT_FBC0:
409 *xsubs = 2;
410 *ysubs = 2;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 return 0;
417 }
418
rkisp_mbus_code_xysubs(u32 code,u32 * xsubs,u32 * ysubs)419 int rkisp_mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs)
420 {
421 switch (code) {
422 case MEDIA_BUS_FMT_YUYV8_2X8:
423 case MEDIA_BUS_FMT_YUYV8_1X16:
424 case MEDIA_BUS_FMT_YVYU8_1X16:
425 case MEDIA_BUS_FMT_UYVY8_1X16:
426 case MEDIA_BUS_FMT_VYUY8_1X16:
427 *xsubs = 2;
428 *ysubs = 1;
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 return 0;
435 }
436
rkisp_stream_frame_start(struct rkisp_device * dev,u32 isp_mis)437 int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis)
438 {
439 struct rkisp_stream *stream;
440 int i;
441
442 if (isp_mis)
443 rkisp_dvbm_event(dev, CIF_ISP_V_START);
444 rkisp_bridge_update_mi(dev, isp_mis);
445
446 for (i = 0; i < RKISP_MAX_STREAM; i++) {
447 if (i == RKISP_STREAM_VIR || i == RKISP_STREAM_LUMA)
448 continue;
449 stream = &dev->cap_dev.stream[i];
450 if (stream->streaming &&
451 stream->ops && stream->ops->frame_start)
452 stream->ops->frame_start(stream, isp_mis);
453 }
454
455 return 0;
456 }
457
rkisp_stream_buf_done_early(struct rkisp_device * dev)458 void rkisp_stream_buf_done_early(struct rkisp_device *dev)
459 {
460 struct rkisp_stream *stream;
461 int i;
462
463 if (!dev->cap_dev.is_done_early)
464 return;
465
466 for (i = 0; i < RKISP_MAX_STREAM; i++) {
467 if (i == RKISP_STREAM_VIR || i == RKISP_STREAM_LUMA ||
468 i == RKISP_STREAM_DMATX0 || i == RKISP_STREAM_DMATX1 ||
469 i == RKISP_STREAM_DMATX2 || i == RKISP_STREAM_DMATX3)
470 continue;
471 stream = &dev->cap_dev.stream[i];
472 if (stream->streaming && !stream->stopping &&
473 stream->ops && stream->ops->frame_end)
474 stream->ops->frame_end(stream, FRAME_WORK);
475 }
476 }
477
478 struct stream_config rkisp_mp_stream_config = {
479 /* constraints */
480 .max_rsz_width = STREAM_MAX_MP_RSZ_OUTPUT_WIDTH,
481 .max_rsz_height = STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT,
482 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
483 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
484 .frame_end_id = CIF_MI_MP_FRAME,
485 /* registers */
486 .rsz = {
487 .ctrl = CIF_MRSZ_CTRL,
488 .scale_hy = CIF_MRSZ_SCALE_HY,
489 .scale_hcr = CIF_MRSZ_SCALE_HCR,
490 .scale_hcb = CIF_MRSZ_SCALE_HCB,
491 .scale_vy = CIF_MRSZ_SCALE_VY,
492 .scale_vc = CIF_MRSZ_SCALE_VC,
493 .scale_lut = CIF_MRSZ_SCALE_LUT,
494 .scale_lut_addr = CIF_MRSZ_SCALE_LUT_ADDR,
495 .scale_hy_shd = CIF_MRSZ_SCALE_HY_SHD,
496 .scale_hcr_shd = CIF_MRSZ_SCALE_HCR_SHD,
497 .scale_hcb_shd = CIF_MRSZ_SCALE_HCB_SHD,
498 .scale_vy_shd = CIF_MRSZ_SCALE_VY_SHD,
499 .scale_vc_shd = CIF_MRSZ_SCALE_VC_SHD,
500 .phase_hy = CIF_MRSZ_PHASE_HY,
501 .phase_hc = CIF_MRSZ_PHASE_HC,
502 .phase_vy = CIF_MRSZ_PHASE_VY,
503 .phase_vc = CIF_MRSZ_PHASE_VC,
504 .ctrl_shd = CIF_MRSZ_CTRL_SHD,
505 .phase_hy_shd = CIF_MRSZ_PHASE_HY_SHD,
506 .phase_hc_shd = CIF_MRSZ_PHASE_HC_SHD,
507 .phase_vy_shd = CIF_MRSZ_PHASE_VY_SHD,
508 .phase_vc_shd = CIF_MRSZ_PHASE_VC_SHD,
509 },
510 .dual_crop = {
511 .ctrl = CIF_DUAL_CROP_CTRL,
512 .yuvmode_mask = CIF_DUAL_CROP_MP_MODE_YUV,
513 .rawmode_mask = CIF_DUAL_CROP_MP_MODE_RAW,
514 .h_offset = CIF_DUAL_CROP_M_H_OFFS,
515 .v_offset = CIF_DUAL_CROP_M_V_OFFS,
516 .h_size = CIF_DUAL_CROP_M_H_SIZE,
517 .v_size = CIF_DUAL_CROP_M_V_SIZE,
518 },
519 .mi = {
520 .y_size_init = CIF_MI_MP_Y_SIZE_INIT,
521 .cb_size_init = CIF_MI_MP_CB_SIZE_INIT,
522 .cr_size_init = CIF_MI_MP_CR_SIZE_INIT,
523 .y_base_ad_init = CIF_MI_MP_Y_BASE_AD_INIT,
524 .cb_base_ad_init = CIF_MI_MP_CB_BASE_AD_INIT,
525 .cr_base_ad_init = CIF_MI_MP_CR_BASE_AD_INIT,
526 .y_offs_cnt_init = CIF_MI_MP_Y_OFFS_CNT_INIT,
527 .cb_offs_cnt_init = CIF_MI_MP_CB_OFFS_CNT_INIT,
528 .cr_offs_cnt_init = CIF_MI_MP_CR_OFFS_CNT_INIT,
529 .y_base_ad_shd = CIF_MI_MP_Y_BASE_AD_SHD,
530 .y_pic_size = ISP3X_MI_MP_WR_Y_PIC_SIZE,
531 },
532 };
533
534 struct stream_config rkisp_sp_stream_config = {
535 /* constraints */
536 .max_rsz_width = STREAM_MAX_SP_RSZ_OUTPUT_WIDTH,
537 .max_rsz_height = STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT,
538 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
539 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
540 .frame_end_id = CIF_MI_SP_FRAME,
541 /* registers */
542 .rsz = {
543 .ctrl = CIF_SRSZ_CTRL,
544 .scale_hy = CIF_SRSZ_SCALE_HY,
545 .scale_hcr = CIF_SRSZ_SCALE_HCR,
546 .scale_hcb = CIF_SRSZ_SCALE_HCB,
547 .scale_vy = CIF_SRSZ_SCALE_VY,
548 .scale_vc = CIF_SRSZ_SCALE_VC,
549 .scale_lut = CIF_SRSZ_SCALE_LUT,
550 .scale_lut_addr = CIF_SRSZ_SCALE_LUT_ADDR,
551 .scale_hy_shd = CIF_SRSZ_SCALE_HY_SHD,
552 .scale_hcr_shd = CIF_SRSZ_SCALE_HCR_SHD,
553 .scale_hcb_shd = CIF_SRSZ_SCALE_HCB_SHD,
554 .scale_vy_shd = CIF_SRSZ_SCALE_VY_SHD,
555 .scale_vc_shd = CIF_SRSZ_SCALE_VC_SHD,
556 .phase_hy = CIF_SRSZ_PHASE_HY,
557 .phase_hc = CIF_SRSZ_PHASE_HC,
558 .phase_vy = CIF_SRSZ_PHASE_VY,
559 .phase_vc = CIF_SRSZ_PHASE_VC,
560 .ctrl_shd = CIF_SRSZ_CTRL_SHD,
561 .phase_hy_shd = CIF_SRSZ_PHASE_HY_SHD,
562 .phase_hc_shd = CIF_SRSZ_PHASE_HC_SHD,
563 .phase_vy_shd = CIF_SRSZ_PHASE_VY_SHD,
564 .phase_vc_shd = CIF_SRSZ_PHASE_VC_SHD,
565 },
566 .dual_crop = {
567 .ctrl = CIF_DUAL_CROP_CTRL,
568 .yuvmode_mask = CIF_DUAL_CROP_SP_MODE_YUV,
569 .rawmode_mask = CIF_DUAL_CROP_SP_MODE_RAW,
570 .h_offset = CIF_DUAL_CROP_S_H_OFFS,
571 .v_offset = CIF_DUAL_CROP_S_V_OFFS,
572 .h_size = CIF_DUAL_CROP_S_H_SIZE,
573 .v_size = CIF_DUAL_CROP_S_V_SIZE,
574 },
575 .mi = {
576 .y_size_init = CIF_MI_SP_Y_SIZE_INIT,
577 .cb_size_init = CIF_MI_SP_CB_SIZE_INIT,
578 .cr_size_init = CIF_MI_SP_CR_SIZE_INIT,
579 .y_base_ad_init = CIF_MI_SP_Y_BASE_AD_INIT,
580 .cb_base_ad_init = CIF_MI_SP_CB_BASE_AD_INIT,
581 .cr_base_ad_init = CIF_MI_SP_CR_BASE_AD_INIT,
582 .y_offs_cnt_init = CIF_MI_SP_Y_OFFS_CNT_INIT,
583 .cb_offs_cnt_init = CIF_MI_SP_CB_OFFS_CNT_INIT,
584 .cr_offs_cnt_init = CIF_MI_SP_CR_OFFS_CNT_INIT,
585 .y_base_ad_shd = CIF_MI_SP_Y_BASE_AD_SHD,
586 .y_pic_size = ISP3X_MI_SP_WR_Y_PIC_SIZE,
587 },
588 };
589
590 static const
find_fmt(struct rkisp_stream * stream,const u32 pixelfmt)591 struct capture_fmt *find_fmt(struct rkisp_stream *stream, const u32 pixelfmt)
592 {
593 const struct capture_fmt *fmt;
594 int i;
595
596 for (i = 0; i < stream->config->fmt_size; i++) {
597 fmt = &stream->config->fmts[i];
598 if (fmt->fourcc == pixelfmt)
599 return fmt;
600 }
601 return NULL;
602 }
603
restrict_rsz_resolution(struct rkisp_stream * stream,const struct stream_config * cfg,struct v4l2_rect * max_rsz)604 static void restrict_rsz_resolution(struct rkisp_stream *stream,
605 const struct stream_config *cfg,
606 struct v4l2_rect *max_rsz)
607 {
608 struct rkisp_device *dev = stream->ispdev;
609 struct v4l2_rect *input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
610
611 if (stream->id == RKISP_STREAM_VIR ||
612 (dev->isp_ver == ISP_V30 && stream->id == RKISP_STREAM_BP)) {
613 max_rsz->width = input_win->width;
614 max_rsz->height = input_win->height;
615 } else if (stream->id == RKISP_STREAM_FBC) {
616 max_rsz->width = stream->dcrop.width;
617 max_rsz->height = stream->dcrop.height;
618 } else if (stream->id == RKISP_STREAM_MPDS ||
619 stream->id == RKISP_STREAM_BPDS) {
620 struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
621
622 max_rsz->width = t->out_fmt.width / 4;
623 max_rsz->height = t->out_fmt.height / 4;
624 } else if (stream->id == RKISP_STREAM_LUMA) {
625 u32 div = dev->is_bigmode ? 32 : 16;
626
627 max_rsz->width = ALIGN(DIV_ROUND_UP(input_win->width, div), 4);
628 max_rsz->height = DIV_ROUND_UP(input_win->height, div);
629 } else if (dev->hw_dev->is_unite) {
630 /* scale down only for unite mode */
631 max_rsz->width = min_t(int, input_win->width, cfg->max_rsz_width);
632 max_rsz->height = min_t(int, input_win->height, cfg->max_rsz_height);
633 } else {
634 /* scale up/down */
635 max_rsz->width = cfg->max_rsz_width;
636 max_rsz->height = cfg->max_rsz_height;
637 }
638 }
639
rkisp_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)640 static int rkisp_set_fmt(struct rkisp_stream *stream,
641 struct v4l2_pix_format_mplane *pixm,
642 bool try)
643 {
644 const struct capture_fmt *fmt;
645 struct rkisp_vdev_node *node = &stream->vnode;
646 const struct stream_config *config = stream->config;
647 struct rkisp_device *dev = stream->ispdev;
648 struct v4l2_rect max_rsz;
649 u32 i, planes, imagsize = 0, xsubs = 1, ysubs = 1;
650
651 fmt = find_fmt(stream, pixm->pixelformat);
652 if (!fmt) {
653 v4l2_err(&dev->v4l2_dev,
654 "%s nonsupport pixelformat:%c%c%c%c\n",
655 node->vdev.name,
656 pixm->pixelformat,
657 pixm->pixelformat >> 8,
658 pixm->pixelformat >> 16,
659 pixm->pixelformat >> 24);
660 return -EINVAL;
661 }
662
663 /* do checks on resolution */
664 restrict_rsz_resolution(stream, config, &max_rsz);
665 if (stream->id == RKISP_STREAM_MP ||
666 stream->id == RKISP_STREAM_SP ||
667 (stream->id == RKISP_STREAM_BP && dev->isp_ver != ISP_V30)) {
668 pixm->width = clamp_t(u32, pixm->width, config->min_rsz_width, max_rsz.width);
669 } else if (pixm->width != max_rsz.width &&
670 pixm->height != max_rsz.height &&
671 (stream->id == RKISP_STREAM_LUMA ||
672 (dev->isp_ver == ISP_V30 &&
673 (stream->id == RKISP_STREAM_BP || stream->id == RKISP_STREAM_FBC)))) {
674 v4l2_warn(&dev->v4l2_dev,
675 "%s no scale %dx%d should equal to %dx%d\n",
676 node->vdev.name,
677 pixm->width, pixm->height,
678 max_rsz.width, max_rsz.height);
679 pixm->width = max_rsz.width;
680 pixm->height = max_rsz.height;
681 } else if (stream->id == RKISP_STREAM_MPDS || stream->id == RKISP_STREAM_BPDS) {
682 struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
683
684 if (pixm->pixelformat != t->out_fmt.pixelformat ||
685 pixm->width != max_rsz.width || pixm->height != max_rsz.height) {
686 v4l2_warn(&dev->v4l2_dev,
687 "%s from %s, force to %dx%d %c%c%c%c\n",
688 node->vdev.name, t->vnode.vdev.name,
689 max_rsz.width, max_rsz.height,
690 t->out_fmt.pixelformat,
691 t->out_fmt.pixelformat >> 8,
692 t->out_fmt.pixelformat >> 16,
693 t->out_fmt.pixelformat >> 24);
694 pixm->pixelformat = t->out_fmt.pixelformat;
695 pixm->width = max_rsz.width;
696 pixm->height = max_rsz.height;
697 }
698 } else if (stream->id == RKISP_STREAM_VIR) {
699 struct rkisp_stream *t;
700
701 if (stream->conn_id != -1) {
702 t = &dev->cap_dev.stream[stream->conn_id];
703 *pixm = t->out_fmt;
704 } else {
705 for (i = RKISP_STREAM_MP; i < RKISP_STREAM_VIR; i++) {
706 t = &dev->cap_dev.stream[i];
707 if (t->out_isp_fmt.fmt_type != FMT_YUV || !t->streaming)
708 continue;
709 if (t->out_fmt.plane_fmt[0].sizeimage > imagsize) {
710 imagsize = t->out_fmt.plane_fmt[0].sizeimage;
711 *pixm = t->out_fmt;
712 stream->conn_id = t->id;
713 }
714 }
715 }
716 if (stream->conn_id == -1) {
717 v4l2_err(&dev->v4l2_dev, "no output stream for iqtool\n");
718 return -EINVAL;
719 }
720 imagsize = 0;
721 }
722
723 pixm->num_planes = fmt->mplanes;
724 pixm->field = V4L2_FIELD_NONE;
725 /* get quantization from ispsd */
726 pixm->quantization = stream->ispdev->isp_sdev.quantization;
727
728 /* calculate size */
729 rkisp_fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
730 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
731 for (i = 0; i < planes; i++) {
732 struct v4l2_plane_pix_format *plane_fmt;
733 unsigned int width, height, bytesperline, w, h;
734
735 plane_fmt = pixm->plane_fmt + i;
736
737 w = (fmt->fmt_type == FMT_FBC) ?
738 ALIGN(pixm->width, 16) : pixm->width;
739 h = (fmt->fmt_type == FMT_FBC) ?
740 ALIGN(pixm->height, 16) : pixm->height;
741 /* mainpath for warp default */
742 if (dev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP)
743 h = dev->cap_dev.wrap_line;
744 width = i ? w / xsubs : w;
745 height = i ? h / ysubs : h;
746
747 if (dev->isp_ver == ISP_V20 &&
748 fmt->fmt_type == FMT_BAYER &&
749 stream->id == RKISP_STREAM_DMATX2)
750 height += RKMODULE_EXTEND_LINE;
751
752 if ((dev->isp_ver == ISP_V20 ||
753 dev->isp_ver == ISP_V21) &&
754 !stream->memory &&
755 fmt->fmt_type == FMT_BAYER &&
756 stream->id != RKISP_STREAM_MP &&
757 stream->id != RKISP_STREAM_SP)
758 /* compact mode need bytesperline 4byte align */
759 bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
760 else
761 bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
762
763 if (i != 0 || plane_fmt->bytesperline < bytesperline)
764 plane_fmt->bytesperline = bytesperline;
765
766 /* 128bit AXI, 16byte align for bytesperline */
767 if ((dev->isp_ver == ISP_V20 && stream->id == RKISP_STREAM_SP) ||
768 dev->isp_ver >= ISP_V30)
769 plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline, 16);
770
771 plane_fmt->sizeimage = plane_fmt->bytesperline * height;
772
773 /* FMT_FBCGAIN: uv address is y size offset need 64 align
774 * FMT_FBC: width and height need 16 align
775 * header: width * height / 16, and 4096 align for mpp
776 * payload: yuv420 or yuv422 size
777 */
778 if (fmt->fmt_type == FMT_FBCGAIN && i == 0)
779 plane_fmt->sizeimage = ALIGN(plane_fmt->sizeimage, 64);
780 else if (fmt->fmt_type == FMT_FBC && i == 0)
781 plane_fmt->sizeimage = ALIGN(plane_fmt->sizeimage >> 4, RK_MPP_ALIGN);
782 else if (fmt->fmt_type == FMT_FBC)
783 plane_fmt->sizeimage += w * h;
784 imagsize += plane_fmt->sizeimage;
785 }
786
787 /* convert to non-MPLANE format.
788 * it's important since we want to unify none-MPLANE
789 * and MPLANE.
790 */
791 if (fmt->mplanes == 1 || fmt->fmt_type == FMT_FBCGAIN)
792 pixm->plane_fmt[0].sizeimage = imagsize;
793
794 if (!try && !stream->start_stream && !stream->streaming) {
795 stream->out_isp_fmt = *fmt;
796 stream->out_fmt = *pixm;
797
798 if (stream->id == RKISP_STREAM_SP) {
799 stream->u.sp.y_stride =
800 pixm->plane_fmt[0].bytesperline /
801 DIV_ROUND_UP(fmt->bpp[0], 8);
802 } else if (stream->id == RKISP_STREAM_MP) {
803 stream->u.mp.raw_enable = (fmt->fmt_type == FMT_BAYER);
804 }
805
806 v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
807 "%s: %s req(%d, %d) out(%d, %d)\n", __func__,
808 node->vdev.name, pixm->width, pixm->height,
809 stream->out_fmt.width, stream->out_fmt.height);
810 }
811
812 return 0;
813 }
814
815 struct rockit_isp_ops rockit_isp_ops = {
816 .rkisp_set_fmt = rkisp_set_fmt,
817 };
818
rkisp_fh_open(struct file * filp)819 int rkisp_fh_open(struct file *filp)
820 {
821 struct rkisp_stream *stream = video_drvdata(filp);
822 int ret;
823
824 if (!stream->ispdev->is_probe_end)
825 return -EINVAL;
826
827 ret = v4l2_fh_open(filp);
828 if (!ret) {
829 ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
830 if (ret < 0)
831 vb2_fop_release(filp);
832 }
833
834 return ret;
835 }
836
rkisp_fop_release(struct file * file)837 int rkisp_fop_release(struct file *file)
838 {
839 struct rkisp_stream *stream = video_drvdata(file);
840 int ret;
841
842 ret = vb2_fop_release(file);
843 if (!ret)
844 v4l2_pipeline_pm_put(&stream->vnode.vdev.entity);
845 return ret;
846 }
847
rkisp_set_stream_def_fmt(struct rkisp_device * dev,u32 id,u32 width,u32 height,u32 pixelformat)848 void rkisp_set_stream_def_fmt(struct rkisp_device *dev, u32 id,
849 u32 width, u32 height, u32 pixelformat)
850 {
851 struct rkisp_stream *stream = &dev->cap_dev.stream[id];
852 struct v4l2_pix_format_mplane pixm;
853
854 memset(&pixm, 0, sizeof(pixm));
855 if (pixelformat)
856 pixm.pixelformat = pixelformat;
857 else
858 pixm.pixelformat = stream->out_isp_fmt.fourcc;
859 if (!pixm.pixelformat)
860 return;
861
862 stream->dcrop.left = 0;
863 stream->dcrop.top = 0;
864 stream->dcrop.width = width;
865 stream->dcrop.height = height;
866
867 pixm.width = width;
868 pixm.height = height;
869 rkisp_set_fmt(stream, &pixm, false);
870 }
871
872 /************************* v4l2_file_operations***************************/
873 static const struct v4l2_file_operations rkisp_fops = {
874 .open = rkisp_fh_open,
875 .release = rkisp_fop_release,
876 .unlocked_ioctl = video_ioctl2,
877 .poll = vb2_fop_poll,
878 .mmap = vb2_fop_mmap,
879 #ifdef CONFIG_COMPAT
880 .compat_ioctl32 = video_ioctl2,
881 #endif
882 };
883
884 /*
885 * mp and sp v4l2_ioctl_ops
886 */
887
rkisp_enum_input(struct file * file,void * priv,struct v4l2_input * input)888 static int rkisp_enum_input(struct file *file, void *priv,
889 struct v4l2_input *input)
890 {
891 if (input->index > 0)
892 return -EINVAL;
893
894 input->type = V4L2_INPUT_TYPE_CAMERA;
895 strlcpy(input->name, "Camera", sizeof(input->name));
896
897 return 0;
898 }
899
rkisp_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)900 static int rkisp_try_fmt_vid_cap_mplane(struct file *file, void *fh,
901 struct v4l2_format *f)
902 {
903 struct rkisp_stream *stream = video_drvdata(file);
904
905 return rkisp_set_fmt(stream, &f->fmt.pix_mp, true);
906 }
907
rkisp_enum_framesizes(struct file * file,void * prov,struct v4l2_frmsizeenum * fsize)908 static int rkisp_enum_framesizes(struct file *file, void *prov,
909 struct v4l2_frmsizeenum *fsize)
910 {
911 struct rkisp_stream *stream = video_drvdata(file);
912 const struct stream_config *config = stream->config;
913 struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
914 struct v4l2_frmsize_discrete *d = &fsize->discrete;
915 struct rkisp_device *dev = stream->ispdev;
916 struct v4l2_rect max_rsz;
917 struct v4l2_rect *input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
918
919 if (fsize->index != 0)
920 return -EINVAL;
921
922 if (!find_fmt(stream, fsize->pixel_format))
923 return -EINVAL;
924
925 restrict_rsz_resolution(stream, config, &max_rsz);
926
927 if (stream->out_isp_fmt.fmt_type == FMT_BAYER ||
928 stream->id == RKISP_STREAM_FBC ||
929 stream->id == RKISP_STREAM_BPDS ||
930 stream->id == RKISP_STREAM_MPDS ||
931 stream->id == RKISP_STREAM_LUMA ||
932 stream->id == RKISP_STREAM_VIR ||
933 (stream->id == RKISP_STREAM_BP && dev->hw_dev->isp_ver == ISP_V30)) {
934 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
935 d->width = max_rsz.width;
936 d->height = max_rsz.height;
937 } else {
938 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
939 s->min_width = STREAM_MIN_RSZ_OUTPUT_WIDTH;
940 s->min_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT;
941 s->max_width = min_t(u32, max_rsz.width, input_win->width);
942 s->max_height = input_win->height;
943 s->step_width = STREAM_OUTPUT_STEP_WISE;
944 s->step_height = STREAM_OUTPUT_STEP_WISE;
945 }
946
947 return 0;
948 }
949
rkisp_get_cmsk(struct rkisp_stream * stream,struct rkisp_cmsk_cfg * cfg)950 static int rkisp_get_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cfg)
951 {
952 struct rkisp_device *dev = stream->ispdev;
953 unsigned long lock_flags = 0;
954 u32 i, win_en, mode;
955
956 if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) ||
957 stream->id == RKISP_STREAM_FBC ||
958 stream->id == RKISP_STREAM_MPDS ||
959 stream->id == RKISP_STREAM_BPDS) {
960 v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__);
961 return -EINVAL;
962 }
963
964 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
965 *cfg = dev->cmsk_cfg;
966 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
967
968 switch (stream->id) {
969 case RKISP_STREAM_MP:
970 win_en = cfg->win[0].win_en;
971 mode = cfg->win[0].mode;
972 break;
973 case RKISP_STREAM_SP:
974 win_en = cfg->win[1].win_en;
975 mode = cfg->win[1].mode;
976 break;
977 case RKISP_STREAM_BP:
978 default:
979 win_en = cfg->win[2].win_en;
980 mode = cfg->win[2].mode;
981 break;
982 }
983
984 cfg->width_ro = dev->isp_sdev.out_crop.width;
985 cfg->height_ro = dev->isp_sdev.out_crop.height;
986 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
987 cfg->win[i].win_en = !!(win_en & BIT(i));
988 cfg->win[i].mode = !!(mode & BIT(i));
989 }
990
991 return 0;
992 }
993
rkisp_set_cmsk(struct rkisp_stream * stream,struct rkisp_cmsk_cfg * cfg)994 static int rkisp_set_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cfg)
995 {
996 struct rkisp_device *dev = stream->ispdev;
997 unsigned long lock_flags = 0;
998 u16 i, win_en = 0, mode = 0;
999 u16 h_offs, v_offs, h_size, v_size;
1000 u32 width = dev->isp_sdev.out_crop.width;
1001 u32 height = dev->isp_sdev.out_crop.height;
1002 u32 align = (dev->isp_ver == ISP_V30) ? 8 : 2;
1003 bool warn = false;
1004
1005 if ((dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32) ||
1006 stream->id == RKISP_STREAM_FBC ||
1007 stream->id == RKISP_STREAM_MPDS ||
1008 stream->id == RKISP_STREAM_BPDS) {
1009 v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__);
1010 return -EINVAL;
1011 }
1012
1013 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
1014 dev->is_cmsk_upd = true;
1015 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
1016 win_en |= cfg->win[i].win_en ? BIT(i) : 0;
1017 mode |= cfg->win[i].mode ? BIT(i) : 0;
1018
1019 if (cfg->win[i].win_en) {
1020 if (cfg->win[i].mode) {
1021 dev->cmsk_cfg.win[i].cover_color_y = cfg->win[i].cover_color_y;
1022 dev->cmsk_cfg.win[i].cover_color_u = cfg->win[i].cover_color_u;
1023 dev->cmsk_cfg.win[i].cover_color_v = cfg->win[i].cover_color_v;
1024 }
1025 h_offs = cfg->win[i].h_offs & ~0x1;
1026 v_offs = cfg->win[i].v_offs & ~0x1;
1027 h_size = ALIGN_DOWN(cfg->win[i].h_size, align);
1028 v_size = ALIGN_DOWN(cfg->win[i].v_size, align);
1029 if (h_offs != cfg->win[i].h_offs ||
1030 v_offs != cfg->win[i].v_offs ||
1031 h_size != cfg->win[i].h_size ||
1032 v_size != cfg->win[i].v_size)
1033 warn = true;
1034 if (h_offs + h_size > width) {
1035 h_size = ALIGN_DOWN(width - h_offs, align);
1036 warn = true;
1037 }
1038 if (v_offs + v_size > height) {
1039 v_size = ALIGN_DOWN(height - v_offs, align);
1040 warn = true;
1041 }
1042 if (warn) {
1043 warn = false;
1044 v4l2_warn(&dev->v4l2_dev,
1045 "%s cmsk offs 2 align, size %d align and offs + size < resolution\n"
1046 "\t cmsk win%d result to offs:%d %d, size:%d %d\n",
1047 stream->vnode.vdev.name, i, align, h_offs, v_offs, h_size, v_size);
1048 }
1049 dev->cmsk_cfg.win[i].h_offs = h_offs;
1050 dev->cmsk_cfg.win[i].v_offs = v_offs;
1051 dev->cmsk_cfg.win[i].h_size = h_size;
1052 dev->cmsk_cfg.win[i].v_size = v_size;
1053 }
1054 }
1055
1056 switch (stream->id) {
1057 case RKISP_STREAM_MP:
1058 dev->cmsk_cfg.win[0].win_en = win_en;
1059 dev->cmsk_cfg.win[0].mode = mode;
1060 break;
1061 case RKISP_STREAM_SP:
1062 dev->cmsk_cfg.win[1].win_en = win_en;
1063 dev->cmsk_cfg.win[1].mode = mode;
1064 break;
1065 case RKISP_STREAM_BP:
1066 default:
1067 dev->cmsk_cfg.win[2].win_en = win_en;
1068 dev->cmsk_cfg.win[2].mode = mode;
1069 break;
1070 }
1071 dev->cmsk_cfg.mosaic_block = cfg->mosaic_block;
1072 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1073 return 0;
1074
1075 }
1076
rkisp_get_stream_info(struct rkisp_stream * stream,struct rkisp_stream_info * info)1077 static int rkisp_get_stream_info(struct rkisp_stream *stream,
1078 struct rkisp_stream_info *info)
1079 {
1080 struct rkisp_device *dev = stream->ispdev;
1081 u32 id = 0;
1082
1083 rkisp_dmarx_get_frame(stream->ispdev, &id, NULL, NULL, true);
1084 info->cur_frame_id = stream->dbg.id;
1085 info->input_frame_loss = dev->isp_sdev.dbg.frameloss;
1086 info->output_frame_loss = stream->dbg.frameloss;
1087 info->stream_on = stream->streaming;
1088 info->stream_id = stream->id;
1089 return 0;
1090 }
1091
rkisp_get_mirror_flip(struct rkisp_stream * stream,struct rkisp_mirror_flip * cfg)1092 static int rkisp_get_mirror_flip(struct rkisp_stream *stream,
1093 struct rkisp_mirror_flip *cfg)
1094 {
1095 struct rkisp_device *dev = stream->ispdev;
1096
1097 if (dev->isp_ver != ISP_V32)
1098 return -EINVAL;
1099
1100 cfg->mirror = dev->cap_dev.is_mirror;
1101 cfg->flip = stream->is_flip;
1102 return 0;
1103 }
1104
rkisp_set_mirror_flip(struct rkisp_stream * stream,struct rkisp_mirror_flip * cfg)1105 static int rkisp_set_mirror_flip(struct rkisp_stream *stream,
1106 struct rkisp_mirror_flip *cfg)
1107 {
1108 struct rkisp_device *dev = stream->ispdev;
1109
1110 if (dev->isp_ver != ISP_V32)
1111 return -EINVAL;
1112
1113 if (dev->cap_dev.wrap_line) {
1114 v4l2_warn(&dev->v4l2_dev, "wrap_line mode can not set the mirror");
1115 dev->cap_dev.is_mirror = 0;
1116 } else {
1117 dev->cap_dev.is_mirror = cfg->mirror;
1118 }
1119
1120 stream->is_flip = cfg->flip;
1121 stream->is_mf_upd = true;
1122 return 0;
1123 }
1124
rkisp_get_wrap_line(struct rkisp_stream * stream,struct rkisp_wrap_info * arg)1125 static int rkisp_get_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_info *arg)
1126 {
1127 struct rkisp_device *dev = stream->ispdev;
1128
1129 if (dev->isp_ver != ISP_V32 && stream->id != RKISP_STREAM_MP)
1130 return -EINVAL;
1131
1132 arg->width = dev->cap_dev.wrap_width;
1133 arg->height = dev->cap_dev.wrap_line;
1134 return 0;
1135 }
1136
rkisp_set_wrap_line(struct rkisp_stream * stream,struct rkisp_wrap_info * arg)1137 static int rkisp_set_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_info *arg)
1138 {
1139 struct rkisp_device *dev = stream->ispdev;
1140
1141 if (dev->isp_ver != ISP_V32 ||
1142 dev->hw_dev->dev_link_num > 1 ||
1143 !stream->ops->set_wrap) {
1144 v4l2_err(&dev->v4l2_dev,
1145 "wrap only support for single sensor and mainpath\n");
1146 return -EINVAL;
1147 }
1148 dev->cap_dev.wrap_width = arg->width;
1149 return stream->ops->set_wrap(stream, arg->height);
1150 }
1151
rkisp_set_fps(struct rkisp_stream * stream,int * fps)1152 static int rkisp_set_fps(struct rkisp_stream *stream, int *fps)
1153 {
1154 struct rkisp_device *dev = stream->ispdev;
1155
1156 if (dev->isp_ver != ISP_V32)
1157 return -EINVAL;
1158
1159 return rkisp_rockit_fps_set(fps, stream);
1160 }
1161
rkisp_get_fps(struct rkisp_stream * stream,int * fps)1162 static int rkisp_get_fps(struct rkisp_stream *stream, int *fps)
1163 {
1164 struct rkisp_device *dev = stream->ispdev;
1165
1166 if (dev->isp_ver != ISP_V32)
1167 return -EINVAL;
1168
1169 return rkisp_rockit_fps_get(fps, stream);
1170 }
1171
rkisp_get_tb_stream_info(struct rkisp_stream * stream,struct rkisp_tb_stream_info * info)1172 int rkisp_get_tb_stream_info(struct rkisp_stream *stream,
1173 struct rkisp_tb_stream_info *info)
1174 {
1175 struct rkisp_device *dev = stream->ispdev;
1176
1177 if (stream->id != RKISP_STREAM_MP) {
1178 v4l2_err(&dev->v4l2_dev, "fast only support for MP\n");
1179 return -EINVAL;
1180 }
1181
1182 if (!dev->tb_stream_info.buf_max) {
1183 v4l2_err(&dev->v4l2_dev, "thunderboot no enough memory for image\n");
1184 return -EINVAL;
1185 }
1186
1187 memcpy(info, &dev->tb_stream_info, sizeof(*info));
1188 return 0;
1189 }
1190
rkisp_free_tb_stream_buf(struct rkisp_stream * stream)1191 int rkisp_free_tb_stream_buf(struct rkisp_stream *stream)
1192 {
1193 struct rkisp_device *dev = stream->ispdev;
1194 struct rkisp_isp_subdev *sdev = &dev->isp_sdev;
1195 struct v4l2_subdev *sd = &sdev->sd;
1196
1197 return sd->ops->core->ioctl(sd, RKISP_CMD_FREE_SHARED_BUF, NULL);
1198 }
1199
rkisp_set_iqtool_connect_id(struct rkisp_stream * stream,int stream_id)1200 static int rkisp_set_iqtool_connect_id(struct rkisp_stream *stream, int stream_id)
1201 {
1202 struct rkisp_device *dev = stream->ispdev;
1203
1204 if (stream->id != RKISP_STREAM_VIR) {
1205 v4l2_err(&dev->v4l2_dev, "only support for iqtool video\n");
1206 goto err;
1207 }
1208
1209 if (stream_id != RKISP_STREAM_MP &&
1210 stream_id != RKISP_STREAM_SP &&
1211 stream_id != RKISP_STREAM_BP) {
1212 v4l2_err(&dev->v4l2_dev, "invalid connect stream id\n");
1213 goto err;
1214 }
1215
1216 stream->conn_id = stream_id;
1217 return 0;
1218 err:
1219 return -EINVAL;
1220 }
1221
rkisp_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)1222 static long rkisp_ioctl_default(struct file *file, void *fh,
1223 bool valid_prio, unsigned int cmd, void *arg)
1224 {
1225 struct rkisp_stream *stream = video_drvdata(file);
1226 long ret = 0;
1227
1228 if (!arg && cmd != RKISP_CMD_FREE_TB_STREAM_BUF)
1229 return -EINVAL;
1230
1231 switch (cmd) {
1232 case RKISP_CMD_GET_CSI_MEMORY_MODE:
1233 if (stream->id != RKISP_STREAM_DMATX0 &&
1234 stream->id != RKISP_STREAM_DMATX1 &&
1235 stream->id != RKISP_STREAM_DMATX2 &&
1236 stream->id != RKISP_STREAM_DMATX3)
1237 ret = -EINVAL;
1238 else if (stream->memory == 0)
1239 *(int *)arg = CSI_MEM_COMPACT;
1240 else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
1241 *(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
1242 else
1243 *(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
1244 break;
1245 case RKISP_CMD_SET_CSI_MEMORY_MODE:
1246 if (stream->id != RKISP_STREAM_DMATX0 &&
1247 stream->id != RKISP_STREAM_DMATX1 &&
1248 stream->id != RKISP_STREAM_DMATX2 &&
1249 stream->id != RKISP_STREAM_DMATX3)
1250 ret = -EINVAL;
1251 else if (*(int *)arg == CSI_MEM_COMPACT)
1252 stream->memory = 0;
1253 else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
1254 stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
1255 else
1256 stream->memory =
1257 SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
1258 break;
1259 case RKISP_CMD_GET_CMSK:
1260 ret = rkisp_get_cmsk(stream, arg);
1261 break;
1262 case RKISP_CMD_SET_CMSK:
1263 ret = rkisp_set_cmsk(stream, arg);
1264 break;
1265 case RKISP_CMD_GET_STREAM_INFO:
1266 ret = rkisp_get_stream_info(stream, arg);
1267 break;
1268 case RKISP_CMD_GET_MIRROR_FLIP:
1269 ret = rkisp_get_mirror_flip(stream, arg);
1270 break;
1271 case RKISP_CMD_SET_MIRROR_FLIP:
1272 ret = rkisp_set_mirror_flip(stream, arg);
1273 break;
1274 case RKISP_CMD_GET_WRAP_LINE:
1275 ret = rkisp_get_wrap_line(stream, arg);
1276 break;
1277 case RKISP_CMD_SET_WRAP_LINE:
1278 ret = rkisp_set_wrap_line(stream, arg);
1279 break;
1280 case RKISP_CMD_SET_FPS:
1281 ret = rkisp_set_fps(stream, arg);
1282 break;
1283 case RKISP_CMD_GET_FPS:
1284 ret = rkisp_get_fps(stream, arg);
1285 break;
1286 case RKISP_CMD_GET_TB_STREAM_INFO:
1287 ret = rkisp_get_tb_stream_info(stream, arg);
1288 break;
1289 case RKISP_CMD_FREE_TB_STREAM_BUF:
1290 ret = rkisp_free_tb_stream_buf(stream);
1291 break;
1292 case RKISP_CMD_SET_IQTOOL_CONN_ID:
1293 ret = rkisp_set_iqtool_connect_id(stream, *(int *)arg);
1294 break;
1295 default:
1296 ret = -EINVAL;
1297 }
1298
1299 return ret;
1300 }
1301
rkisp_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)1302 static int rkisp_enum_frameintervals(struct file *file, void *fh,
1303 struct v4l2_frmivalenum *fival)
1304 {
1305 const struct rkisp_stream *stream = video_drvdata(file);
1306 struct rkisp_device *dev = stream->ispdev;
1307 struct rkisp_sensor_info *sensor = dev->active_sensor;
1308 struct v4l2_subdev_frame_interval fi;
1309 int ret;
1310
1311 if (fival->index != 0)
1312 return -EINVAL;
1313
1314 if (!sensor) {
1315 /* TODO: active_sensor is NULL if using DMARX path */
1316 v4l2_err(&dev->v4l2_dev, "%s Not active sensor\n", __func__);
1317 return -ENODEV;
1318 }
1319
1320 ret = v4l2_subdev_call(sensor->sd, video, g_frame_interval, &fi);
1321 if (ret && ret != -ENOIOCTLCMD) {
1322 return ret;
1323 } else if (ret == -ENOIOCTLCMD) {
1324 /* Set a default value for sensors not implements ioctl */
1325 fi.interval.numerator = 1;
1326 fi.interval.denominator = 30;
1327 }
1328
1329 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
1330 fival->stepwise.step.numerator = 1;
1331 fival->stepwise.step.denominator = 1;
1332 fival->stepwise.max.numerator = 1;
1333 fival->stepwise.max.denominator = 1;
1334 fival->stepwise.min.numerator = fi.interval.numerator;
1335 fival->stepwise.min.denominator = fi.interval.denominator;
1336
1337 return 0;
1338 }
1339
rkisp_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)1340 static int rkisp_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1341 struct v4l2_fmtdesc *f)
1342 {
1343 struct rkisp_stream *stream = video_drvdata(file);
1344 const struct capture_fmt *fmt = NULL;
1345 struct rkisp_device *dev = stream->ispdev;
1346 struct ispsd_in_fmt *isp_in_fmt = &dev->isp_sdev.in_fmt;
1347 struct ispsd_out_fmt *isp_out_fmt = &dev->isp_sdev.out_fmt;
1348 int ret = -EINVAL;
1349
1350 /* only one output format for raw */
1351 if (isp_out_fmt->fmt_type == FMT_BAYER ||
1352 stream->id == RKISP_STREAM_DMATX0 ||
1353 stream->id == RKISP_STREAM_DMATX1 ||
1354 stream->id == RKISP_STREAM_DMATX2 ||
1355 stream->id == RKISP_STREAM_DMATX3) {
1356 u32 pixelformat = rkisp_mbus_pixelcode_to_v4l2(isp_in_fmt->mbus_code);
1357
1358 if (f->index == 0) {
1359 fmt = find_fmt(stream, pixelformat);
1360 if (fmt) {
1361 f->pixelformat = pixelformat;
1362 ret = 0;
1363 }
1364 }
1365 return ret;
1366 }
1367
1368 if (f->index >= stream->config->fmt_size)
1369 return -EINVAL;
1370
1371 fmt = &stream->config->fmts[f->index];
1372 /* only output yuv format */
1373 if (isp_out_fmt->fmt_type == FMT_YUV && fmt->fmt_type == FMT_BAYER)
1374 return -EINVAL;
1375
1376 f->pixelformat = fmt->fourcc;
1377 switch (f->pixelformat) {
1378 case V4L2_PIX_FMT_FBC2:
1379 strscpy(f->description,
1380 "Rockchip yuv422sp fbc encoder",
1381 sizeof(f->description));
1382 break;
1383 case V4L2_PIX_FMT_FBC0:
1384 strscpy(f->description,
1385 "Rockchip yuv420sp fbc encoder",
1386 sizeof(f->description));
1387 break;
1388 case V4L2_PIX_FMT_FBCG:
1389 strscpy(f->description,
1390 "Rockchip fbc gain",
1391 sizeof(f->description));
1392 break;
1393 case V4l2_PIX_FMT_EBD8:
1394 strscpy(f->description,
1395 "Embedded data 8-bit",
1396 sizeof(f->description));
1397 break;
1398 case V4l2_PIX_FMT_SPD16:
1399 strscpy(f->description,
1400 "Shield pix data 16-bit",
1401 sizeof(f->description));
1402 break;
1403 default:
1404 break;
1405 }
1406
1407 return 0;
1408 }
1409
rkisp_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)1410 static int rkisp_s_fmt_vid_cap_mplane(struct file *file,
1411 void *priv, struct v4l2_format *f)
1412 {
1413 struct rkisp_stream *stream = video_drvdata(file);
1414 struct video_device *vdev = &stream->vnode.vdev;
1415 struct rkisp_vdev_node *node = vdev_to_node(vdev);
1416 struct rkisp_device *dev = stream->ispdev;
1417
1418 if (vb2_is_streaming(&node->buf_queue)) {
1419 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
1420 return -EBUSY;
1421 }
1422
1423 return rkisp_set_fmt(stream, &f->fmt.pix_mp, false);
1424 }
1425
rkisp_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1426 static int rkisp_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1427 struct v4l2_format *f)
1428 {
1429 struct rkisp_stream *stream = video_drvdata(file);
1430
1431 f->fmt.pix_mp = stream->out_fmt;
1432
1433 return 0;
1434 }
1435
rkisp_g_selection(struct file * file,void * prv,struct v4l2_selection * sel)1436 static int rkisp_g_selection(struct file *file, void *prv,
1437 struct v4l2_selection *sel)
1438 {
1439 struct rkisp_stream *stream = video_drvdata(file);
1440 struct rkisp_device *dev = stream->ispdev;
1441 struct v4l2_rect *dcrop = &stream->dcrop;
1442 struct v4l2_rect *input_win;
1443
1444 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
1445
1446 switch (sel->target) {
1447 case V4L2_SEL_TGT_CROP_BOUNDS:
1448 sel->r.width = input_win->width;
1449 sel->r.height = input_win->height;
1450 sel->r.left = 0;
1451 sel->r.top = 0;
1452 break;
1453 case V4L2_SEL_TGT_CROP:
1454 sel->r = *dcrop;
1455 break;
1456 default:
1457 return -EINVAL;
1458 }
1459
1460 return 0;
1461 }
1462
rkisp_update_crop(struct rkisp_stream * stream,struct v4l2_rect * sel,const struct v4l2_rect * in)1463 static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
1464 struct v4l2_rect *sel,
1465 const struct v4l2_rect *in)
1466 {
1467 struct rkisp_device *dev = stream->ispdev;
1468 bool is_unite = dev->hw_dev->is_unite;
1469 u32 align = is_unite ? 4 : 2;
1470
1471 /* Not crop for MP bayer raw data and dmatx path */
1472 if ((stream->id == RKISP_STREAM_MP &&
1473 stream->out_isp_fmt.fmt_type == FMT_BAYER) ||
1474 stream->id == RKISP_STREAM_DMATX0 ||
1475 stream->id == RKISP_STREAM_DMATX1 ||
1476 stream->id == RKISP_STREAM_DMATX2 ||
1477 stream->id == RKISP_STREAM_DMATX3 ||
1478 stream->id == RKISP_STREAM_MPDS ||
1479 stream->id == RKISP_STREAM_BPDS) {
1480 sel->left = 0;
1481 sel->top = 0;
1482 sel->width = in->width;
1483 sel->height = in->height;
1484 return sel;
1485 }
1486
1487 sel->left = ALIGN(sel->left, 2);
1488 sel->width = ALIGN(sel->width, align);
1489 sel->left = clamp_t(u32, sel->left, 0,
1490 in->width - STREAM_MIN_MP_SP_INPUT_WIDTH);
1491 sel->top = clamp_t(u32, sel->top, 0,
1492 in->height - STREAM_MIN_MP_SP_INPUT_HEIGHT);
1493 sel->width = clamp_t(u32, sel->width, STREAM_MIN_MP_SP_INPUT_WIDTH,
1494 in->width - sel->left);
1495 sel->height = clamp_t(u32, sel->height, STREAM_MIN_MP_SP_INPUT_HEIGHT,
1496 in->height - sel->top);
1497 if (is_unite && (sel->width + 2 * sel->left) != in->width) {
1498 sel->left = ALIGN_DOWN((in->width - sel->width) / 2, 2);
1499 v4l2_warn(&dev->v4l2_dev,
1500 "try horizontal center crop(%d,%d)/%dx%d for dual isp\n",
1501 sel->left, sel->top, sel->width, sel->height);
1502 }
1503 stream->is_crop_upd = true;
1504 return sel;
1505 }
1506
rkisp_s_selection(struct file * file,void * prv,struct v4l2_selection * sel)1507 static int rkisp_s_selection(struct file *file, void *prv,
1508 struct v4l2_selection *sel)
1509 {
1510 struct rkisp_stream *stream = video_drvdata(file);
1511 struct rkisp_device *dev = stream->ispdev;
1512 struct v4l2_rect *dcrop = &stream->dcrop;
1513 const struct v4l2_rect *input_win;
1514
1515 if (sel->target != V4L2_SEL_TGT_CROP)
1516 return -EINVAL;
1517
1518 if (sel->flags != 0)
1519 return -EINVAL;
1520
1521 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
1522 *dcrop = *rkisp_update_crop(stream, &sel->r, input_win);
1523 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1524 "stream %d crop(%d,%d)/%dx%d\n", stream->id,
1525 dcrop->left, dcrop->top, dcrop->width, dcrop->height);
1526
1527 return 0;
1528 }
1529
rkisp_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1530 static int rkisp_querycap(struct file *file, void *priv,
1531 struct v4l2_capability *cap)
1532 {
1533 struct rkisp_stream *stream = video_drvdata(file);
1534 struct device *dev = stream->ispdev->dev;
1535 struct video_device *vdev = video_devdata(file);
1536
1537 strlcpy(cap->card, vdev->name, sizeof(cap->card));
1538 snprintf(cap->driver, sizeof(cap->driver),
1539 "%s_v%d", dev->driver->name,
1540 stream->ispdev->isp_ver >> 4);
1541 snprintf(cap->bus_info, sizeof(cap->bus_info),
1542 "platform:%s", dev_name(dev));
1543 cap->version = RKISP_DRIVER_VERSION;
1544 return 0;
1545 }
1546
1547 static const struct v4l2_ioctl_ops rkisp_v4l2_ioctl_ops = {
1548 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1549 .vidioc_querybuf = vb2_ioctl_querybuf,
1550 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1551 .vidioc_qbuf = vb2_ioctl_qbuf,
1552 .vidioc_expbuf = vb2_ioctl_expbuf,
1553 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1554 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1555 .vidioc_streamon = vb2_ioctl_streamon,
1556 .vidioc_streamoff = vb2_ioctl_streamoff,
1557 .vidioc_enum_input = rkisp_enum_input,
1558 .vidioc_try_fmt_vid_cap_mplane = rkisp_try_fmt_vid_cap_mplane,
1559 .vidioc_enum_fmt_vid_cap = rkisp_enum_fmt_vid_cap_mplane,
1560 .vidioc_s_fmt_vid_cap_mplane = rkisp_s_fmt_vid_cap_mplane,
1561 .vidioc_g_fmt_vid_cap_mplane = rkisp_g_fmt_vid_cap_mplane,
1562 .vidioc_s_selection = rkisp_s_selection,
1563 .vidioc_g_selection = rkisp_g_selection,
1564 .vidioc_querycap = rkisp_querycap,
1565 .vidioc_enum_frameintervals = rkisp_enum_frameintervals,
1566 .vidioc_enum_framesizes = rkisp_enum_framesizes,
1567 .vidioc_default = rkisp_ioctl_default,
1568 };
1569
rkisp_buf_done_task(unsigned long arg)1570 static void rkisp_buf_done_task(unsigned long arg)
1571 {
1572 struct rkisp_stream *stream = (struct rkisp_stream *)arg;
1573 struct rkisp_buffer *buf = NULL;
1574 unsigned long lock_flags = 0;
1575 LIST_HEAD(local_list);
1576
1577 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1578 list_replace_init(&stream->buf_done_list, &local_list);
1579 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1580
1581 while (!list_empty(&local_list)) {
1582 buf = list_first_entry(&local_list,
1583 struct rkisp_buffer, queue);
1584 list_del(&buf->queue);
1585
1586 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
1587 "stream:%d seq:%d buf:0x%x done\n",
1588 stream->id, buf->vb.sequence, buf->buff_addr[0]);
1589 vb2_buffer_done(&buf->vb.vb2_buf,
1590 stream->streaming ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR);
1591 }
1592 }
1593
rkisp_stream_buf_done(struct rkisp_stream * stream,struct rkisp_buffer * buf)1594 void rkisp_stream_buf_done(struct rkisp_stream *stream,
1595 struct rkisp_buffer *buf)
1596 {
1597 unsigned long lock_flags = 0;
1598
1599 if (!stream || !buf)
1600 return;
1601 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1602 list_add_tail(&buf->queue, &stream->buf_done_list);
1603 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1604 tasklet_schedule(&stream->buf_done_tasklet);
1605 }
1606
rkisp_stream_fast(struct work_struct * work)1607 static void rkisp_stream_fast(struct work_struct *work)
1608 {
1609 struct rkisp_capture_device *cap_dev =
1610 container_of(work, struct rkisp_capture_device, fast_work);
1611 struct rkisp_stream *stream = &cap_dev->stream[0];
1612 struct rkisp_device *ispdev = cap_dev->ispdev;
1613 struct v4l2_subdev *sd = ispdev->active_sensor->sd;
1614 int ret;
1615
1616 if (ispdev->isp_ver != ISP_V32)
1617 return;
1618
1619 rkisp_chk_tb_over(ispdev);
1620 if (ispdev->tb_head.complete != RKISP_TB_OK)
1621 return;
1622 ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
1623 if (ret < 0) {
1624 dev_err(ispdev->dev, "%s PM get fail:%d\n", __func__, ret);
1625 ispdev->is_thunderboot = false;
1626 return;
1627 }
1628
1629 if (ispdev->hw_dev->dev_num > 1)
1630 ispdev->hw_dev->is_single = false;
1631 ispdev->is_pre_on = true;
1632 ispdev->is_rdbk_auto = true;
1633 ispdev->pipe.open(&ispdev->pipe, &stream->vnode.vdev.entity, true);
1634 v4l2_subdev_call(sd, video, s_stream, true);
1635 }
1636
rkisp_unregister_stream_vdev(struct rkisp_stream * stream)1637 void rkisp_unregister_stream_vdev(struct rkisp_stream *stream)
1638 {
1639 tasklet_kill(&stream->buf_done_tasklet);
1640 media_entity_cleanup(&stream->vnode.vdev.entity);
1641 video_unregister_device(&stream->vnode.vdev);
1642 }
1643
rkisp_register_stream_vdev(struct rkisp_stream * stream)1644 int rkisp_register_stream_vdev(struct rkisp_stream *stream)
1645 {
1646 struct rkisp_device *dev = stream->ispdev;
1647 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1648 struct video_device *vdev = &stream->vnode.vdev;
1649 struct rkisp_vdev_node *node;
1650 struct media_entity *source, *sink;
1651 int ret = 0, pad;
1652
1653 mutex_init(&stream->apilock);
1654 node = vdev_to_node(vdev);
1655
1656 vdev->ioctl_ops = &rkisp_v4l2_ioctl_ops;
1657 vdev->release = video_device_release_empty;
1658 vdev->fops = &rkisp_fops;
1659 vdev->minor = -1;
1660 vdev->v4l2_dev = v4l2_dev;
1661 vdev->lock = &stream->apilock;
1662 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1663 V4L2_CAP_STREAMING;
1664 video_set_drvdata(vdev, stream);
1665 vdev->vfl_dir = VFL_DIR_RX;
1666 node->pad.flags = MEDIA_PAD_FL_SINK;
1667 vdev->queue = &node->buf_queue;
1668
1669 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1670 if (ret < 0) {
1671 v4l2_err(v4l2_dev,
1672 "video_register_device failed with error %d\n", ret);
1673 return ret;
1674 }
1675
1676 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1677 if (ret < 0)
1678 goto unreg;
1679
1680 source = &dev->csi_dev.sd.entity;
1681 switch (stream->id) {
1682 case RKISP_STREAM_DMATX0://CSI_SRC_CH1
1683 case RKISP_STREAM_DMATX1://CSI_SRC_CH2
1684 case RKISP_STREAM_DMATX2://CSI_SRC_CH3
1685 case RKISP_STREAM_DMATX3://CSI_SRC_CH4
1686 pad = stream->id;
1687 dev->csi_dev.sink[pad - 1].linked = true;
1688 dev->csi_dev.sink[pad - 1].index = BIT(pad - 1);
1689 break;
1690 default:
1691 source = &dev->isp_sdev.sd.entity;
1692 pad = RKISP_ISP_PAD_SOURCE_PATH;
1693 }
1694 sink = &vdev->entity;
1695 ret = media_create_pad_link(source, pad,
1696 sink, 0, stream->linked);
1697 if (ret < 0)
1698 goto unreg;
1699 INIT_LIST_HEAD(&stream->buf_done_list);
1700 tasklet_init(&stream->buf_done_tasklet,
1701 rkisp_buf_done_task,
1702 (unsigned long)stream);
1703 tasklet_disable(&stream->buf_done_tasklet);
1704 return 0;
1705 unreg:
1706 video_unregister_device(vdev);
1707 return ret;
1708 }
1709
rkisp_register_stream_vdevs(struct rkisp_device * dev)1710 int rkisp_register_stream_vdevs(struct rkisp_device *dev)
1711 {
1712 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1713 struct stream_config *st_cfg = &rkisp_mp_stream_config;
1714 int ret = 0;
1715
1716 memset(cap_dev, 0, sizeof(*cap_dev));
1717 cap_dev->ispdev = dev;
1718 atomic_set(&cap_dev->refcnt, 0);
1719
1720 if (dev->isp_ver <= ISP_V13) {
1721 if (dev->isp_ver == ISP_V12) {
1722 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V12;
1723 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V12;
1724 } else if (dev->isp_ver == ISP_V13) {
1725 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V13;
1726 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V13;
1727 }
1728 ret = rkisp_register_stream_v1x(dev);
1729 } else if (dev->isp_ver == ISP_V20) {
1730 ret = rkisp_register_stream_v20(dev);
1731 } else if (dev->isp_ver == ISP_V21) {
1732 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V21;
1733 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21;
1734 ret = rkisp_register_stream_v21(dev);
1735 } else if (dev->isp_ver == ISP_V30) {
1736 st_cfg->max_rsz_width = dev->hw_dev->is_unite ?
1737 CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
1738 st_cfg->max_rsz_height = dev->hw_dev->is_unite ?
1739 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
1740 ret = rkisp_register_stream_v30(dev);
1741 } else if (dev->isp_ver == ISP_V32) {
1742 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
1743 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
1744 st_cfg = &rkisp_sp_stream_config;
1745 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
1746 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
1747 ret = rkisp_register_stream_v32(dev);
1748 } else if (dev->isp_ver == ISP_V32_L) {
1749 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;
1750 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L;
1751 st_cfg = &rkisp_sp_stream_config;
1752 st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;
1753 st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L;
1754 ret = rkisp_register_stream_v32(dev);
1755 }
1756
1757 INIT_WORK(&cap_dev->fast_work, rkisp_stream_fast);
1758 return ret;
1759 }
1760
rkisp_unregister_stream_vdevs(struct rkisp_device * dev)1761 void rkisp_unregister_stream_vdevs(struct rkisp_device *dev)
1762 {
1763 if (dev->isp_ver <= ISP_V13)
1764 rkisp_unregister_stream_v1x(dev);
1765 else if (dev->isp_ver == ISP_V20)
1766 rkisp_unregister_stream_v20(dev);
1767 else if (dev->isp_ver == ISP_V21)
1768 rkisp_unregister_stream_v21(dev);
1769 else if (dev->isp_ver == ISP_V30)
1770 rkisp_unregister_stream_v30(dev);
1771 else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
1772 rkisp_unregister_stream_v32(dev);
1773 }
1774
rkisp_mi_isr(u32 mis_val,struct rkisp_device * dev)1775 void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
1776 {
1777 if (dev->isp_ver <= ISP_V13)
1778 rkisp_mi_v1x_isr(mis_val, dev);
1779 else if (dev->isp_ver == ISP_V20)
1780 rkisp_mi_v20_isr(mis_val, dev);
1781 else if (dev->isp_ver == ISP_V21)
1782 rkisp_mi_v21_isr(mis_val, dev);
1783 else if (dev->isp_ver == ISP_V30)
1784 rkisp_mi_v30_isr(mis_val, dev);
1785 else if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V32_L)
1786 rkisp_mi_v32_isr(mis_val, dev);
1787 }
1788