xref: /OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/cif/dev.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Rockchip CIF Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _RKCIF_DEV_H
9*4882a593Smuzhiyun #define _RKCIF_DEV_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <media/media-device.h>
13*4882a593Smuzhiyun #include <media/media-entity.h>
14*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
15*4882a593Smuzhiyun #include <media/v4l2-device.h>
16*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
17*4882a593Smuzhiyun #include <media/v4l2-mc.h>
18*4882a593Smuzhiyun #include <linux/workqueue.h>
19*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
20*4882a593Smuzhiyun #include <linux/rkcif-config.h>
21*4882a593Smuzhiyun #include <linux/soc/rockchip/rockchip_thunderboot_service.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "regs.h"
24*4882a593Smuzhiyun #include "version.h"
25*4882a593Smuzhiyun #include "cif-luma.h"
26*4882a593Smuzhiyun #include "mipi-csi2.h"
27*4882a593Smuzhiyun #include "hw.h"
28*4882a593Smuzhiyun #include "subdev-itf.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CPU_RV1106)
31*4882a593Smuzhiyun #include <linux/soc/rockchip/rk_sdmmc.h>
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define CIF_DRIVER_NAME		"rkcif"
35*4882a593Smuzhiyun #define CIF_VIDEODEVICE_NAME	"stream_cif"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define OF_CIF_MONITOR_PARA	"rockchip,cif-monitor"
38*4882a593Smuzhiyun #define OF_CIF_WAIT_LINE	"wait-line"
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define CIF_MONITOR_PARA_NUM	(5)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define RKCIF_SINGLE_STREAM	1
43*4882a593Smuzhiyun #define RKCIF_STREAM_CIF	0
44*4882a593Smuzhiyun #define CIF_DVP_VDEV_NAME CIF_VIDEODEVICE_NAME		"_dvp"
45*4882a593Smuzhiyun #define CIF_MIPI_ID0_VDEV_NAME CIF_VIDEODEVICE_NAME	"_mipi_id0"
46*4882a593Smuzhiyun #define CIF_MIPI_ID1_VDEV_NAME CIF_VIDEODEVICE_NAME	"_mipi_id1"
47*4882a593Smuzhiyun #define CIF_MIPI_ID2_VDEV_NAME CIF_VIDEODEVICE_NAME	"_mipi_id2"
48*4882a593Smuzhiyun #define CIF_MIPI_ID3_VDEV_NAME CIF_VIDEODEVICE_NAME	"_mipi_id3"
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define CIF_DVP_ID0_VDEV_NAME CIF_VIDEODEVICE_NAME	"_dvp_id0"
51*4882a593Smuzhiyun #define CIF_DVP_ID1_VDEV_NAME CIF_VIDEODEVICE_NAME	"_dvp_id1"
52*4882a593Smuzhiyun #define CIF_DVP_ID2_VDEV_NAME CIF_VIDEODEVICE_NAME	"_dvp_id2"
53*4882a593Smuzhiyun #define CIF_DVP_ID3_VDEV_NAME CIF_VIDEODEVICE_NAME	"_dvp_id3"
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define RKCIF_PLANE_Y		0
56*4882a593Smuzhiyun #define RKCIF_PLANE_CBCR	1
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun  * RK1808 support 5 channel inputs simultaneously:
60*4882a593Smuzhiyun  * dvp + 4 mipi virtual channels;
61*4882a593Smuzhiyun  * RV1126/RK356X support 4 channels of BT.656/BT.1120/MIPI
62*4882a593Smuzhiyun  */
63*4882a593Smuzhiyun #define RKCIF_MULTI_STREAMS_NUM	5
64*4882a593Smuzhiyun #define RKCIF_STREAM_MIPI_ID0	0
65*4882a593Smuzhiyun #define RKCIF_STREAM_MIPI_ID1	1
66*4882a593Smuzhiyun #define RKCIF_STREAM_MIPI_ID2	2
67*4882a593Smuzhiyun #define RKCIF_STREAM_MIPI_ID3	3
68*4882a593Smuzhiyun #define RKCIF_MAX_STREAM_MIPI	4
69*4882a593Smuzhiyun #define RKCIF_MAX_STREAM_LVDS	4
70*4882a593Smuzhiyun #define RKCIF_MAX_STREAM_DVP	4
71*4882a593Smuzhiyun #define RKCIF_STREAM_DVP	4
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define RKCIF_MAX_SENSOR	2
74*4882a593Smuzhiyun #define RKCIF_MAX_CSI_CHANNEL	4
75*4882a593Smuzhiyun #define RKCIF_MAX_PIPELINE	4
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define RKCIF_DEFAULT_WIDTH	640
78*4882a593Smuzhiyun #define RKCIF_DEFAULT_HEIGHT	480
79*4882a593Smuzhiyun #define RKCIF_FS_DETECTED_NUM	2
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define RKCIF_MAX_INTERVAL_NS	5000000
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun  * for HDR mode sync buf
84*4882a593Smuzhiyun  */
85*4882a593Smuzhiyun #define RDBK_MAX		3
86*4882a593Smuzhiyun #define RDBK_TOISP_MAX		2
87*4882a593Smuzhiyun #define RDBK_L			0
88*4882a593Smuzhiyun #define RDBK_M			1
89*4882a593Smuzhiyun #define RDBK_S			2
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun  * for distinguishing cropping from senosr or usr
93*4882a593Smuzhiyun  */
94*4882a593Smuzhiyun #define CROP_SRC_SENSOR_MASK		(0x1 << 0)
95*4882a593Smuzhiyun #define CROP_SRC_USR_MASK		(0x1 << 1)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun enum rkcif_workmode {
98*4882a593Smuzhiyun 	RKCIF_WORKMODE_ONEFRAME = 0x00,
99*4882a593Smuzhiyun 	RKCIF_WORKMODE_PINGPONG = 0x01,
100*4882a593Smuzhiyun 	RKCIF_WORKMODE_LINELOOP = 0x02
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun enum rkcif_stream_mode {
104*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_NONE       = 0x0,
105*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_CAPTURE    = 0x01,
106*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_TOISP      = 0x02,
107*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_TOSCALE    = 0x04,
108*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_TOISP_RDBK = 0x08,
109*4882a593Smuzhiyun 	RKCIF_STREAM_MODE_ROCKIT     = 0x10
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun enum rkcif_yuvaddr_state {
113*4882a593Smuzhiyun 	RKCIF_YUV_ADDR_STATE_UPDATE = 0x0,
114*4882a593Smuzhiyun 	RKCIF_YUV_ADDR_STATE_INIT = 0x1
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun enum rkcif_state {
118*4882a593Smuzhiyun 	RKCIF_STATE_DISABLED,
119*4882a593Smuzhiyun 	RKCIF_STATE_READY,
120*4882a593Smuzhiyun 	RKCIF_STATE_STREAMING,
121*4882a593Smuzhiyun 	RKCIF_STATE_RESET_IN_STREAMING,
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun enum rkcif_lvds_pad {
125*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SINK = 0x0,
126*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SRC_ID0,
127*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SRC_ID1,
128*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SRC_ID2,
129*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SRC_ID3,
130*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SCL_ID0,
131*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SCL_ID1,
132*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SCL_ID2,
133*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_SCL_ID3,
134*4882a593Smuzhiyun 	RKCIF_LVDS_PAD_MAX,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun enum rkcif_lvds_state {
138*4882a593Smuzhiyun 	RKCIF_LVDS_STOP = 0,
139*4882a593Smuzhiyun 	RKCIF_LVDS_START,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun enum rkcif_inf_id {
143*4882a593Smuzhiyun 	RKCIF_DVP,
144*4882a593Smuzhiyun 	RKCIF_MIPI_LVDS,
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun enum rkcif_clk_edge {
148*4882a593Smuzhiyun 	RKCIF_CLK_RISING = 0x0,
149*4882a593Smuzhiyun 	RKCIF_CLK_FALLING,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun  * for distinguishing cropping from senosr or usr
154*4882a593Smuzhiyun  */
155*4882a593Smuzhiyun enum rkcif_crop_src {
156*4882a593Smuzhiyun 	CROP_SRC_ACT	= 0x0,
157*4882a593Smuzhiyun 	CROP_SRC_SENSOR,
158*4882a593Smuzhiyun 	CROP_SRC_USR,
159*4882a593Smuzhiyun 	CROP_SRC_MAX
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun  * struct rkcif_pipeline - An CIF hardware pipeline
164*4882a593Smuzhiyun  *
165*4882a593Smuzhiyun  * Capture device call other devices via pipeline
166*4882a593Smuzhiyun  *
167*4882a593Smuzhiyun  * @num_subdevs: number of linked subdevs
168*4882a593Smuzhiyun  * @power_cnt: pipeline power count
169*4882a593Smuzhiyun  * @stream_cnt: stream power count
170*4882a593Smuzhiyun  */
171*4882a593Smuzhiyun struct rkcif_pipeline {
172*4882a593Smuzhiyun 	struct media_pipeline pipe;
173*4882a593Smuzhiyun 	int num_subdevs;
174*4882a593Smuzhiyun 	atomic_t power_cnt;
175*4882a593Smuzhiyun 	atomic_t stream_cnt;
176*4882a593Smuzhiyun 	struct v4l2_subdev *subdevs[RKCIF_MAX_PIPELINE];
177*4882a593Smuzhiyun 	int (*open)(struct rkcif_pipeline *p,
178*4882a593Smuzhiyun 		    struct media_entity *me, bool prepare);
179*4882a593Smuzhiyun 	int (*close)(struct rkcif_pipeline *p);
180*4882a593Smuzhiyun 	int (*set_stream)(struct rkcif_pipeline *p, bool on);
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun struct rkcif_buffer {
184*4882a593Smuzhiyun 	struct vb2_v4l2_buffer vb;
185*4882a593Smuzhiyun 	struct list_head queue;
186*4882a593Smuzhiyun 	union {
187*4882a593Smuzhiyun 		u32 buff_addr[VIDEO_MAX_PLANES];
188*4882a593Smuzhiyun 		void *vaddr[VIDEO_MAX_PLANES];
189*4882a593Smuzhiyun 	};
190*4882a593Smuzhiyun 	struct dma_buf *dbuf;
191*4882a593Smuzhiyun 	u64 fe_timestamp;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun struct rkcif_tools_buffer {
195*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vb;
196*4882a593Smuzhiyun 	struct rkisp_rx_buf *dbufs;
197*4882a593Smuzhiyun 	struct list_head list;
198*4882a593Smuzhiyun 	u32 frame_idx;
199*4882a593Smuzhiyun 	u64 timestamp;
200*4882a593Smuzhiyun 	int use_cnt;
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun extern int rkcif_debug;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun /*
206*4882a593Smuzhiyun  * struct rkcif_sensor_info - Sensor infomations
207*4882a593Smuzhiyun  * @sd: v4l2 subdev of sensor
208*4882a593Smuzhiyun  * @mbus: media bus configuration
209*4882a593Smuzhiyun  * @fi: v4l2 subdev frame interval
210*4882a593Smuzhiyun  * @lanes: lane num of sensor
211*4882a593Smuzhiyun  * @raw_rect: raw output rectangle of sensor, not crop or selection
212*4882a593Smuzhiyun  * @selection: selection info of sensor
213*4882a593Smuzhiyun  */
214*4882a593Smuzhiyun struct rkcif_sensor_info {
215*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
216*4882a593Smuzhiyun 	struct v4l2_mbus_config mbus;
217*4882a593Smuzhiyun 	struct v4l2_subdev_frame_interval fi;
218*4882a593Smuzhiyun 	int lanes;
219*4882a593Smuzhiyun 	struct v4l2_rect raw_rect;
220*4882a593Smuzhiyun 	struct v4l2_subdev_selection selection;
221*4882a593Smuzhiyun 	int dsi_input_en;
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun enum cif_fmt_type {
225*4882a593Smuzhiyun 	CIF_FMT_TYPE_YUV = 0,
226*4882a593Smuzhiyun 	CIF_FMT_TYPE_RAW,
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun /*
230*4882a593Smuzhiyun  * struct cif_output_fmt - The output format
231*4882a593Smuzhiyun  *
232*4882a593Smuzhiyun  * @bpp: bits per pixel for each cplanes
233*4882a593Smuzhiyun  * @fourcc: pixel format in fourcc
234*4882a593Smuzhiyun  * @fmt_val: the fmt val corresponding to CIF_FOR register
235*4882a593Smuzhiyun  * @csi_fmt_val: the fmt val corresponding to CIF_CSI_ID_CTRL
236*4882a593Smuzhiyun  * @cplanes: number of colour planes
237*4882a593Smuzhiyun  * @mplanes: number of planes for format
238*4882a593Smuzhiyun  * @raw_bpp: bits per pixel for raw format
239*4882a593Smuzhiyun  * @fmt_type: image format, raw or yuv
240*4882a593Smuzhiyun  */
241*4882a593Smuzhiyun struct cif_output_fmt {
242*4882a593Smuzhiyun 	u8 bpp[VIDEO_MAX_PLANES];
243*4882a593Smuzhiyun 	u32 fourcc;
244*4882a593Smuzhiyun 	u32 fmt_val;
245*4882a593Smuzhiyun 	u32 csi_fmt_val;
246*4882a593Smuzhiyun 	u8 cplanes;
247*4882a593Smuzhiyun 	u8 mplanes;
248*4882a593Smuzhiyun 	u8 raw_bpp;
249*4882a593Smuzhiyun 	enum cif_fmt_type fmt_type;
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun /*
253*4882a593Smuzhiyun  * struct cif_input_fmt - The input mbus format from sensor
254*4882a593Smuzhiyun  *
255*4882a593Smuzhiyun  * @mbus_code: mbus format
256*4882a593Smuzhiyun  * @dvp_fmt_val: the fmt val corresponding to CIF_FOR register
257*4882a593Smuzhiyun  * @csi_fmt_val: the fmt val corresponding to CIF_CSI_ID_CTRL
258*4882a593Smuzhiyun  * @fmt_type: image format, raw or yuv
259*4882a593Smuzhiyun  * @field: the field type of the input from sensor
260*4882a593Smuzhiyun  */
261*4882a593Smuzhiyun struct cif_input_fmt {
262*4882a593Smuzhiyun 	u32 mbus_code;
263*4882a593Smuzhiyun 	u32 dvp_fmt_val;
264*4882a593Smuzhiyun 	u32 csi_fmt_val;
265*4882a593Smuzhiyun 	u32 csi_yuv_order;
266*4882a593Smuzhiyun 	enum cif_fmt_type fmt_type;
267*4882a593Smuzhiyun 	enum v4l2_field field;
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun struct csi_channel_info {
271*4882a593Smuzhiyun 	unsigned char id;
272*4882a593Smuzhiyun 	unsigned char enable;	/* capture enable */
273*4882a593Smuzhiyun 	unsigned char vc;
274*4882a593Smuzhiyun 	unsigned char data_type;
275*4882a593Smuzhiyun 	unsigned char data_bit;
276*4882a593Smuzhiyun 	unsigned char crop_en;
277*4882a593Smuzhiyun 	unsigned char cmd_mode_en;
278*4882a593Smuzhiyun 	unsigned char fmt_val;
279*4882a593Smuzhiyun 	unsigned char csi_fmt_val;
280*4882a593Smuzhiyun 	unsigned int width;
281*4882a593Smuzhiyun 	unsigned int height;
282*4882a593Smuzhiyun 	unsigned int virtual_width;
283*4882a593Smuzhiyun 	unsigned int left_virtual_width;
284*4882a593Smuzhiyun 	unsigned int crop_st_x;
285*4882a593Smuzhiyun 	unsigned int crop_st_y;
286*4882a593Smuzhiyun 	unsigned int dsi_input;
287*4882a593Smuzhiyun 	struct rkmodule_lvds_cfg lvds_cfg;
288*4882a593Smuzhiyun 	struct rkmodule_capture_info capture_info;
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun struct rkcif_vdev_node {
292*4882a593Smuzhiyun 	struct vb2_queue buf_queue;
293*4882a593Smuzhiyun 	/* vfd lock */
294*4882a593Smuzhiyun 	struct mutex vlock;
295*4882a593Smuzhiyun 	struct video_device vdev;
296*4882a593Smuzhiyun 	struct media_pad pad;
297*4882a593Smuzhiyun };
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /*
300*4882a593Smuzhiyun  * the mark that csi frame0/1 interrupts enabled
301*4882a593Smuzhiyun  * in CIF_MIPI_INTEN
302*4882a593Smuzhiyun  */
303*4882a593Smuzhiyun enum cif_frame_ready {
304*4882a593Smuzhiyun 	CIF_CSI_FRAME0_READY = 0x1,
305*4882a593Smuzhiyun 	CIF_CSI_FRAME1_READY
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun /* struct rkcif_hdr - hdr configured
309*4882a593Smuzhiyun  * @op_mode: hdr optional mode
310*4882a593Smuzhiyun  */
311*4882a593Smuzhiyun struct rkcif_hdr {
312*4882a593Smuzhiyun 	u8 mode;
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun /* struct rkcif_fps_stats - take notes on timestamp of buf
316*4882a593Smuzhiyun  * @frm0_timestamp: timesstamp of buf in frm0
317*4882a593Smuzhiyun  * @frm1_timestamp: timesstamp of buf in frm1
318*4882a593Smuzhiyun  */
319*4882a593Smuzhiyun struct rkcif_fps_stats {
320*4882a593Smuzhiyun 	u64 frm0_timestamp;
321*4882a593Smuzhiyun 	u64 frm1_timestamp;
322*4882a593Smuzhiyun };
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun /* struct rkcif_fps_stats - take notes on timestamp of buf
325*4882a593Smuzhiyun  * @fs_timestamp: timesstamp of frame start
326*4882a593Smuzhiyun  * @fe_timestamp: timesstamp of frame end
327*4882a593Smuzhiyun  * @wk_timestamp: timesstamp of buf send to user in wake up mode
328*4882a593Smuzhiyun  * @readout_time: one frame of readout time
329*4882a593Smuzhiyun  * @early_time: early time of buf send to user
330*4882a593Smuzhiyun  * @total_time: totaltime of readout time in hdr
331*4882a593Smuzhiyun  */
332*4882a593Smuzhiyun struct rkcif_readout_stats {
333*4882a593Smuzhiyun 	u64 fs_timestamp;
334*4882a593Smuzhiyun 	u64 fe_timestamp;
335*4882a593Smuzhiyun 	u64 wk_timestamp;
336*4882a593Smuzhiyun 	u64 readout_time;
337*4882a593Smuzhiyun 	u64 early_time;
338*4882a593Smuzhiyun 	u64 total_time;
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun /* struct rkcif_irq_stats - take notes on irq number
342*4882a593Smuzhiyun  * @csi_overflow_cnt: count of csi overflow irq
343*4882a593Smuzhiyun  * @csi_bwidth_lack_cnt: count of csi bandwidth lack irq
344*4882a593Smuzhiyun  * @dvp_bus_err_cnt: count of dvp bus err irq
345*4882a593Smuzhiyun  * @dvp_overflow_cnt: count dvp overflow irq
346*4882a593Smuzhiyun  * @dvp_line_err_cnt: count dvp line err irq
347*4882a593Smuzhiyun  * @dvp_pix_err_cnt: count dvp pix err irq
348*4882a593Smuzhiyun  * @all_frm_end_cnt: raw frame end count
349*4882a593Smuzhiyun  * @all_err_cnt: all err count
350*4882a593Smuzhiyun  * @
351*4882a593Smuzhiyun  */
352*4882a593Smuzhiyun struct rkcif_irq_stats {
353*4882a593Smuzhiyun 	u64 csi_overflow_cnt;
354*4882a593Smuzhiyun 	u64 csi_bwidth_lack_cnt;
355*4882a593Smuzhiyun 	u64 csi_size_err_cnt;
356*4882a593Smuzhiyun 	u64 dvp_bus_err_cnt;
357*4882a593Smuzhiyun 	u64 dvp_overflow_cnt;
358*4882a593Smuzhiyun 	u64 dvp_line_err_cnt;
359*4882a593Smuzhiyun 	u64 dvp_pix_err_cnt;
360*4882a593Smuzhiyun 	u64 dvp_size_err_cnt;
361*4882a593Smuzhiyun 	u64 dvp_bwidth_lack_cnt;
362*4882a593Smuzhiyun 	u64 frm_end_cnt[RKCIF_MAX_STREAM_MIPI];
363*4882a593Smuzhiyun 	u64 not_active_buf_cnt[RKCIF_MAX_STREAM_MIPI];
364*4882a593Smuzhiyun 	u64 trig_simult_cnt[RKCIF_MAX_STREAM_MIPI];
365*4882a593Smuzhiyun 	u64 all_err_cnt;
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun /*
369*4882a593Smuzhiyun  * the detecting mode of cif reset timer
370*4882a593Smuzhiyun  * related with dts property:rockchip,cif-monitor
371*4882a593Smuzhiyun  */
372*4882a593Smuzhiyun enum rkcif_monitor_mode {
373*4882a593Smuzhiyun 	RKCIF_MONITOR_MODE_IDLE = 0x0,
374*4882a593Smuzhiyun 	RKCIF_MONITOR_MODE_CONTINUE,
375*4882a593Smuzhiyun 	RKCIF_MONITOR_MODE_TRIGGER,
376*4882a593Smuzhiyun 	RKCIF_MONITOR_MODE_HOTPLUG,
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun /*
380*4882a593Smuzhiyun  * the parameters to resume when reset cif in running
381*4882a593Smuzhiyun  */
382*4882a593Smuzhiyun struct rkcif_resume_info {
383*4882a593Smuzhiyun 	u32 frm_sync_seq;
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun struct rkcif_work_struct {
387*4882a593Smuzhiyun 	struct work_struct	work;
388*4882a593Smuzhiyun 	enum rkmodule_reset_src	reset_src;
389*4882a593Smuzhiyun 	struct rkcif_resume_info	resume_info;
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun struct rkcif_timer {
393*4882a593Smuzhiyun 	struct timer_list	timer;
394*4882a593Smuzhiyun 	spinlock_t		timer_lock;
395*4882a593Smuzhiyun 	spinlock_t		csi2_err_lock;
396*4882a593Smuzhiyun 	unsigned long		cycle;
397*4882a593Smuzhiyun 	/* unit: us */
398*4882a593Smuzhiyun 	unsigned long		line_end_cycle;
399*4882a593Smuzhiyun 	unsigned int		run_cnt;
400*4882a593Smuzhiyun 	unsigned int		max_run_cnt;
401*4882a593Smuzhiyun 	unsigned int		stop_index_of_run_cnt;
402*4882a593Smuzhiyun 	unsigned int		last_buf_wakeup_cnt[RKCIF_MAX_STREAM_MIPI];
403*4882a593Smuzhiyun 	unsigned long		csi2_err_cnt_even;
404*4882a593Smuzhiyun 	unsigned long		csi2_err_cnt_odd;
405*4882a593Smuzhiyun 	unsigned int		csi2_err_ref_cnt;
406*4882a593Smuzhiyun 	unsigned int		csi2_err_fs_fe_cnt;
407*4882a593Smuzhiyun 	unsigned int		csi2_err_fs_fe_detect_cnt;
408*4882a593Smuzhiyun 	unsigned int		frm_num_of_monitor_cycle;
409*4882a593Smuzhiyun 	unsigned int		triggered_frame_num;
410*4882a593Smuzhiyun 	unsigned int		vts;
411*4882a593Smuzhiyun 	unsigned int		raw_height;
412*4882a593Smuzhiyun 	/* unit: ms */
413*4882a593Smuzhiyun 	unsigned int		err_time_interval;
414*4882a593Smuzhiyun 	unsigned int		csi2_err_triggered_cnt;
415*4882a593Smuzhiyun 	unsigned int		notifer_called_cnt;
416*4882a593Smuzhiyun 	unsigned long		frame_end_cycle_us;
417*4882a593Smuzhiyun 	u64			csi2_first_err_timestamp;
418*4882a593Smuzhiyun 	bool			is_triggered;
419*4882a593Smuzhiyun 	bool			is_buf_stop_update;
420*4882a593Smuzhiyun 	bool			is_running;
421*4882a593Smuzhiyun 	bool			is_csi2_err_occurred;
422*4882a593Smuzhiyun 	bool			has_been_init;
423*4882a593Smuzhiyun 	bool			is_ctrl_by_user;
424*4882a593Smuzhiyun 	enum rkcif_monitor_mode	monitor_mode;
425*4882a593Smuzhiyun 	enum rkmodule_reset_src	reset_src;
426*4882a593Smuzhiyun };
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun struct rkcif_extend_info {
429*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane	pixm;
430*4882a593Smuzhiyun 	bool is_extended;
431*4882a593Smuzhiyun };
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun enum rkcif_capture_mode {
434*4882a593Smuzhiyun 	RKCIF_TO_DDR = 0,
435*4882a593Smuzhiyun 	RKCIF_TO_ISP_DDR,
436*4882a593Smuzhiyun 	RKCIF_TO_ISP_DMA,
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun /*
440*4882a593Smuzhiyun  * list: used for buf rotation
441*4882a593Smuzhiyun  * list_free: only used to release buf asynchronously
442*4882a593Smuzhiyun  */
443*4882a593Smuzhiyun struct rkcif_rx_buffer {
444*4882a593Smuzhiyun 	int buf_idx;
445*4882a593Smuzhiyun 	struct list_head list;
446*4882a593Smuzhiyun 	struct list_head list_free;
447*4882a593Smuzhiyun 	struct rkisp_rx_buf dbufs;
448*4882a593Smuzhiyun 	struct rkcif_dummy_buffer dummy;
449*4882a593Smuzhiyun 	struct rkisp_thunderboot_shmem shmem;
450*4882a593Smuzhiyun 	u64 fe_timestamp;
451*4882a593Smuzhiyun };
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun enum rkcif_dma_en_mode {
454*4882a593Smuzhiyun 	RKCIF_DMAEN_BY_VICAP = 0x1,
455*4882a593Smuzhiyun 	RKCIF_DMAEN_BY_ISP = 0x2,
456*4882a593Smuzhiyun 	RKCIF_DMAEN_BY_VICAP_TO_ISP = 0x4,
457*4882a593Smuzhiyun 	RKCIF_DMAEN_BY_ISP_TO_VICAP = 0x8,
458*4882a593Smuzhiyun 	RKCIF_DMAEN_BY_ROCKIT = 0x10,
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun struct rkcif_skip_info {
462*4882a593Smuzhiyun 	u8 cap_m;
463*4882a593Smuzhiyun 	u8 skip_n;
464*4882a593Smuzhiyun 	bool skip_en;
465*4882a593Smuzhiyun 	bool skip_to_en;
466*4882a593Smuzhiyun 	bool skip_to_dis;
467*4882a593Smuzhiyun };
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun struct rkcif_sync_cfg {
470*4882a593Smuzhiyun 	u32 type;
471*4882a593Smuzhiyun 	u32 group;
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun /*
475*4882a593Smuzhiyun  * struct rkcif_stream - Stream states TODO
476*4882a593Smuzhiyun  *
477*4882a593Smuzhiyun  * @vbq_lock: lock to protect buf_queue
478*4882a593Smuzhiyun  * @buf_queue: queued buffer list
479*4882a593Smuzhiyun  * @dummy_buf: dummy space to store dropped data
480*4882a593Smuzhiyun  * @crop_enable: crop status when stream off
481*4882a593Smuzhiyun  * @crop_dyn_en: crop status when streaming
482*4882a593Smuzhiyun  * rkcif use shadowsock registers, so it need two buffer at a time
483*4882a593Smuzhiyun  * @curr_buf: the buffer used for current frame
484*4882a593Smuzhiyun  * @next_buf: the buffer used for next frame
485*4882a593Smuzhiyun  * @fps_lock: to protect parameters about calculating fps
486*4882a593Smuzhiyun  */
487*4882a593Smuzhiyun struct rkcif_stream {
488*4882a593Smuzhiyun 	unsigned id:3;
489*4882a593Smuzhiyun 	struct rkcif_device		*cifdev;
490*4882a593Smuzhiyun 	struct rkcif_vdev_node		vnode;
491*4882a593Smuzhiyun 	enum rkcif_state		state;
492*4882a593Smuzhiyun 	wait_queue_head_t		wq_stopped;
493*4882a593Smuzhiyun 	unsigned int			frame_idx;
494*4882a593Smuzhiyun 	int				frame_phase;
495*4882a593Smuzhiyun 	int				frame_phase_cache;
496*4882a593Smuzhiyun 	unsigned int			crop_mask;
497*4882a593Smuzhiyun 	/* lock between irq and buf_queue */
498*4882a593Smuzhiyun 	struct list_head		buf_head;
499*4882a593Smuzhiyun 	struct rkcif_buffer		*curr_buf;
500*4882a593Smuzhiyun 	struct rkcif_buffer		*next_buf;
501*4882a593Smuzhiyun 	struct rkcif_rx_buffer		*curr_buf_toisp;
502*4882a593Smuzhiyun 	struct rkcif_rx_buffer		*next_buf_toisp;
503*4882a593Smuzhiyun 	struct list_head		rockit_buf_head;
504*4882a593Smuzhiyun 	struct rkcif_buffer		*curr_buf_rockit;
505*4882a593Smuzhiyun 	struct rkcif_buffer		*next_buf_rockit;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	spinlock_t vbq_lock; /* vfd lock */
508*4882a593Smuzhiyun 	spinlock_t fps_lock;
509*4882a593Smuzhiyun 	/* TODO: pad for dvp and mipi separately? */
510*4882a593Smuzhiyun 	struct media_pad		pad;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	const struct cif_output_fmt	*cif_fmt_out;
513*4882a593Smuzhiyun 	const struct cif_input_fmt	*cif_fmt_in;
514*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane	pixm;
515*4882a593Smuzhiyun 	struct v4l2_rect		crop[CROP_SRC_MAX];
516*4882a593Smuzhiyun 	struct rkcif_fps_stats		fps_stats;
517*4882a593Smuzhiyun 	struct rkcif_extend_info	extend_line;
518*4882a593Smuzhiyun 	struct rkcif_readout_stats	readout;
519*4882a593Smuzhiyun 	unsigned int			fs_cnt_in_single_frame;
520*4882a593Smuzhiyun 	unsigned int			capture_mode;
521*4882a593Smuzhiyun 	struct rkcif_scale_vdev		*scale_vdev;
522*4882a593Smuzhiyun 	struct rkcif_tools_vdev		*tools_vdev;
523*4882a593Smuzhiyun 	int				dma_en;
524*4882a593Smuzhiyun 	int				to_en_dma;
525*4882a593Smuzhiyun 	int				to_stop_dma;
526*4882a593Smuzhiyun 	int				buf_owner;
527*4882a593Smuzhiyun 	int				buf_replace_cnt;
528*4882a593Smuzhiyun 	struct list_head		rx_buf_head_vicap;
529*4882a593Smuzhiyun 	unsigned int			cur_stream_mode;
530*4882a593Smuzhiyun 	struct rkcif_rx_buffer		rx_buf[RKISP_VICAP_BUF_CNT_MAX];
531*4882a593Smuzhiyun 	struct list_head		rx_buf_head;
532*4882a593Smuzhiyun 	int				total_buf_num;
533*4882a593Smuzhiyun 	u64				line_int_cnt;
534*4882a593Smuzhiyun 	int				lack_buf_cnt;
535*4882a593Smuzhiyun 	unsigned int			buf_wake_up_cnt;
536*4882a593Smuzhiyun 	struct rkcif_skip_info		skip_info;
537*4882a593Smuzhiyun 	struct tasklet_struct		vb_done_tasklet;
538*4882a593Smuzhiyun 	struct list_head		vb_done_list;
539*4882a593Smuzhiyun 	int				last_rx_buf_idx;
540*4882a593Smuzhiyun 	int				last_frame_idx;
541*4882a593Smuzhiyun 	int				new_fource_idx;
542*4882a593Smuzhiyun 	atomic_t			buf_cnt;
543*4882a593Smuzhiyun 	bool				stopping;
544*4882a593Smuzhiyun 	bool				crop_enable;
545*4882a593Smuzhiyun 	bool				crop_dyn_en;
546*4882a593Smuzhiyun 	bool				is_compact;
547*4882a593Smuzhiyun 	bool				is_dvp_yuv_addr_init;
548*4882a593Smuzhiyun 	bool				is_fs_fe_not_paired;
549*4882a593Smuzhiyun 	bool				is_line_wake_up;
550*4882a593Smuzhiyun 	bool				is_line_inten;
551*4882a593Smuzhiyun 	bool				is_can_stop;
552*4882a593Smuzhiyun 	bool				is_buf_active;
553*4882a593Smuzhiyun 	bool				is_high_align;
554*4882a593Smuzhiyun 	bool				to_en_scale;
555*4882a593Smuzhiyun 	bool				is_finish_stop_dma;
556*4882a593Smuzhiyun 	bool				is_in_vblank;
557*4882a593Smuzhiyun 	bool				is_change_toisp;
558*4882a593Smuzhiyun 	bool				is_stop_capture;
559*4882a593Smuzhiyun };
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun struct rkcif_lvds_subdev {
562*4882a593Smuzhiyun 	struct rkcif_device	*cifdev;
563*4882a593Smuzhiyun 	struct v4l2_subdev sd;
564*4882a593Smuzhiyun 	struct v4l2_subdev *remote_sd;
565*4882a593Smuzhiyun 	struct media_pad pads[RKCIF_LVDS_PAD_MAX];
566*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt in_fmt;
567*4882a593Smuzhiyun 	struct v4l2_rect crop;
568*4882a593Smuzhiyun 	const struct cif_output_fmt	*cif_fmt_out;
569*4882a593Smuzhiyun 	const struct cif_input_fmt	*cif_fmt_in;
570*4882a593Smuzhiyun 	enum rkcif_lvds_state		state;
571*4882a593Smuzhiyun 	struct rkcif_sensor_info	sensor_self;
572*4882a593Smuzhiyun 	atomic_t			frm_sync_seq;
573*4882a593Smuzhiyun };
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun struct rkcif_dvp_sof_subdev {
576*4882a593Smuzhiyun 	struct rkcif_device *cifdev;
577*4882a593Smuzhiyun 	struct v4l2_subdev sd;
578*4882a593Smuzhiyun 	atomic_t			frm_sync_seq;
579*4882a593Smuzhiyun };
580*4882a593Smuzhiyun 
to_rkcif_buffer(struct vb2_v4l2_buffer * vb)581*4882a593Smuzhiyun static inline struct rkcif_buffer *to_rkcif_buffer(struct vb2_v4l2_buffer *vb)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun 	return container_of(vb, struct rkcif_buffer, vb);
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun static inline
vdev_to_node(struct video_device * vdev)587*4882a593Smuzhiyun struct rkcif_vdev_node *vdev_to_node(struct video_device *vdev)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	return container_of(vdev, struct rkcif_vdev_node, vdev);
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun static inline
to_rkcif_stream(struct rkcif_vdev_node * vnode)593*4882a593Smuzhiyun struct rkcif_stream *to_rkcif_stream(struct rkcif_vdev_node *vnode)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun 	return container_of(vnode, struct rkcif_stream, vnode);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun 
queue_to_node(struct vb2_queue * q)598*4882a593Smuzhiyun static inline struct rkcif_vdev_node *queue_to_node(struct vb2_queue *q)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun 	return container_of(q, struct rkcif_vdev_node, buf_queue);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun 
to_vb2_queue(struct file * file)603*4882a593Smuzhiyun static inline struct vb2_queue *to_vb2_queue(struct file *file)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun 	struct rkcif_vdev_node *vnode = video_drvdata(file);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	return &vnode->buf_queue;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun #define SCALE_DRIVER_NAME		"rkcif_scale"
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun #define RKCIF_SCALE_CH0		0
613*4882a593Smuzhiyun #define RKCIF_SCALE_CH1		1
614*4882a593Smuzhiyun #define RKCIF_SCALE_CH2		2
615*4882a593Smuzhiyun #define RKCIF_SCALE_CH3		3
616*4882a593Smuzhiyun #define RKCIF_MAX_SCALE_CH	4
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun #define CIF_SCALE_CH0_VDEV_NAME CIF_DRIVER_NAME	"_scale_ch0"
619*4882a593Smuzhiyun #define CIF_SCALE_CH1_VDEV_NAME CIF_DRIVER_NAME	"_scale_ch1"
620*4882a593Smuzhiyun #define CIF_SCALE_CH2_VDEV_NAME CIF_DRIVER_NAME	"_scale_ch2"
621*4882a593Smuzhiyun #define CIF_SCALE_CH3_VDEV_NAME CIF_DRIVER_NAME	"_scale_ch3"
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun #define RKCIF_SCALE_ENUM_SIZE_MAX	3
624*4882a593Smuzhiyun #define RKCIF_MAX_SDITF			4
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun enum scale_ch_sw {
627*4882a593Smuzhiyun 	SCALE_MIPI0_ID0,
628*4882a593Smuzhiyun 	SCALE_MIPI0_ID1,
629*4882a593Smuzhiyun 	SCALE_MIPI0_ID2,
630*4882a593Smuzhiyun 	SCALE_MIPI0_ID3,
631*4882a593Smuzhiyun 	SCALE_MIPI1_ID0,
632*4882a593Smuzhiyun 	SCALE_MIPI1_ID1,
633*4882a593Smuzhiyun 	SCALE_MIPI1_ID2,
634*4882a593Smuzhiyun 	SCALE_MIPI1_ID3,
635*4882a593Smuzhiyun 	SCALE_MIPI2_ID0,
636*4882a593Smuzhiyun 	SCALE_MIPI2_ID1,
637*4882a593Smuzhiyun 	SCALE_MIPI2_ID2,
638*4882a593Smuzhiyun 	SCALE_MIPI2_ID3,
639*4882a593Smuzhiyun 	SCALE_MIPI3_ID0,
640*4882a593Smuzhiyun 	SCALE_MIPI3_ID1,
641*4882a593Smuzhiyun 	SCALE_MIPI3_ID2,
642*4882a593Smuzhiyun 	SCALE_MIPI3_ID3,
643*4882a593Smuzhiyun 	SCALE_MIPI4_ID0,
644*4882a593Smuzhiyun 	SCALE_MIPI4_ID1,
645*4882a593Smuzhiyun 	SCALE_MIPI4_ID2,
646*4882a593Smuzhiyun 	SCALE_MIPI4_ID3,
647*4882a593Smuzhiyun 	SCALE_MIPI5_ID0,
648*4882a593Smuzhiyun 	SCALE_MIPI5_ID1,
649*4882a593Smuzhiyun 	SCALE_MIPI5_ID2,
650*4882a593Smuzhiyun 	SCALE_MIPI5_ID3,
651*4882a593Smuzhiyun 	SCALE_DVP,
652*4882a593Smuzhiyun 	SCALE_CH_MAX,
653*4882a593Smuzhiyun };
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun enum scale_mode {
656*4882a593Smuzhiyun 	SCALE_8TIMES,
657*4882a593Smuzhiyun 	SCALE_16TIMES,
658*4882a593Smuzhiyun 	SCALE_32TIMES,
659*4882a593Smuzhiyun };
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun struct rkcif_scale_ch_info {
662*4882a593Smuzhiyun 	u32 width;
663*4882a593Smuzhiyun 	u32 height;
664*4882a593Smuzhiyun 	u32 vir_width;
665*4882a593Smuzhiyun };
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun struct rkcif_scale_src_res {
668*4882a593Smuzhiyun 	u32 width;
669*4882a593Smuzhiyun 	u32 height;
670*4882a593Smuzhiyun };
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun /*
673*4882a593Smuzhiyun  * struct rkcif_scale_vdev - CIF Capture device
674*4882a593Smuzhiyun  *
675*4882a593Smuzhiyun  * @irq_lock: buffer queue lock
676*4882a593Smuzhiyun  * @stat: stats buffer list
677*4882a593Smuzhiyun  * @readout_wq: workqueue for statistics information read
678*4882a593Smuzhiyun  */
679*4882a593Smuzhiyun struct rkcif_scale_vdev {
680*4882a593Smuzhiyun 	unsigned int ch:3;
681*4882a593Smuzhiyun 	struct rkcif_device *cifdev;
682*4882a593Smuzhiyun 	struct rkcif_vdev_node vnode;
683*4882a593Smuzhiyun 	struct rkcif_stream *stream;
684*4882a593Smuzhiyun 	struct list_head buf_head;
685*4882a593Smuzhiyun 	spinlock_t vbq_lock; /* vfd lock */
686*4882a593Smuzhiyun 	wait_queue_head_t wq_stopped;
687*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane	pixm;
688*4882a593Smuzhiyun 	const struct cif_output_fmt *scale_out_fmt;
689*4882a593Smuzhiyun 	struct rkcif_scale_ch_info ch_info;
690*4882a593Smuzhiyun 	struct rkcif_scale_src_res src_res;
691*4882a593Smuzhiyun 	struct rkcif_buffer *curr_buf;
692*4882a593Smuzhiyun 	struct rkcif_buffer *next_buf;
693*4882a593Smuzhiyun 	struct bayer_blc blc;
694*4882a593Smuzhiyun 	enum rkcif_state state;
695*4882a593Smuzhiyun 	unsigned int ch_src;
696*4882a593Smuzhiyun 	unsigned int scale_mode;
697*4882a593Smuzhiyun 	int frame_phase;
698*4882a593Smuzhiyun 	unsigned int frame_idx;
699*4882a593Smuzhiyun 	bool stopping;
700*4882a593Smuzhiyun };
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun static inline
to_rkcif_scale_vdev(struct rkcif_vdev_node * vnode)703*4882a593Smuzhiyun struct rkcif_scale_vdev *to_rkcif_scale_vdev(struct rkcif_vdev_node *vnode)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	return container_of(vnode, struct rkcif_scale_vdev, vnode);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun void rkcif_init_scale_vdev(struct rkcif_device *cif_dev, u32 ch);
709*4882a593Smuzhiyun int rkcif_register_scale_vdevs(struct rkcif_device *cif_dev,
710*4882a593Smuzhiyun 				int stream_num,
711*4882a593Smuzhiyun 				bool is_multi_input);
712*4882a593Smuzhiyun void rkcif_unregister_scale_vdevs(struct rkcif_device *cif_dev,
713*4882a593Smuzhiyun 				   int stream_num);
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun #define TOOLS_DRIVER_NAME		"rkcif_tools"
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun #define RKCIF_TOOLS_CH0		0
718*4882a593Smuzhiyun #define RKCIF_TOOLS_CH1		1
719*4882a593Smuzhiyun #define RKCIF_TOOLS_CH2		2
720*4882a593Smuzhiyun #define RKCIF_MAX_TOOLS_CH	3
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun #define CIF_TOOLS_CH0_VDEV_NAME CIF_DRIVER_NAME	"_tools_id0"
723*4882a593Smuzhiyun #define CIF_TOOLS_CH1_VDEV_NAME CIF_DRIVER_NAME	"_tools_id1"
724*4882a593Smuzhiyun #define CIF_TOOLS_CH2_VDEV_NAME CIF_DRIVER_NAME	"_tools_id2"
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun /*
727*4882a593Smuzhiyun  * struct rkcif_tools_vdev - CIF Capture device
728*4882a593Smuzhiyun  *
729*4882a593Smuzhiyun  * @irq_lock: buffer queue lock
730*4882a593Smuzhiyun  * @stat: stats buffer list
731*4882a593Smuzhiyun  * @readout_wq: workqueue for statistics information read
732*4882a593Smuzhiyun  */
733*4882a593Smuzhiyun struct rkcif_tools_vdev {
734*4882a593Smuzhiyun 	unsigned int ch:3;
735*4882a593Smuzhiyun 	struct rkcif_device *cifdev;
736*4882a593Smuzhiyun 	struct rkcif_vdev_node vnode;
737*4882a593Smuzhiyun 	struct rkcif_stream *stream;
738*4882a593Smuzhiyun 	struct list_head buf_head;
739*4882a593Smuzhiyun 	struct list_head buf_done_head;
740*4882a593Smuzhiyun 	struct list_head src_buf_head;
741*4882a593Smuzhiyun 	spinlock_t vbq_lock; /* vfd lock */
742*4882a593Smuzhiyun 	wait_queue_head_t wq_stopped;
743*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane	pixm;
744*4882a593Smuzhiyun 	const struct cif_output_fmt *tools_out_fmt;
745*4882a593Smuzhiyun 	struct rkcif_buffer *curr_buf;
746*4882a593Smuzhiyun 	struct work_struct work;
747*4882a593Smuzhiyun 	enum rkcif_state state;
748*4882a593Smuzhiyun 	int frame_phase;
749*4882a593Smuzhiyun 	unsigned int frame_idx;
750*4882a593Smuzhiyun 	bool stopping;
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun static inline
to_rkcif_tools_vdev(struct rkcif_vdev_node * vnode)754*4882a593Smuzhiyun struct rkcif_tools_vdev *to_rkcif_tools_vdev(struct rkcif_vdev_node *vnode)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun 	return container_of(vnode, struct rkcif_tools_vdev, vnode);
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun void rkcif_init_tools_vdev(struct rkcif_device *cif_dev, u32 ch);
760*4882a593Smuzhiyun int rkcif_register_tools_vdevs(struct rkcif_device *cif_dev,
761*4882a593Smuzhiyun 				int stream_num,
762*4882a593Smuzhiyun 				bool is_multi_input);
763*4882a593Smuzhiyun void rkcif_unregister_tools_vdevs(struct rkcif_device *cif_dev,
764*4882a593Smuzhiyun 				   int stream_num);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun enum rkcif_err_state {
767*4882a593Smuzhiyun 	RKCIF_ERR_ID0_NOT_BUF = 0x1,
768*4882a593Smuzhiyun 	RKCIF_ERR_ID1_NOT_BUF = 0x2,
769*4882a593Smuzhiyun 	RKCIF_ERR_ID2_NOT_BUF = 0x4,
770*4882a593Smuzhiyun 	RKCIF_ERR_ID3_NOT_BUF = 0x8,
771*4882a593Smuzhiyun 	RKCIF_ERR_ID0_TRIG_SIMULT = 0x10,
772*4882a593Smuzhiyun 	RKCIF_ERR_ID1_TRIG_SIMULT = 0x20,
773*4882a593Smuzhiyun 	RKCIF_ERR_ID2_TRIG_SIMULT = 0x40,
774*4882a593Smuzhiyun 	RKCIF_ERR_ID3_TRIG_SIMULT = 0x80,
775*4882a593Smuzhiyun 	RKCIF_ERR_SIZE = 0x100,
776*4882a593Smuzhiyun 	RKCIF_ERR_OVERFLOW = 0x200,
777*4882a593Smuzhiyun 	RKCIF_ERR_BANDWIDTH_LACK = 0x400,
778*4882a593Smuzhiyun 	RKCIF_ERR_BUS = 0X800,
779*4882a593Smuzhiyun 	RKCIF_ERR_ID0_MULTI_FS = 0x1000,
780*4882a593Smuzhiyun 	RKCIF_ERR_ID1_MULTI_FS = 0x2000,
781*4882a593Smuzhiyun 	RKCIF_ERR_ID2_MULTI_FS = 0x4000,
782*4882a593Smuzhiyun 	RKCIF_ERR_ID3_MULTI_FS = 0x8000,
783*4882a593Smuzhiyun 	RKCIF_ERR_PIXEL = 0x10000,
784*4882a593Smuzhiyun 	RKCIF_ERR_LINE = 0x20000,
785*4882a593Smuzhiyun };
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun struct rkcif_err_state_work {
788*4882a593Smuzhiyun 	struct work_struct	work;
789*4882a593Smuzhiyun 	u64 last_timestamp;
790*4882a593Smuzhiyun 	u32 err_state;
791*4882a593Smuzhiyun 	u32 intstat;
792*4882a593Smuzhiyun 	u32 lastline;
793*4882a593Smuzhiyun 	u32 lastpixel;
794*4882a593Smuzhiyun };
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun /*
797*4882a593Smuzhiyun  * struct rkcif_device - ISP platform device
798*4882a593Smuzhiyun  * @base_addr: base register address
799*4882a593Smuzhiyun  * @active_sensor: sensor in-use, set when streaming on
800*4882a593Smuzhiyun  * @stream: capture video device
801*4882a593Smuzhiyun  */
802*4882a593Smuzhiyun struct rkcif_device {
803*4882a593Smuzhiyun 	struct list_head		list;
804*4882a593Smuzhiyun 	struct device			*dev;
805*4882a593Smuzhiyun 	struct v4l2_device		v4l2_dev;
806*4882a593Smuzhiyun 	struct media_device		media_dev;
807*4882a593Smuzhiyun 	struct v4l2_async_notifier	notifier;
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun 	struct rkcif_sensor_info	sensors[RKCIF_MAX_SENSOR];
810*4882a593Smuzhiyun 	u32				num_sensors;
811*4882a593Smuzhiyun 	struct rkcif_sensor_info	*active_sensor;
812*4882a593Smuzhiyun 	struct rkcif_sensor_info	terminal_sensor;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	struct rkcif_stream		stream[RKCIF_MULTI_STREAMS_NUM];
815*4882a593Smuzhiyun 	struct rkcif_scale_vdev		scale_vdev[RKCIF_MULTI_STREAMS_NUM];
816*4882a593Smuzhiyun 	struct rkcif_tools_vdev		tools_vdev[RKCIF_MAX_TOOLS_CH];
817*4882a593Smuzhiyun 	struct rkcif_pipeline		pipe;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	struct csi_channel_info		channels[RKCIF_MAX_CSI_CHANNEL];
820*4882a593Smuzhiyun 	int				num_channels;
821*4882a593Smuzhiyun 	int				chip_id;
822*4882a593Smuzhiyun 	atomic_t			stream_cnt;
823*4882a593Smuzhiyun 	atomic_t			power_cnt;
824*4882a593Smuzhiyun 	struct mutex			stream_lock; /* lock between streams */
825*4882a593Smuzhiyun 	struct mutex			scale_lock; /* lock between scale dev */
826*4882a593Smuzhiyun 	struct mutex			tools_lock; /* lock between tools dev */
827*4882a593Smuzhiyun 	enum rkcif_workmode		workmode;
828*4882a593Smuzhiyun 	bool				can_be_reset;
829*4882a593Smuzhiyun 	struct rkmodule_hdr_cfg		hdr;
830*4882a593Smuzhiyun 	struct rkcif_buffer		*rdbk_buf[RDBK_MAX];
831*4882a593Smuzhiyun 	struct rkcif_rx_buffer		*rdbk_rx_buf[RDBK_MAX];
832*4882a593Smuzhiyun 	struct rkcif_luma_vdev		luma_vdev;
833*4882a593Smuzhiyun 	struct rkcif_lvds_subdev	lvds_subdev;
834*4882a593Smuzhiyun 	struct rkcif_dvp_sof_subdev	dvp_sof_subdev;
835*4882a593Smuzhiyun 	struct rkcif_hw *hw_dev;
836*4882a593Smuzhiyun 	irqreturn_t (*isr_hdl)(int irq, struct rkcif_device *cif_dev);
837*4882a593Smuzhiyun 	int inf_id;
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	struct sditf_priv		*sditf[RKCIF_MAX_SDITF];
840*4882a593Smuzhiyun 	struct proc_dir_entry		*proc_dir;
841*4882a593Smuzhiyun 	struct rkcif_irq_stats		irq_stats;
842*4882a593Smuzhiyun 	spinlock_t			hdr_lock; /* lock for hdr buf sync */
843*4882a593Smuzhiyun 	spinlock_t			buffree_lock;
844*4882a593Smuzhiyun 	struct rkcif_timer		reset_watchdog_timer;
845*4882a593Smuzhiyun 	struct rkcif_work_struct	reset_work;
846*4882a593Smuzhiyun 	int				id_use_cnt;
847*4882a593Smuzhiyun 	unsigned int			csi_host_idx;
848*4882a593Smuzhiyun 	unsigned int			csi_host_idx_def;
849*4882a593Smuzhiyun 	unsigned int			dvp_sof_in_oneframe;
850*4882a593Smuzhiyun 	unsigned int			wait_line;
851*4882a593Smuzhiyun 	unsigned int			wait_line_bak;
852*4882a593Smuzhiyun 	unsigned int			wait_line_cache;
853*4882a593Smuzhiyun 	struct completion		cmpl_ntf;
854*4882a593Smuzhiyun 	struct csi2_dphy_hw		*dphy_hw;
855*4882a593Smuzhiyun 	phys_addr_t			resmem_pa;
856*4882a593Smuzhiyun 	size_t				resmem_size;
857*4882a593Smuzhiyun 	struct rk_tb_client		tb_client;
858*4882a593Smuzhiyun 	bool				is_start_hdr;
859*4882a593Smuzhiyun 	bool				reset_work_cancel;
860*4882a593Smuzhiyun 	bool				iommu_en;
861*4882a593Smuzhiyun 	bool				is_use_dummybuf;
862*4882a593Smuzhiyun 	bool				is_notifier_isp;
863*4882a593Smuzhiyun 	bool				is_thunderboot;
864*4882a593Smuzhiyun 	bool				is_rdbk_to_online;
865*4882a593Smuzhiyun 	bool				is_support_tools;
866*4882a593Smuzhiyun 	int				rdbk_debug;
867*4882a593Smuzhiyun 	struct rkcif_sync_cfg		sync_cfg;
868*4882a593Smuzhiyun 	int				sditf_cnt;
869*4882a593Smuzhiyun 	u32				early_line;
870*4882a593Smuzhiyun 	int				isp_runtime_max;
871*4882a593Smuzhiyun 	int				sensor_linetime;
872*4882a593Smuzhiyun 	u32				err_state;
873*4882a593Smuzhiyun 	struct rkcif_err_state_work	err_state_work;
874*4882a593Smuzhiyun };
875*4882a593Smuzhiyun 
876*4882a593Smuzhiyun extern struct platform_driver rkcif_plat_drv;
877*4882a593Smuzhiyun void rkcif_set_fps(struct rkcif_stream *stream, struct rkcif_fps *fps);
878*4882a593Smuzhiyun int rkcif_do_start_stream(struct rkcif_stream *stream,
879*4882a593Smuzhiyun 				enum rkcif_stream_mode mode);
880*4882a593Smuzhiyun void rkcif_do_stop_stream(struct rkcif_stream *stream,
881*4882a593Smuzhiyun 				enum rkcif_stream_mode mode);
882*4882a593Smuzhiyun void rkcif_irq_handle_scale(struct rkcif_device *cif_dev,
883*4882a593Smuzhiyun 				  unsigned int intstat_glb);
884*4882a593Smuzhiyun void rkcif_buf_queue(struct vb2_buffer *vb);
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun void rkcif_vb_done_tasklet(struct rkcif_stream *stream, struct rkcif_buffer *buf);
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun int rkcif_scale_start(struct rkcif_scale_vdev *scale_vdev);
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun const struct
891*4882a593Smuzhiyun cif_input_fmt *rkcif_get_input_fmt(struct rkcif_device *dev,
892*4882a593Smuzhiyun 				 struct v4l2_rect *rect,
893*4882a593Smuzhiyun 				 u32 pad_id, struct csi_channel_info *csi_info);
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun void rkcif_write_register(struct rkcif_device *dev,
896*4882a593Smuzhiyun 			  enum cif_reg_index index, u32 val);
897*4882a593Smuzhiyun void rkcif_write_register_or(struct rkcif_device *dev,
898*4882a593Smuzhiyun 			     enum cif_reg_index index, u32 val);
899*4882a593Smuzhiyun void rkcif_write_register_and(struct rkcif_device *dev,
900*4882a593Smuzhiyun 			      enum cif_reg_index index, u32 val);
901*4882a593Smuzhiyun unsigned int rkcif_read_register(struct rkcif_device *dev,
902*4882a593Smuzhiyun 				 enum cif_reg_index index);
903*4882a593Smuzhiyun void rkcif_write_grf_reg(struct rkcif_device *dev,
904*4882a593Smuzhiyun 			 enum cif_reg_index index, u32 val);
905*4882a593Smuzhiyun u32 rkcif_read_grf_reg(struct rkcif_device *dev,
906*4882a593Smuzhiyun 		       enum cif_reg_index index);
907*4882a593Smuzhiyun void rkcif_unregister_stream_vdevs(struct rkcif_device *dev,
908*4882a593Smuzhiyun 				   int stream_num);
909*4882a593Smuzhiyun int rkcif_register_stream_vdevs(struct rkcif_device *dev,
910*4882a593Smuzhiyun 				int stream_num,
911*4882a593Smuzhiyun 				bool is_multi_input);
912*4882a593Smuzhiyun void rkcif_stream_init(struct rkcif_device *dev, u32 id);
913*4882a593Smuzhiyun void rkcif_set_default_fmt(struct rkcif_device *cif_dev);
914*4882a593Smuzhiyun void rkcif_irq_oneframe(struct rkcif_device *cif_dev);
915*4882a593Smuzhiyun void rkcif_irq_pingpong(struct rkcif_device *cif_dev);
916*4882a593Smuzhiyun void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev);
917*4882a593Smuzhiyun unsigned int rkcif_irq_global(struct rkcif_device *cif_dev);
918*4882a593Smuzhiyun void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb);
919*4882a593Smuzhiyun int rkcif_register_lvds_subdev(struct rkcif_device *dev);
920*4882a593Smuzhiyun void rkcif_unregister_lvds_subdev(struct rkcif_device *dev);
921*4882a593Smuzhiyun int rkcif_register_dvp_sof_subdev(struct rkcif_device *dev);
922*4882a593Smuzhiyun void rkcif_unregister_dvp_sof_subdev(struct rkcif_device *dev);
923*4882a593Smuzhiyun void rkcif_irq_lite_lvds(struct rkcif_device *cif_dev);
924*4882a593Smuzhiyun int rkcif_plat_init(struct rkcif_device *cif_dev, struct device_node *node, int inf_id);
925*4882a593Smuzhiyun int rkcif_plat_uninit(struct rkcif_device *cif_dev);
926*4882a593Smuzhiyun int rkcif_attach_hw(struct rkcif_device *cif_dev);
927*4882a593Smuzhiyun int rkcif_update_sensor_info(struct rkcif_stream *stream);
928*4882a593Smuzhiyun int rkcif_reset_notifier(struct notifier_block *nb, unsigned long action, void *data);
929*4882a593Smuzhiyun void rkcif_reset_watchdog_timer_handler(struct timer_list *t);
930*4882a593Smuzhiyun void rkcif_config_dvp_clk_sampling_edge(struct rkcif_device *dev,
931*4882a593Smuzhiyun 					enum rkcif_clk_edge edge);
932*4882a593Smuzhiyun void rkcif_enable_dvp_clk_dual_edge(struct rkcif_device *dev, bool on);
933*4882a593Smuzhiyun void rkcif_reset_work(struct work_struct *work);
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
936*4882a593Smuzhiyun 			    struct vb2_v4l2_buffer *vb_done);
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num);
939*4882a593Smuzhiyun void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num);
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun int rkcif_set_fmt(struct rkcif_stream *stream,
942*4882a593Smuzhiyun 		       struct v4l2_pix_format_mplane *pixm,
943*4882a593Smuzhiyun 		       bool try);
944*4882a593Smuzhiyun void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable);
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun void rkcif_do_soft_reset(struct rkcif_device *dev);
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode);
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun void rkcif_config_dvp_pin(struct rkcif_device *dev, bool on);
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev);
953*4882a593Smuzhiyun s32 rkcif_get_sensor_vblank(struct rkcif_device *dev);
954*4882a593Smuzhiyun int rkcif_get_linetime(struct rkcif_stream *stream);
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun void rkcif_assign_check_buffer_update_toisp(struct rkcif_stream *stream);
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun struct rkcif_rx_buffer *to_cif_rx_buf(struct rkisp_rx_buf *dbufs);
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun int rkcif_clr_unready_dev(void);
961*4882a593Smuzhiyun 
962*4882a593Smuzhiyun const struct
963*4882a593Smuzhiyun cif_output_fmt *rkcif_find_output_fmt(struct rkcif_stream *stream, u32 pixelfmt);
964*4882a593Smuzhiyun /* Rockit */
965*4882a593Smuzhiyun int rkcif_rockit_buf_done(struct rkcif_stream *stream, struct rkcif_buffer *buf);
966*4882a593Smuzhiyun void rkcif_rockit_dev_init(struct rkcif_device *dev);
967*4882a593Smuzhiyun void rkcif_rockit_dev_deinit(void);
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun void rkcif_err_print_work(struct work_struct *work);
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun #endif
972