xref: /OK3568_Linux_fs/kernel/drivers/media/platform/qcom/venus/firmware.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2017 Linaro Ltd.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/device.h>
7*4882a593Smuzhiyun #include <linux/firmware.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/iommu.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/qcom_scm.h>
16*4882a593Smuzhiyun #include <linux/sizes.h>
17*4882a593Smuzhiyun #include <linux/soc/qcom/mdt_loader.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "core.h"
20*4882a593Smuzhiyun #include "firmware.h"
21*4882a593Smuzhiyun #include "hfi_venus_io.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define VENUS_PAS_ID			9
24*4882a593Smuzhiyun #define VENUS_FW_MEM_SIZE		(6 * SZ_1M)
25*4882a593Smuzhiyun #define VENUS_FW_START_ADDR		0x0
26*4882a593Smuzhiyun 
venus_reset_cpu(struct venus_core * core)27*4882a593Smuzhiyun static void venus_reset_cpu(struct venus_core *core)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	u32 fw_size = core->fw.mapped_mem_size;
30*4882a593Smuzhiyun 	void __iomem *base = core->base;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	writel(0, base + WRAPPER_FW_START_ADDR);
33*4882a593Smuzhiyun 	writel(fw_size, base + WRAPPER_FW_END_ADDR);
34*4882a593Smuzhiyun 	writel(0, base + WRAPPER_CPA_START_ADDR);
35*4882a593Smuzhiyun 	writel(fw_size, base + WRAPPER_CPA_END_ADDR);
36*4882a593Smuzhiyun 	writel(fw_size, base + WRAPPER_NONPIX_START_ADDR);
37*4882a593Smuzhiyun 	writel(fw_size, base + WRAPPER_NONPIX_END_ADDR);
38*4882a593Smuzhiyun 	writel(0x0, base + WRAPPER_CPU_CGC_DIS);
39*4882a593Smuzhiyun 	writel(0x0, base + WRAPPER_CPU_CLOCK_CONFIG);
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	/* Bring ARM9 out of reset */
42*4882a593Smuzhiyun 	writel(0, base + WRAPPER_A9SS_SW_RESET);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
venus_set_hw_state(struct venus_core * core,bool resume)45*4882a593Smuzhiyun int venus_set_hw_state(struct venus_core *core, bool resume)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	int ret;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	if (core->use_tz) {
50*4882a593Smuzhiyun 		ret = qcom_scm_set_remote_state(resume, 0);
51*4882a593Smuzhiyun 		if (resume && ret == -EINVAL)
52*4882a593Smuzhiyun 			ret = 0;
53*4882a593Smuzhiyun 		return ret;
54*4882a593Smuzhiyun 	}
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	if (resume)
57*4882a593Smuzhiyun 		venus_reset_cpu(core);
58*4882a593Smuzhiyun 	else
59*4882a593Smuzhiyun 		writel(1, core->base + WRAPPER_A9SS_SW_RESET);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
venus_load_fw(struct venus_core * core,const char * fwname,phys_addr_t * mem_phys,size_t * mem_size)64*4882a593Smuzhiyun static int venus_load_fw(struct venus_core *core, const char *fwname,
65*4882a593Smuzhiyun 			 phys_addr_t *mem_phys, size_t *mem_size)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	const struct firmware *mdt;
68*4882a593Smuzhiyun 	struct device_node *node;
69*4882a593Smuzhiyun 	struct device *dev;
70*4882a593Smuzhiyun 	struct resource r;
71*4882a593Smuzhiyun 	ssize_t fw_size;
72*4882a593Smuzhiyun 	void *mem_va;
73*4882a593Smuzhiyun 	int ret;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	*mem_phys = 0;
76*4882a593Smuzhiyun 	*mem_size = 0;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	dev = core->dev;
79*4882a593Smuzhiyun 	node = of_parse_phandle(dev->of_node, "memory-region", 0);
80*4882a593Smuzhiyun 	if (!node) {
81*4882a593Smuzhiyun 		dev_err(dev, "no memory-region specified\n");
82*4882a593Smuzhiyun 		return -EINVAL;
83*4882a593Smuzhiyun 	}
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	ret = of_address_to_resource(node, 0, &r);
86*4882a593Smuzhiyun 	if (ret)
87*4882a593Smuzhiyun 		goto err_put_node;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	ret = request_firmware(&mdt, fwname, dev);
90*4882a593Smuzhiyun 	if (ret < 0)
91*4882a593Smuzhiyun 		goto err_put_node;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	fw_size = qcom_mdt_get_size(mdt);
94*4882a593Smuzhiyun 	if (fw_size < 0) {
95*4882a593Smuzhiyun 		ret = fw_size;
96*4882a593Smuzhiyun 		goto err_release_fw;
97*4882a593Smuzhiyun 	}
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	*mem_phys = r.start;
100*4882a593Smuzhiyun 	*mem_size = resource_size(&r);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) {
103*4882a593Smuzhiyun 		ret = -EINVAL;
104*4882a593Smuzhiyun 		goto err_release_fw;
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	mem_va = memremap(r.start, *mem_size, MEMREMAP_WC);
108*4882a593Smuzhiyun 	if (!mem_va) {
109*4882a593Smuzhiyun 		dev_err(dev, "unable to map memory region: %pR\n", &r);
110*4882a593Smuzhiyun 		ret = -ENOMEM;
111*4882a593Smuzhiyun 		goto err_release_fw;
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	if (core->use_tz)
115*4882a593Smuzhiyun 		ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID,
116*4882a593Smuzhiyun 				    mem_va, *mem_phys, *mem_size, NULL);
117*4882a593Smuzhiyun 	else
118*4882a593Smuzhiyun 		ret = qcom_mdt_load_no_init(dev, mdt, fwname, VENUS_PAS_ID,
119*4882a593Smuzhiyun 					    mem_va, *mem_phys, *mem_size, NULL);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	memunmap(mem_va);
122*4882a593Smuzhiyun err_release_fw:
123*4882a593Smuzhiyun 	release_firmware(mdt);
124*4882a593Smuzhiyun err_put_node:
125*4882a593Smuzhiyun 	of_node_put(node);
126*4882a593Smuzhiyun 	return ret;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
venus_boot_no_tz(struct venus_core * core,phys_addr_t mem_phys,size_t mem_size)129*4882a593Smuzhiyun static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys,
130*4882a593Smuzhiyun 			    size_t mem_size)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	struct iommu_domain *iommu;
133*4882a593Smuzhiyun 	struct device *dev;
134*4882a593Smuzhiyun 	int ret;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	dev = core->fw.dev;
137*4882a593Smuzhiyun 	if (!dev)
138*4882a593Smuzhiyun 		return -EPROBE_DEFER;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	iommu = core->fw.iommu_domain;
141*4882a593Smuzhiyun 	core->fw.mapped_mem_size = mem_size;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size,
144*4882a593Smuzhiyun 			IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV);
145*4882a593Smuzhiyun 	if (ret) {
146*4882a593Smuzhiyun 		dev_err(dev, "could not map video firmware region\n");
147*4882a593Smuzhiyun 		return ret;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	venus_reset_cpu(core);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return 0;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
venus_shutdown_no_tz(struct venus_core * core)155*4882a593Smuzhiyun static int venus_shutdown_no_tz(struct venus_core *core)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	const size_t mapped = core->fw.mapped_mem_size;
158*4882a593Smuzhiyun 	struct iommu_domain *iommu;
159*4882a593Smuzhiyun 	size_t unmapped;
160*4882a593Smuzhiyun 	u32 reg;
161*4882a593Smuzhiyun 	struct device *dev = core->fw.dev;
162*4882a593Smuzhiyun 	void __iomem *base = core->base;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* Assert the reset to ARM9 */
165*4882a593Smuzhiyun 	reg = readl_relaxed(base + WRAPPER_A9SS_SW_RESET);
166*4882a593Smuzhiyun 	reg |= WRAPPER_A9SS_SW_RESET_BIT;
167*4882a593Smuzhiyun 	writel_relaxed(reg, base + WRAPPER_A9SS_SW_RESET);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	/* Make sure reset is asserted before the mapping is removed */
170*4882a593Smuzhiyun 	mb();
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	iommu = core->fw.iommu_domain;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped);
175*4882a593Smuzhiyun 	if (unmapped != mapped)
176*4882a593Smuzhiyun 		dev_err(dev, "failed to unmap firmware\n");
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
venus_boot(struct venus_core * core)181*4882a593Smuzhiyun int venus_boot(struct venus_core *core)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct device *dev = core->dev;
184*4882a593Smuzhiyun 	const struct venus_resources *res = core->res;
185*4882a593Smuzhiyun 	phys_addr_t mem_phys;
186*4882a593Smuzhiyun 	size_t mem_size;
187*4882a593Smuzhiyun 	int ret;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) ||
190*4882a593Smuzhiyun 	    (core->use_tz && !qcom_scm_is_available()))
191*4882a593Smuzhiyun 		return -EPROBE_DEFER;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	ret = venus_load_fw(core, core->res->fwname, &mem_phys, &mem_size);
194*4882a593Smuzhiyun 	if (ret) {
195*4882a593Smuzhiyun 		dev_err(dev, "fail to load video firmware\n");
196*4882a593Smuzhiyun 		return -EINVAL;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	if (core->use_tz)
200*4882a593Smuzhiyun 		ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID);
201*4882a593Smuzhiyun 	else
202*4882a593Smuzhiyun 		ret = venus_boot_no_tz(core, mem_phys, mem_size);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	if (ret)
205*4882a593Smuzhiyun 		return ret;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	if (core->use_tz && res->cp_size) {
208*4882a593Smuzhiyun 		ret = qcom_scm_mem_protect_video_var(res->cp_start,
209*4882a593Smuzhiyun 						     res->cp_size,
210*4882a593Smuzhiyun 						     res->cp_nonpixel_start,
211*4882a593Smuzhiyun 						     res->cp_nonpixel_size);
212*4882a593Smuzhiyun 		if (ret) {
213*4882a593Smuzhiyun 			qcom_scm_pas_shutdown(VENUS_PAS_ID);
214*4882a593Smuzhiyun 			dev_err(dev, "set virtual address ranges fail (%d)\n",
215*4882a593Smuzhiyun 				ret);
216*4882a593Smuzhiyun 			return ret;
217*4882a593Smuzhiyun 		}
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
venus_shutdown(struct venus_core * core)223*4882a593Smuzhiyun int venus_shutdown(struct venus_core *core)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun 	int ret;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	if (core->use_tz)
228*4882a593Smuzhiyun 		ret = qcom_scm_pas_shutdown(VENUS_PAS_ID);
229*4882a593Smuzhiyun 	else
230*4882a593Smuzhiyun 		ret = venus_shutdown_no_tz(core);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
venus_firmware_init(struct venus_core * core)235*4882a593Smuzhiyun int venus_firmware_init(struct venus_core *core)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	struct platform_device_info info;
238*4882a593Smuzhiyun 	struct iommu_domain *iommu_dom;
239*4882a593Smuzhiyun 	struct platform_device *pdev;
240*4882a593Smuzhiyun 	struct device_node *np;
241*4882a593Smuzhiyun 	int ret;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	np = of_get_child_by_name(core->dev->of_node, "video-firmware");
244*4882a593Smuzhiyun 	if (!np) {
245*4882a593Smuzhiyun 		core->use_tz = true;
246*4882a593Smuzhiyun 		return 0;
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	memset(&info, 0, sizeof(info));
250*4882a593Smuzhiyun 	info.fwnode = &np->fwnode;
251*4882a593Smuzhiyun 	info.parent = core->dev;
252*4882a593Smuzhiyun 	info.name = np->name;
253*4882a593Smuzhiyun 	info.dma_mask = DMA_BIT_MASK(32);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	pdev = platform_device_register_full(&info);
256*4882a593Smuzhiyun 	if (IS_ERR(pdev)) {
257*4882a593Smuzhiyun 		of_node_put(np);
258*4882a593Smuzhiyun 		return PTR_ERR(pdev);
259*4882a593Smuzhiyun 	}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	pdev->dev.of_node = np;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	ret = of_dma_configure(&pdev->dev, np, true);
264*4882a593Smuzhiyun 	if (ret) {
265*4882a593Smuzhiyun 		dev_err(core->dev, "dma configure fail\n");
266*4882a593Smuzhiyun 		goto err_unregister;
267*4882a593Smuzhiyun 	}
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	core->fw.dev = &pdev->dev;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	iommu_dom = iommu_domain_alloc(&platform_bus_type);
272*4882a593Smuzhiyun 	if (!iommu_dom) {
273*4882a593Smuzhiyun 		dev_err(core->fw.dev, "Failed to allocate iommu domain\n");
274*4882a593Smuzhiyun 		ret = -ENOMEM;
275*4882a593Smuzhiyun 		goto err_unregister;
276*4882a593Smuzhiyun 	}
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	ret = iommu_attach_device(iommu_dom, core->fw.dev);
279*4882a593Smuzhiyun 	if (ret) {
280*4882a593Smuzhiyun 		dev_err(core->fw.dev, "could not attach device\n");
281*4882a593Smuzhiyun 		goto err_iommu_free;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	core->fw.iommu_domain = iommu_dom;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	of_node_put(np);
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	return 0;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun err_iommu_free:
291*4882a593Smuzhiyun 	iommu_domain_free(iommu_dom);
292*4882a593Smuzhiyun err_unregister:
293*4882a593Smuzhiyun 	platform_device_unregister(pdev);
294*4882a593Smuzhiyun 	of_node_put(np);
295*4882a593Smuzhiyun 	return ret;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
venus_firmware_deinit(struct venus_core * core)298*4882a593Smuzhiyun void venus_firmware_deinit(struct venus_core *core)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	struct iommu_domain *iommu;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	if (!core->fw.dev)
303*4882a593Smuzhiyun 		return;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	iommu = core->fw.iommu_domain;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	iommu_detach_device(iommu, core->fw.dev);
308*4882a593Smuzhiyun 	iommu_domain_free(iommu);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	platform_device_unregister(to_platform_device(core->fw.dev));
311*4882a593Smuzhiyun }
312