1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * camss-vfe.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8*4882a593Smuzhiyun * Copyright (C) 2015-2018 Linaro Ltd. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef QC_MSM_CAMSS_VFE_H 11*4882a593Smuzhiyun #define QC_MSM_CAMSS_VFE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/clk.h> 14*4882a593Smuzhiyun #include <linux/spinlock_types.h> 15*4882a593Smuzhiyun #include <media/media-entity.h> 16*4882a593Smuzhiyun #include <media/v4l2-device.h> 17*4882a593Smuzhiyun #include <media/v4l2-subdev.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include "camss-video.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MSM_VFE_PAD_SINK 0 22*4882a593Smuzhiyun #define MSM_VFE_PAD_SRC 1 23*4882a593Smuzhiyun #define MSM_VFE_PADS_NUM 2 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MSM_VFE_LINE_NUM 4 26*4882a593Smuzhiyun #define MSM_VFE_IMAGE_MASTERS_NUM 7 27*4882a593Smuzhiyun #define MSM_VFE_COMPOSITE_IRQ_NUM 4 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum vfe_output_state { 30*4882a593Smuzhiyun VFE_OUTPUT_OFF, 31*4882a593Smuzhiyun VFE_OUTPUT_RESERVED, 32*4882a593Smuzhiyun VFE_OUTPUT_SINGLE, 33*4882a593Smuzhiyun VFE_OUTPUT_CONTINUOUS, 34*4882a593Smuzhiyun VFE_OUTPUT_IDLE, 35*4882a593Smuzhiyun VFE_OUTPUT_STOPPING 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum vfe_line_id { 39*4882a593Smuzhiyun VFE_LINE_NONE = -1, 40*4882a593Smuzhiyun VFE_LINE_RDI0 = 0, 41*4882a593Smuzhiyun VFE_LINE_RDI1 = 1, 42*4882a593Smuzhiyun VFE_LINE_RDI2 = 2, 43*4882a593Smuzhiyun VFE_LINE_PIX = 3 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct vfe_output { 47*4882a593Smuzhiyun u8 wm_num; 48*4882a593Smuzhiyun u8 wm_idx[3]; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun int active_buf; 51*4882a593Smuzhiyun struct camss_buffer *buf[2]; 52*4882a593Smuzhiyun struct camss_buffer *last_buffer; 53*4882a593Smuzhiyun struct list_head pending_bufs; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun unsigned int drop_update_idx; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum vfe_output_state state; 58*4882a593Smuzhiyun unsigned int sequence; 59*4882a593Smuzhiyun int wait_sof; 60*4882a593Smuzhiyun int wait_reg_update; 61*4882a593Smuzhiyun struct completion sof; 62*4882a593Smuzhiyun struct completion reg_update; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct vfe_line { 66*4882a593Smuzhiyun enum vfe_line_id id; 67*4882a593Smuzhiyun struct v4l2_subdev subdev; 68*4882a593Smuzhiyun struct media_pad pads[MSM_VFE_PADS_NUM]; 69*4882a593Smuzhiyun struct v4l2_mbus_framefmt fmt[MSM_VFE_PADS_NUM]; 70*4882a593Smuzhiyun struct v4l2_rect compose; 71*4882a593Smuzhiyun struct v4l2_rect crop; 72*4882a593Smuzhiyun struct camss_video video_out; 73*4882a593Smuzhiyun struct vfe_output output; 74*4882a593Smuzhiyun const struct vfe_format *formats; 75*4882a593Smuzhiyun unsigned int nformats; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct vfe_device; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct vfe_hw_ops { 81*4882a593Smuzhiyun void (*hw_version_read)(struct vfe_device *vfe, struct device *dev); 82*4882a593Smuzhiyun u16 (*get_ub_size)(u8 vfe_id); 83*4882a593Smuzhiyun void (*global_reset)(struct vfe_device *vfe); 84*4882a593Smuzhiyun void (*halt_request)(struct vfe_device *vfe); 85*4882a593Smuzhiyun void (*halt_clear)(struct vfe_device *vfe); 86*4882a593Smuzhiyun void (*wm_enable)(struct vfe_device *vfe, u8 wm, u8 enable); 87*4882a593Smuzhiyun void (*wm_frame_based)(struct vfe_device *vfe, u8 wm, u8 enable); 88*4882a593Smuzhiyun void (*wm_line_based)(struct vfe_device *vfe, u32 wm, 89*4882a593Smuzhiyun struct v4l2_pix_format_mplane *pix, 90*4882a593Smuzhiyun u8 plane, u32 enable); 91*4882a593Smuzhiyun void (*wm_set_framedrop_period)(struct vfe_device *vfe, u8 wm, u8 per); 92*4882a593Smuzhiyun void (*wm_set_framedrop_pattern)(struct vfe_device *vfe, u8 wm, 93*4882a593Smuzhiyun u32 pattern); 94*4882a593Smuzhiyun void (*wm_set_ub_cfg)(struct vfe_device *vfe, u8 wm, u16 offset, 95*4882a593Smuzhiyun u16 depth); 96*4882a593Smuzhiyun void (*bus_reload_wm)(struct vfe_device *vfe, u8 wm); 97*4882a593Smuzhiyun void (*wm_set_ping_addr)(struct vfe_device *vfe, u8 wm, u32 addr); 98*4882a593Smuzhiyun void (*wm_set_pong_addr)(struct vfe_device *vfe, u8 wm, u32 addr); 99*4882a593Smuzhiyun int (*wm_get_ping_pong_status)(struct vfe_device *vfe, u8 wm); 100*4882a593Smuzhiyun void (*bus_enable_wr_if)(struct vfe_device *vfe, u8 enable); 101*4882a593Smuzhiyun void (*bus_connect_wm_to_rdi)(struct vfe_device *vfe, u8 wm, 102*4882a593Smuzhiyun enum vfe_line_id id); 103*4882a593Smuzhiyun void (*wm_set_subsample)(struct vfe_device *vfe, u8 wm); 104*4882a593Smuzhiyun void (*bus_disconnect_wm_from_rdi)(struct vfe_device *vfe, u8 wm, 105*4882a593Smuzhiyun enum vfe_line_id id); 106*4882a593Smuzhiyun void (*set_xbar_cfg)(struct vfe_device *vfe, struct vfe_output *output, 107*4882a593Smuzhiyun u8 enable); 108*4882a593Smuzhiyun void (*set_rdi_cid)(struct vfe_device *vfe, enum vfe_line_id id, 109*4882a593Smuzhiyun u8 cid); 110*4882a593Smuzhiyun void (*set_realign_cfg)(struct vfe_device *vfe, struct vfe_line *line, 111*4882a593Smuzhiyun u8 enable); 112*4882a593Smuzhiyun void (*reg_update)(struct vfe_device *vfe, enum vfe_line_id line_id); 113*4882a593Smuzhiyun void (*reg_update_clear)(struct vfe_device *vfe, 114*4882a593Smuzhiyun enum vfe_line_id line_id); 115*4882a593Smuzhiyun void (*enable_irq_wm_line)(struct vfe_device *vfe, u8 wm, 116*4882a593Smuzhiyun enum vfe_line_id line_id, u8 enable); 117*4882a593Smuzhiyun void (*enable_irq_pix_line)(struct vfe_device *vfe, u8 comp, 118*4882a593Smuzhiyun enum vfe_line_id line_id, u8 enable); 119*4882a593Smuzhiyun void (*enable_irq_common)(struct vfe_device *vfe); 120*4882a593Smuzhiyun void (*set_demux_cfg)(struct vfe_device *vfe, struct vfe_line *line); 121*4882a593Smuzhiyun void (*set_scale_cfg)(struct vfe_device *vfe, struct vfe_line *line); 122*4882a593Smuzhiyun void (*set_crop_cfg)(struct vfe_device *vfe, struct vfe_line *line); 123*4882a593Smuzhiyun void (*set_clamp_cfg)(struct vfe_device *vfe); 124*4882a593Smuzhiyun void (*set_qos)(struct vfe_device *vfe); 125*4882a593Smuzhiyun void (*set_ds)(struct vfe_device *vfe); 126*4882a593Smuzhiyun void (*set_cgc_override)(struct vfe_device *vfe, u8 wm, u8 enable); 127*4882a593Smuzhiyun void (*set_camif_cfg)(struct vfe_device *vfe, struct vfe_line *line); 128*4882a593Smuzhiyun void (*set_camif_cmd)(struct vfe_device *vfe, u8 enable); 129*4882a593Smuzhiyun void (*set_module_cfg)(struct vfe_device *vfe, u8 enable); 130*4882a593Smuzhiyun int (*camif_wait_for_stop)(struct vfe_device *vfe, struct device *dev); 131*4882a593Smuzhiyun void (*isr_read)(struct vfe_device *vfe, u32 *value0, u32 *value1); 132*4882a593Smuzhiyun void (*violation_read)(struct vfe_device *vfe); 133*4882a593Smuzhiyun irqreturn_t (*isr)(int irq, void *dev); 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun struct vfe_isr_ops { 137*4882a593Smuzhiyun void (*reset_ack)(struct vfe_device *vfe); 138*4882a593Smuzhiyun void (*halt_ack)(struct vfe_device *vfe); 139*4882a593Smuzhiyun void (*reg_update)(struct vfe_device *vfe, enum vfe_line_id line_id); 140*4882a593Smuzhiyun void (*sof)(struct vfe_device *vfe, enum vfe_line_id line_id); 141*4882a593Smuzhiyun void (*comp_done)(struct vfe_device *vfe, u8 comp); 142*4882a593Smuzhiyun void (*wm_done)(struct vfe_device *vfe, u8 wm); 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct vfe_device { 146*4882a593Smuzhiyun struct camss *camss; 147*4882a593Smuzhiyun u8 id; 148*4882a593Smuzhiyun void __iomem *base; 149*4882a593Smuzhiyun u32 irq; 150*4882a593Smuzhiyun char irq_name[30]; 151*4882a593Smuzhiyun struct camss_clock *clock; 152*4882a593Smuzhiyun int nclocks; 153*4882a593Smuzhiyun struct completion reset_complete; 154*4882a593Smuzhiyun struct completion halt_complete; 155*4882a593Smuzhiyun struct mutex power_lock; 156*4882a593Smuzhiyun int power_count; 157*4882a593Smuzhiyun struct mutex stream_lock; 158*4882a593Smuzhiyun int stream_count; 159*4882a593Smuzhiyun spinlock_t output_lock; 160*4882a593Smuzhiyun enum vfe_line_id wm_output_map[MSM_VFE_IMAGE_MASTERS_NUM]; 161*4882a593Smuzhiyun struct vfe_line line[MSM_VFE_LINE_NUM]; 162*4882a593Smuzhiyun u32 reg_update; 163*4882a593Smuzhiyun u8 was_streaming; 164*4882a593Smuzhiyun const struct vfe_hw_ops *ops; 165*4882a593Smuzhiyun struct vfe_isr_ops isr_ops; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun struct resources; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, 171*4882a593Smuzhiyun const struct resources *res, u8 id); 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun int msm_vfe_register_entities(struct vfe_device *vfe, 174*4882a593Smuzhiyun struct v4l2_device *v4l2_dev); 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun void msm_vfe_unregister_entities(struct vfe_device *vfe); 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun void msm_vfe_get_vfe_id(struct media_entity *entity, u8 *id); 179*4882a593Smuzhiyun void msm_vfe_get_vfe_line_id(struct media_entity *entity, enum vfe_line_id *id); 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun extern const struct vfe_hw_ops vfe_ops_4_1; 182*4882a593Smuzhiyun extern const struct vfe_hw_ops vfe_ops_4_7; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #endif /* QC_MSM_CAMSS_VFE_H */ 185