1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * camss-csiphy.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Qualcomm MSM Camera Subsystem - CSIPHY Module 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8*4882a593Smuzhiyun * Copyright (C) 2016-2018 Linaro Ltd. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef QC_MSM_CAMSS_CSIPHY_H 11*4882a593Smuzhiyun #define QC_MSM_CAMSS_CSIPHY_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/clk.h> 14*4882a593Smuzhiyun #include <linux/interrupt.h> 15*4882a593Smuzhiyun #include <media/media-entity.h> 16*4882a593Smuzhiyun #include <media/v4l2-device.h> 17*4882a593Smuzhiyun #include <media/v4l2-mediabus.h> 18*4882a593Smuzhiyun #include <media/v4l2-subdev.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MSM_CSIPHY_PAD_SINK 0 21*4882a593Smuzhiyun #define MSM_CSIPHY_PAD_SRC 1 22*4882a593Smuzhiyun #define MSM_CSIPHY_PADS_NUM 2 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct csiphy_lane { 25*4882a593Smuzhiyun u8 pos; 26*4882a593Smuzhiyun u8 pol; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct csiphy_lanes_cfg { 30*4882a593Smuzhiyun int num_data; 31*4882a593Smuzhiyun struct csiphy_lane *data; 32*4882a593Smuzhiyun struct csiphy_lane clk; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct csiphy_csi2_cfg { 36*4882a593Smuzhiyun struct csiphy_lanes_cfg lane_cfg; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct csiphy_config { 40*4882a593Smuzhiyun u8 combo_mode; 41*4882a593Smuzhiyun u8 csid_id; 42*4882a593Smuzhiyun struct csiphy_csi2_cfg *csi2; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct csiphy_device; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct csiphy_hw_ops { 48*4882a593Smuzhiyun void (*hw_version_read)(struct csiphy_device *csiphy, 49*4882a593Smuzhiyun struct device *dev); 50*4882a593Smuzhiyun void (*reset)(struct csiphy_device *csiphy); 51*4882a593Smuzhiyun void (*lanes_enable)(struct csiphy_device *csiphy, 52*4882a593Smuzhiyun struct csiphy_config *cfg, 53*4882a593Smuzhiyun u32 pixel_clock, u8 bpp, u8 lane_mask); 54*4882a593Smuzhiyun void (*lanes_disable)(struct csiphy_device *csiphy, 55*4882a593Smuzhiyun struct csiphy_config *cfg); 56*4882a593Smuzhiyun irqreturn_t (*isr)(int irq, void *dev); 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct csiphy_device { 60*4882a593Smuzhiyun struct camss *camss; 61*4882a593Smuzhiyun u8 id; 62*4882a593Smuzhiyun struct v4l2_subdev subdev; 63*4882a593Smuzhiyun struct media_pad pads[MSM_CSIPHY_PADS_NUM]; 64*4882a593Smuzhiyun void __iomem *base; 65*4882a593Smuzhiyun void __iomem *base_clk_mux; 66*4882a593Smuzhiyun u32 irq; 67*4882a593Smuzhiyun char irq_name[30]; 68*4882a593Smuzhiyun struct camss_clock *clock; 69*4882a593Smuzhiyun int nclocks; 70*4882a593Smuzhiyun u32 timer_clk_rate; 71*4882a593Smuzhiyun struct csiphy_config cfg; 72*4882a593Smuzhiyun struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM]; 73*4882a593Smuzhiyun const struct csiphy_hw_ops *ops; 74*4882a593Smuzhiyun const struct csiphy_format *formats; 75*4882a593Smuzhiyun unsigned int nformats; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct resources; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun int msm_csiphy_subdev_init(struct camss *camss, 81*4882a593Smuzhiyun struct csiphy_device *csiphy, 82*4882a593Smuzhiyun const struct resources *res, u8 id); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun int msm_csiphy_register_entity(struct csiphy_device *csiphy, 85*4882a593Smuzhiyun struct v4l2_device *v4l2_dev); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; 90*4882a593Smuzhiyun extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* QC_MSM_CAMSS_CSIPHY_H */ 93