1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * camss-csiphy.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Qualcomm MSM Camera Subsystem - CSIPHY Module
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8*4882a593Smuzhiyun * Copyright (C) 2016-2018 Linaro Ltd.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <media/media-entity.h>
19*4882a593Smuzhiyun #include <media/v4l2-device.h>
20*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "camss-csiphy.h"
23*4882a593Smuzhiyun #include "camss.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MSM_CSIPHY_NAME "msm_csiphy"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct csiphy_format {
28*4882a593Smuzhiyun u32 code;
29*4882a593Smuzhiyun u8 bpp;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct csiphy_format csiphy_formats_8x16[] = {
33*4882a593Smuzhiyun { MEDIA_BUS_FMT_UYVY8_2X8, 8 },
34*4882a593Smuzhiyun { MEDIA_BUS_FMT_VYUY8_2X8, 8 },
35*4882a593Smuzhiyun { MEDIA_BUS_FMT_YUYV8_2X8, 8 },
36*4882a593Smuzhiyun { MEDIA_BUS_FMT_YVYU8_2X8, 8 },
37*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR8_1X8, 8 },
38*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG8_1X8, 8 },
39*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG8_1X8, 8 },
40*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB8_1X8, 8 },
41*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR10_1X10, 10 },
42*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
43*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
44*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
45*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR12_1X12, 12 },
46*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG12_1X12, 12 },
47*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG12_1X12, 12 },
48*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
49*4882a593Smuzhiyun { MEDIA_BUS_FMT_Y10_1X10, 10 },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct csiphy_format csiphy_formats_8x96[] = {
53*4882a593Smuzhiyun { MEDIA_BUS_FMT_UYVY8_2X8, 8 },
54*4882a593Smuzhiyun { MEDIA_BUS_FMT_VYUY8_2X8, 8 },
55*4882a593Smuzhiyun { MEDIA_BUS_FMT_YUYV8_2X8, 8 },
56*4882a593Smuzhiyun { MEDIA_BUS_FMT_YVYU8_2X8, 8 },
57*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR8_1X8, 8 },
58*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG8_1X8, 8 },
59*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG8_1X8, 8 },
60*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB8_1X8, 8 },
61*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR10_1X10, 10 },
62*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
63*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
64*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
65*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR12_1X12, 12 },
66*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG12_1X12, 12 },
67*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG12_1X12, 12 },
68*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
69*4882a593Smuzhiyun { MEDIA_BUS_FMT_SBGGR14_1X14, 14 },
70*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGBRG14_1X14, 14 },
71*4882a593Smuzhiyun { MEDIA_BUS_FMT_SGRBG14_1X14, 14 },
72*4882a593Smuzhiyun { MEDIA_BUS_FMT_SRGGB14_1X14, 14 },
73*4882a593Smuzhiyun { MEDIA_BUS_FMT_Y10_1X10, 10 },
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * csiphy_get_bpp - map media bus format to bits per pixel
78*4882a593Smuzhiyun * @formats: supported media bus formats array
79*4882a593Smuzhiyun * @nformats: size of @formats array
80*4882a593Smuzhiyun * @code: media bus format code
81*4882a593Smuzhiyun *
82*4882a593Smuzhiyun * Return number of bits per pixel
83*4882a593Smuzhiyun */
csiphy_get_bpp(const struct csiphy_format * formats,unsigned int nformats,u32 code)84*4882a593Smuzhiyun static u8 csiphy_get_bpp(const struct csiphy_format *formats,
85*4882a593Smuzhiyun unsigned int nformats, u32 code)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun unsigned int i;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun for (i = 0; i < nformats; i++)
90*4882a593Smuzhiyun if (code == formats[i].code)
91*4882a593Smuzhiyun return formats[i].bpp;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun WARN(1, "Unknown format\n");
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return formats[0].bpp;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module
100*4882a593Smuzhiyun * @csiphy: CSIPHY device
101*4882a593Smuzhiyun */
csiphy_set_clock_rates(struct csiphy_device * csiphy)102*4882a593Smuzhiyun static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct device *dev = csiphy->camss->dev;
105*4882a593Smuzhiyun u32 pixel_clock;
106*4882a593Smuzhiyun int i, j;
107*4882a593Smuzhiyun int ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
110*4882a593Smuzhiyun if (ret)
111*4882a593Smuzhiyun pixel_clock = 0;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun for (i = 0; i < csiphy->nclocks; i++) {
114*4882a593Smuzhiyun struct camss_clock *clock = &csiphy->clock[i];
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (!strcmp(clock->name, "csiphy0_timer") ||
117*4882a593Smuzhiyun !strcmp(clock->name, "csiphy1_timer") ||
118*4882a593Smuzhiyun !strcmp(clock->name, "csiphy2_timer")) {
119*4882a593Smuzhiyun u8 bpp = csiphy_get_bpp(csiphy->formats,
120*4882a593Smuzhiyun csiphy->nformats,
121*4882a593Smuzhiyun csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
122*4882a593Smuzhiyun u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
123*4882a593Smuzhiyun u64 min_rate = pixel_clock * bpp / (2 * num_lanes * 4);
124*4882a593Smuzhiyun long round_rate;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun camss_add_clock_margin(&min_rate);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun for (j = 0; j < clock->nfreqs; j++)
129*4882a593Smuzhiyun if (min_rate < clock->freq[j])
130*4882a593Smuzhiyun break;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (j == clock->nfreqs) {
133*4882a593Smuzhiyun dev_err(dev,
134*4882a593Smuzhiyun "Pixel clock is too high for CSIPHY\n");
135*4882a593Smuzhiyun return -EINVAL;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* if sensor pixel clock is not available */
139*4882a593Smuzhiyun /* set highest possible CSIPHY clock rate */
140*4882a593Smuzhiyun if (min_rate == 0)
141*4882a593Smuzhiyun j = clock->nfreqs - 1;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun round_rate = clk_round_rate(clock->clk, clock->freq[j]);
144*4882a593Smuzhiyun if (round_rate < 0) {
145*4882a593Smuzhiyun dev_err(dev, "clk round rate failed: %ld\n",
146*4882a593Smuzhiyun round_rate);
147*4882a593Smuzhiyun return -EINVAL;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun csiphy->timer_clk_rate = round_rate;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate);
153*4882a593Smuzhiyun if (ret < 0) {
154*4882a593Smuzhiyun dev_err(dev, "clk set rate failed: %d\n", ret);
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /*
164*4882a593Smuzhiyun * csiphy_set_power - Power on/off CSIPHY module
165*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
166*4882a593Smuzhiyun * @on: Requested power state
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
169*4882a593Smuzhiyun */
csiphy_set_power(struct v4l2_subdev * sd,int on)170*4882a593Smuzhiyun static int csiphy_set_power(struct v4l2_subdev *sd, int on)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
173*4882a593Smuzhiyun struct device *dev = csiphy->camss->dev;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (on) {
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = pm_runtime_get_sync(dev);
179*4882a593Smuzhiyun if (ret < 0) {
180*4882a593Smuzhiyun pm_runtime_put_sync(dev);
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ret = csiphy_set_clock_rates(csiphy);
185*4882a593Smuzhiyun if (ret < 0) {
186*4882a593Smuzhiyun pm_runtime_put_sync(dev);
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev);
191*4882a593Smuzhiyun if (ret < 0) {
192*4882a593Smuzhiyun pm_runtime_put_sync(dev);
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun enable_irq(csiphy->irq);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun csiphy->ops->reset(csiphy);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun csiphy->ops->hw_version_read(csiphy, dev);
201*4882a593Smuzhiyun } else {
202*4882a593Smuzhiyun disable_irq(csiphy->irq);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun camss_disable_clocks(csiphy->nclocks, csiphy->clock);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun pm_runtime_put_sync(dev);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /*
213*4882a593Smuzhiyun * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter
214*4882a593Smuzhiyun * @lane_cfg - CSI2 lane configuration
215*4882a593Smuzhiyun *
216*4882a593Smuzhiyun * Return lane mask
217*4882a593Smuzhiyun */
csiphy_get_lane_mask(struct csiphy_lanes_cfg * lane_cfg)218*4882a593Smuzhiyun static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun u8 lane_mask;
221*4882a593Smuzhiyun int i;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun lane_mask = 1 << lane_cfg->clk.pos;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun for (i = 0; i < lane_cfg->num_data; i++)
226*4882a593Smuzhiyun lane_mask |= 1 << lane_cfg->data[i].pos;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return lane_mask;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun * csiphy_stream_on - Enable streaming on CSIPHY module
233*4882a593Smuzhiyun * @csiphy: CSIPHY device
234*4882a593Smuzhiyun *
235*4882a593Smuzhiyun * Helper function to enable streaming on CSIPHY module.
236*4882a593Smuzhiyun * Main configuration of CSIPHY module is also done here.
237*4882a593Smuzhiyun *
238*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
239*4882a593Smuzhiyun */
csiphy_stream_on(struct csiphy_device * csiphy)240*4882a593Smuzhiyun static int csiphy_stream_on(struct csiphy_device *csiphy)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct csiphy_config *cfg = &csiphy->cfg;
243*4882a593Smuzhiyun u32 pixel_clock;
244*4882a593Smuzhiyun u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg);
245*4882a593Smuzhiyun u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats,
246*4882a593Smuzhiyun csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
247*4882a593Smuzhiyun u8 val;
248*4882a593Smuzhiyun int ret;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock);
251*4882a593Smuzhiyun if (ret) {
252*4882a593Smuzhiyun dev_err(csiphy->camss->dev,
253*4882a593Smuzhiyun "Cannot get CSI2 transmitter's pixel clock\n");
254*4882a593Smuzhiyun return -EINVAL;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun if (!pixel_clock) {
257*4882a593Smuzhiyun dev_err(csiphy->camss->dev,
258*4882a593Smuzhiyun "Got pixel clock == 0, cannot continue\n");
259*4882a593Smuzhiyun return -EINVAL;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun val = readl_relaxed(csiphy->base_clk_mux);
263*4882a593Smuzhiyun if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) {
264*4882a593Smuzhiyun val &= ~0xf0;
265*4882a593Smuzhiyun val |= cfg->csid_id << 4;
266*4882a593Smuzhiyun } else {
267*4882a593Smuzhiyun val &= ~0xf;
268*4882a593Smuzhiyun val |= cfg->csid_id;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun writel_relaxed(val, csiphy->base_clk_mux);
271*4882a593Smuzhiyun wmb();
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun return 0;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun /*
279*4882a593Smuzhiyun * csiphy_stream_off - Disable streaming on CSIPHY module
280*4882a593Smuzhiyun * @csiphy: CSIPHY device
281*4882a593Smuzhiyun *
282*4882a593Smuzhiyun * Helper function to disable streaming on CSIPHY module
283*4882a593Smuzhiyun */
csiphy_stream_off(struct csiphy_device * csiphy)284*4882a593Smuzhiyun static void csiphy_stream_off(struct csiphy_device *csiphy)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun csiphy->ops->lanes_disable(csiphy, &csiphy->cfg);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /*
291*4882a593Smuzhiyun * csiphy_set_stream - Enable/disable streaming on CSIPHY module
292*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
293*4882a593Smuzhiyun * @enable: Requested streaming state
294*4882a593Smuzhiyun *
295*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
296*4882a593Smuzhiyun */
csiphy_set_stream(struct v4l2_subdev * sd,int enable)297*4882a593Smuzhiyun static int csiphy_set_stream(struct v4l2_subdev *sd, int enable)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
300*4882a593Smuzhiyun int ret = 0;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (enable)
303*4882a593Smuzhiyun ret = csiphy_stream_on(csiphy);
304*4882a593Smuzhiyun else
305*4882a593Smuzhiyun csiphy_stream_off(csiphy);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /*
311*4882a593Smuzhiyun * __csiphy_get_format - Get pointer to format structure
312*4882a593Smuzhiyun * @csiphy: CSIPHY device
313*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
314*4882a593Smuzhiyun * @pad: pad from which format is requested
315*4882a593Smuzhiyun * @which: TRY or ACTIVE format
316*4882a593Smuzhiyun *
317*4882a593Smuzhiyun * Return pointer to TRY or ACTIVE format structure
318*4882a593Smuzhiyun */
319*4882a593Smuzhiyun static struct v4l2_mbus_framefmt *
__csiphy_get_format(struct csiphy_device * csiphy,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)320*4882a593Smuzhiyun __csiphy_get_format(struct csiphy_device *csiphy,
321*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
322*4882a593Smuzhiyun unsigned int pad,
323*4882a593Smuzhiyun enum v4l2_subdev_format_whence which)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun if (which == V4L2_SUBDEV_FORMAT_TRY)
326*4882a593Smuzhiyun return v4l2_subdev_get_try_format(&csiphy->subdev, cfg, pad);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun return &csiphy->fmt[pad];
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /*
332*4882a593Smuzhiyun * csiphy_try_format - Handle try format by pad subdev method
333*4882a593Smuzhiyun * @csiphy: CSIPHY device
334*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
335*4882a593Smuzhiyun * @pad: pad on which format is requested
336*4882a593Smuzhiyun * @fmt: pointer to v4l2 format structure
337*4882a593Smuzhiyun * @which: wanted subdev format
338*4882a593Smuzhiyun */
csiphy_try_format(struct csiphy_device * csiphy,struct v4l2_subdev_pad_config * cfg,unsigned int pad,struct v4l2_mbus_framefmt * fmt,enum v4l2_subdev_format_whence which)339*4882a593Smuzhiyun static void csiphy_try_format(struct csiphy_device *csiphy,
340*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
341*4882a593Smuzhiyun unsigned int pad,
342*4882a593Smuzhiyun struct v4l2_mbus_framefmt *fmt,
343*4882a593Smuzhiyun enum v4l2_subdev_format_whence which)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun unsigned int i;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun switch (pad) {
348*4882a593Smuzhiyun case MSM_CSIPHY_PAD_SINK:
349*4882a593Smuzhiyun /* Set format on sink pad */
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun for (i = 0; i < csiphy->nformats; i++)
352*4882a593Smuzhiyun if (fmt->code == csiphy->formats[i].code)
353*4882a593Smuzhiyun break;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun /* If not found, use UYVY as default */
356*4882a593Smuzhiyun if (i >= csiphy->nformats)
357*4882a593Smuzhiyun fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun fmt->width = clamp_t(u32, fmt->width, 1, 8191);
360*4882a593Smuzhiyun fmt->height = clamp_t(u32, fmt->height, 1, 8191);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun fmt->field = V4L2_FIELD_NONE;
363*4882a593Smuzhiyun fmt->colorspace = V4L2_COLORSPACE_SRGB;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun case MSM_CSIPHY_PAD_SRC:
368*4882a593Smuzhiyun /* Set and return a format same as sink pad */
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun *fmt = *__csiphy_get_format(csiphy, cfg, MSM_CSID_PAD_SINK,
371*4882a593Smuzhiyun which);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /*
378*4882a593Smuzhiyun * csiphy_enum_mbus_code - Handle pixel format enumeration
379*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
380*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
381*4882a593Smuzhiyun * @code: pointer to v4l2_subdev_mbus_code_enum structure
382*4882a593Smuzhiyun * return -EINVAL or zero on success
383*4882a593Smuzhiyun */
csiphy_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)384*4882a593Smuzhiyun static int csiphy_enum_mbus_code(struct v4l2_subdev *sd,
385*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
386*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
389*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (code->pad == MSM_CSIPHY_PAD_SINK) {
392*4882a593Smuzhiyun if (code->index >= csiphy->nformats)
393*4882a593Smuzhiyun return -EINVAL;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun code->code = csiphy->formats[code->index].code;
396*4882a593Smuzhiyun } else {
397*4882a593Smuzhiyun if (code->index > 0)
398*4882a593Smuzhiyun return -EINVAL;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SINK,
401*4882a593Smuzhiyun code->which);
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun code->code = format->code;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun return 0;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /*
410*4882a593Smuzhiyun * csiphy_enum_frame_size - Handle frame size enumeration
411*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
412*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
413*4882a593Smuzhiyun * @fse: pointer to v4l2_subdev_frame_size_enum structure
414*4882a593Smuzhiyun * return -EINVAL or zero on success
415*4882a593Smuzhiyun */
csiphy_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)416*4882a593Smuzhiyun static int csiphy_enum_frame_size(struct v4l2_subdev *sd,
417*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
418*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
421*4882a593Smuzhiyun struct v4l2_mbus_framefmt format;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun if (fse->index != 0)
424*4882a593Smuzhiyun return -EINVAL;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun format.code = fse->code;
427*4882a593Smuzhiyun format.width = 1;
428*4882a593Smuzhiyun format.height = 1;
429*4882a593Smuzhiyun csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which);
430*4882a593Smuzhiyun fse->min_width = format.width;
431*4882a593Smuzhiyun fse->min_height = format.height;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (format.code != fse->code)
434*4882a593Smuzhiyun return -EINVAL;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun format.code = fse->code;
437*4882a593Smuzhiyun format.width = -1;
438*4882a593Smuzhiyun format.height = -1;
439*4882a593Smuzhiyun csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which);
440*4882a593Smuzhiyun fse->max_width = format.width;
441*4882a593Smuzhiyun fse->max_height = format.height;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /*
447*4882a593Smuzhiyun * csiphy_get_format - Handle get format by pads subdev method
448*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
449*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
450*4882a593Smuzhiyun * @fmt: pointer to v4l2 subdev format structure
451*4882a593Smuzhiyun *
452*4882a593Smuzhiyun * Return -EINVAL or zero on success
453*4882a593Smuzhiyun */
csiphy_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)454*4882a593Smuzhiyun static int csiphy_get_format(struct v4l2_subdev *sd,
455*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
456*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
459*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which);
462*4882a593Smuzhiyun if (format == NULL)
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun fmt->format = *format;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun return 0;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun * csiphy_set_format - Handle set format by pads subdev method
472*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
473*4882a593Smuzhiyun * @cfg: V4L2 subdev pad configuration
474*4882a593Smuzhiyun * @fmt: pointer to v4l2 subdev format structure
475*4882a593Smuzhiyun *
476*4882a593Smuzhiyun * Return -EINVAL or zero on success
477*4882a593Smuzhiyun */
csiphy_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)478*4882a593Smuzhiyun static int csiphy_set_format(struct v4l2_subdev *sd,
479*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
480*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct csiphy_device *csiphy = v4l2_get_subdevdata(sd);
483*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which);
486*4882a593Smuzhiyun if (format == NULL)
487*4882a593Smuzhiyun return -EINVAL;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun csiphy_try_format(csiphy, cfg, fmt->pad, &fmt->format, fmt->which);
490*4882a593Smuzhiyun *format = fmt->format;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun /* Propagate the format from sink to source */
493*4882a593Smuzhiyun if (fmt->pad == MSM_CSIPHY_PAD_SINK) {
494*4882a593Smuzhiyun format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC,
495*4882a593Smuzhiyun fmt->which);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun *format = fmt->format;
498*4882a593Smuzhiyun csiphy_try_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC, format,
499*4882a593Smuzhiyun fmt->which);
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun return 0;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /*
506*4882a593Smuzhiyun * csiphy_init_formats - Initialize formats on all pads
507*4882a593Smuzhiyun * @sd: CSIPHY V4L2 subdevice
508*4882a593Smuzhiyun * @fh: V4L2 subdev file handle
509*4882a593Smuzhiyun *
510*4882a593Smuzhiyun * Initialize all pad formats with default values.
511*4882a593Smuzhiyun *
512*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
513*4882a593Smuzhiyun */
csiphy_init_formats(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)514*4882a593Smuzhiyun static int csiphy_init_formats(struct v4l2_subdev *sd,
515*4882a593Smuzhiyun struct v4l2_subdev_fh *fh)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun struct v4l2_subdev_format format = {
518*4882a593Smuzhiyun .pad = MSM_CSIPHY_PAD_SINK,
519*4882a593Smuzhiyun .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
520*4882a593Smuzhiyun V4L2_SUBDEV_FORMAT_ACTIVE,
521*4882a593Smuzhiyun .format = {
522*4882a593Smuzhiyun .code = MEDIA_BUS_FMT_UYVY8_2X8,
523*4882a593Smuzhiyun .width = 1920,
524*4882a593Smuzhiyun .height = 1080
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun };
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun return csiphy_set_format(sd, fh ? fh->pad : NULL, &format);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /*
532*4882a593Smuzhiyun * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources
533*4882a593Smuzhiyun * @csiphy: CSIPHY device
534*4882a593Smuzhiyun * @res: CSIPHY module resources table
535*4882a593Smuzhiyun * @id: CSIPHY module id
536*4882a593Smuzhiyun *
537*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
538*4882a593Smuzhiyun */
msm_csiphy_subdev_init(struct camss * camss,struct csiphy_device * csiphy,const struct resources * res,u8 id)539*4882a593Smuzhiyun int msm_csiphy_subdev_init(struct camss *camss,
540*4882a593Smuzhiyun struct csiphy_device *csiphy,
541*4882a593Smuzhiyun const struct resources *res, u8 id)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct device *dev = camss->dev;
544*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(dev);
545*4882a593Smuzhiyun struct resource *r;
546*4882a593Smuzhiyun int i, j;
547*4882a593Smuzhiyun int ret;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun csiphy->camss = camss;
550*4882a593Smuzhiyun csiphy->id = id;
551*4882a593Smuzhiyun csiphy->cfg.combo_mode = 0;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun if (camss->version == CAMSS_8x16) {
554*4882a593Smuzhiyun csiphy->ops = &csiphy_ops_2ph_1_0;
555*4882a593Smuzhiyun csiphy->formats = csiphy_formats_8x16;
556*4882a593Smuzhiyun csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16);
557*4882a593Smuzhiyun } else if (camss->version == CAMSS_8x96) {
558*4882a593Smuzhiyun csiphy->ops = &csiphy_ops_3ph_1_0;
559*4882a593Smuzhiyun csiphy->formats = csiphy_formats_8x96;
560*4882a593Smuzhiyun csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96);
561*4882a593Smuzhiyun } else {
562*4882a593Smuzhiyun return -EINVAL;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun /* Memory */
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
568*4882a593Smuzhiyun csiphy->base = devm_ioremap_resource(dev, r);
569*4882a593Smuzhiyun if (IS_ERR(csiphy->base)) {
570*4882a593Smuzhiyun dev_err(dev, "could not map memory\n");
571*4882a593Smuzhiyun return PTR_ERR(csiphy->base);
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
575*4882a593Smuzhiyun csiphy->base_clk_mux = devm_ioremap_resource(dev, r);
576*4882a593Smuzhiyun if (IS_ERR(csiphy->base_clk_mux)) {
577*4882a593Smuzhiyun dev_err(dev, "could not map memory\n");
578*4882a593Smuzhiyun return PTR_ERR(csiphy->base_clk_mux);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun /* Interrupt */
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun r = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
584*4882a593Smuzhiyun res->interrupt[0]);
585*4882a593Smuzhiyun if (!r) {
586*4882a593Smuzhiyun dev_err(dev, "missing IRQ\n");
587*4882a593Smuzhiyun return -EINVAL;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun csiphy->irq = r->start;
591*4882a593Smuzhiyun snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d",
592*4882a593Smuzhiyun dev_name(dev), MSM_CSIPHY_NAME, csiphy->id);
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr,
595*4882a593Smuzhiyun IRQF_TRIGGER_RISING, csiphy->irq_name, csiphy);
596*4882a593Smuzhiyun if (ret < 0) {
597*4882a593Smuzhiyun dev_err(dev, "request_irq failed: %d\n", ret);
598*4882a593Smuzhiyun return ret;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun disable_irq(csiphy->irq);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun /* Clocks */
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun csiphy->nclocks = 0;
606*4882a593Smuzhiyun while (res->clock[csiphy->nclocks])
607*4882a593Smuzhiyun csiphy->nclocks++;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun csiphy->clock = devm_kcalloc(dev,
610*4882a593Smuzhiyun csiphy->nclocks, sizeof(*csiphy->clock),
611*4882a593Smuzhiyun GFP_KERNEL);
612*4882a593Smuzhiyun if (!csiphy->clock)
613*4882a593Smuzhiyun return -ENOMEM;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun for (i = 0; i < csiphy->nclocks; i++) {
616*4882a593Smuzhiyun struct camss_clock *clock = &csiphy->clock[i];
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun clock->clk = devm_clk_get(dev, res->clock[i]);
619*4882a593Smuzhiyun if (IS_ERR(clock->clk))
620*4882a593Smuzhiyun return PTR_ERR(clock->clk);
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun clock->name = res->clock[i];
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun clock->nfreqs = 0;
625*4882a593Smuzhiyun while (res->clock_rate[i][clock->nfreqs])
626*4882a593Smuzhiyun clock->nfreqs++;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun if (!clock->nfreqs) {
629*4882a593Smuzhiyun clock->freq = NULL;
630*4882a593Smuzhiyun continue;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun clock->freq = devm_kcalloc(dev,
634*4882a593Smuzhiyun clock->nfreqs,
635*4882a593Smuzhiyun sizeof(*clock->freq),
636*4882a593Smuzhiyun GFP_KERNEL);
637*4882a593Smuzhiyun if (!clock->freq)
638*4882a593Smuzhiyun return -ENOMEM;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun for (j = 0; j < clock->nfreqs; j++)
641*4882a593Smuzhiyun clock->freq[j] = res->clock_rate[i][j];
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun return 0;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /*
648*4882a593Smuzhiyun * csiphy_link_setup - Setup CSIPHY connections
649*4882a593Smuzhiyun * @entity: Pointer to media entity structure
650*4882a593Smuzhiyun * @local: Pointer to local pad
651*4882a593Smuzhiyun * @remote: Pointer to remote pad
652*4882a593Smuzhiyun * @flags: Link flags
653*4882a593Smuzhiyun *
654*4882a593Smuzhiyun * Rreturn 0 on success
655*4882a593Smuzhiyun */
csiphy_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)656*4882a593Smuzhiyun static int csiphy_link_setup(struct media_entity *entity,
657*4882a593Smuzhiyun const struct media_pad *local,
658*4882a593Smuzhiyun const struct media_pad *remote, u32 flags)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun if ((local->flags & MEDIA_PAD_FL_SOURCE) &&
661*4882a593Smuzhiyun (flags & MEDIA_LNK_FL_ENABLED)) {
662*4882a593Smuzhiyun struct v4l2_subdev *sd;
663*4882a593Smuzhiyun struct csiphy_device *csiphy;
664*4882a593Smuzhiyun struct csid_device *csid;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun if (media_entity_remote_pad(local))
667*4882a593Smuzhiyun return -EBUSY;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun sd = media_entity_to_v4l2_subdev(entity);
670*4882a593Smuzhiyun csiphy = v4l2_get_subdevdata(sd);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun sd = media_entity_to_v4l2_subdev(remote->entity);
673*4882a593Smuzhiyun csid = v4l2_get_subdevdata(sd);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun csiphy->cfg.csid_id = csid->id;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun return 0;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops csiphy_core_ops = {
682*4882a593Smuzhiyun .s_power = csiphy_set_power,
683*4882a593Smuzhiyun };
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops csiphy_video_ops = {
686*4882a593Smuzhiyun .s_stream = csiphy_set_stream,
687*4882a593Smuzhiyun };
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops csiphy_pad_ops = {
690*4882a593Smuzhiyun .enum_mbus_code = csiphy_enum_mbus_code,
691*4882a593Smuzhiyun .enum_frame_size = csiphy_enum_frame_size,
692*4882a593Smuzhiyun .get_fmt = csiphy_get_format,
693*4882a593Smuzhiyun .set_fmt = csiphy_set_format,
694*4882a593Smuzhiyun };
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun static const struct v4l2_subdev_ops csiphy_v4l2_ops = {
697*4882a593Smuzhiyun .core = &csiphy_core_ops,
698*4882a593Smuzhiyun .video = &csiphy_video_ops,
699*4882a593Smuzhiyun .pad = &csiphy_pad_ops,
700*4882a593Smuzhiyun };
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops csiphy_v4l2_internal_ops = {
703*4882a593Smuzhiyun .open = csiphy_init_formats,
704*4882a593Smuzhiyun };
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun static const struct media_entity_operations csiphy_media_ops = {
707*4882a593Smuzhiyun .link_setup = csiphy_link_setup,
708*4882a593Smuzhiyun .link_validate = v4l2_subdev_link_validate,
709*4882a593Smuzhiyun };
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun /*
712*4882a593Smuzhiyun * msm_csiphy_register_entity - Register subdev node for CSIPHY module
713*4882a593Smuzhiyun * @csiphy: CSIPHY device
714*4882a593Smuzhiyun * @v4l2_dev: V4L2 device
715*4882a593Smuzhiyun *
716*4882a593Smuzhiyun * Return 0 on success or a negative error code otherwise
717*4882a593Smuzhiyun */
msm_csiphy_register_entity(struct csiphy_device * csiphy,struct v4l2_device * v4l2_dev)718*4882a593Smuzhiyun int msm_csiphy_register_entity(struct csiphy_device *csiphy,
719*4882a593Smuzhiyun struct v4l2_device *v4l2_dev)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun struct v4l2_subdev *sd = &csiphy->subdev;
722*4882a593Smuzhiyun struct media_pad *pads = csiphy->pads;
723*4882a593Smuzhiyun struct device *dev = csiphy->camss->dev;
724*4882a593Smuzhiyun int ret;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun v4l2_subdev_init(sd, &csiphy_v4l2_ops);
727*4882a593Smuzhiyun sd->internal_ops = &csiphy_v4l2_internal_ops;
728*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
729*4882a593Smuzhiyun snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
730*4882a593Smuzhiyun MSM_CSIPHY_NAME, csiphy->id);
731*4882a593Smuzhiyun v4l2_set_subdevdata(sd, csiphy);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun ret = csiphy_init_formats(sd, NULL);
734*4882a593Smuzhiyun if (ret < 0) {
735*4882a593Smuzhiyun dev_err(dev, "Failed to init format: %d\n", ret);
736*4882a593Smuzhiyun return ret;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun pads[MSM_CSIPHY_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
740*4882a593Smuzhiyun pads[MSM_CSIPHY_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
743*4882a593Smuzhiyun sd->entity.ops = &csiphy_media_ops;
744*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, MSM_CSIPHY_PADS_NUM, pads);
745*4882a593Smuzhiyun if (ret < 0) {
746*4882a593Smuzhiyun dev_err(dev, "Failed to init media entity: %d\n", ret);
747*4882a593Smuzhiyun return ret;
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun ret = v4l2_device_register_subdev(v4l2_dev, sd);
751*4882a593Smuzhiyun if (ret < 0) {
752*4882a593Smuzhiyun dev_err(dev, "Failed to register subdev: %d\n", ret);
753*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return ret;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun /*
760*4882a593Smuzhiyun * msm_csiphy_unregister_entity - Unregister CSIPHY module subdev node
761*4882a593Smuzhiyun * @csiphy: CSIPHY device
762*4882a593Smuzhiyun */
msm_csiphy_unregister_entity(struct csiphy_device * csiphy)763*4882a593Smuzhiyun void msm_csiphy_unregister_entity(struct csiphy_device *csiphy)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun v4l2_device_unregister_subdev(&csiphy->subdev);
766*4882a593Smuzhiyun media_entity_cleanup(&csiphy->subdev.entity);
767*4882a593Smuzhiyun }
768