xref: /OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/ispcsi2.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ispcsi2.h
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * TI OMAP3 ISP - CSI2 module
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2010 Nokia Corporation
8*4882a593Smuzhiyun  * Copyright (C) 2009 Texas Instruments, Inc.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11*4882a593Smuzhiyun  *	     Sakari Ailus <sakari.ailus@iki.fi>
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #ifndef OMAP3_ISP_CSI2_H
15*4882a593Smuzhiyun #define OMAP3_ISP_CSI2_H
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/videodev2.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct isp_csiphy;
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* This is not an exhaustive list */
23*4882a593Smuzhiyun enum isp_csi2_pix_formats {
24*4882a593Smuzhiyun 	CSI2_PIX_FMT_OTHERS = 0,
25*4882a593Smuzhiyun 	CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
26*4882a593Smuzhiyun 	CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
27*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
28*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
29*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW8 = 0x2a,
30*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
31*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
32*4882a593Smuzhiyun 	CSI2_PIX_FMT_RAW8_VP = 0x12a,
33*4882a593Smuzhiyun 	CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
34*4882a593Smuzhiyun 	CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
35*4882a593Smuzhiyun 	CSI2_USERDEF_8BIT_DATA1 = 0x40,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun enum isp_csi2_irqevents {
39*4882a593Smuzhiyun 	OCP_ERR_IRQ = 0x4000,
40*4882a593Smuzhiyun 	SHORT_PACKET_IRQ = 0x2000,
41*4882a593Smuzhiyun 	ECC_CORRECTION_IRQ = 0x1000,
42*4882a593Smuzhiyun 	ECC_NO_CORRECTION_IRQ = 0x800,
43*4882a593Smuzhiyun 	COMPLEXIO2_ERR_IRQ = 0x400,
44*4882a593Smuzhiyun 	COMPLEXIO1_ERR_IRQ = 0x200,
45*4882a593Smuzhiyun 	FIFO_OVF_IRQ = 0x100,
46*4882a593Smuzhiyun 	CONTEXT7 = 0x80,
47*4882a593Smuzhiyun 	CONTEXT6 = 0x40,
48*4882a593Smuzhiyun 	CONTEXT5 = 0x20,
49*4882a593Smuzhiyun 	CONTEXT4 = 0x10,
50*4882a593Smuzhiyun 	CONTEXT3 = 0x8,
51*4882a593Smuzhiyun 	CONTEXT2 = 0x4,
52*4882a593Smuzhiyun 	CONTEXT1 = 0x2,
53*4882a593Smuzhiyun 	CONTEXT0 = 0x1,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun enum isp_csi2_ctx_irqevents {
57*4882a593Smuzhiyun 	CTX_ECC_CORRECTION = 0x100,
58*4882a593Smuzhiyun 	CTX_LINE_NUMBER = 0x80,
59*4882a593Smuzhiyun 	CTX_FRAME_NUMBER = 0x40,
60*4882a593Smuzhiyun 	CTX_CS = 0x20,
61*4882a593Smuzhiyun 	CTX_LE = 0x8,
62*4882a593Smuzhiyun 	CTX_LS = 0x4,
63*4882a593Smuzhiyun 	CTX_FE = 0x2,
64*4882a593Smuzhiyun 	CTX_FS = 0x1,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun enum isp_csi2_frame_mode {
68*4882a593Smuzhiyun 	ISP_CSI2_FRAME_IMMEDIATE,
69*4882a593Smuzhiyun 	ISP_CSI2_FRAME_AFTERFEC,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define ISP_CSI2_MAX_CTX_NUM	7
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct isp_csi2_ctx_cfg {
75*4882a593Smuzhiyun 	u8 ctxnum;		/* context number 0 - 7 */
76*4882a593Smuzhiyun 	u8 dpcm_decompress;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	/* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
79*4882a593Smuzhiyun 	u8 virtual_id;
80*4882a593Smuzhiyun 	u16 format_id;		/* as in CSI2_CTx_CTRL2[9:0] */
81*4882a593Smuzhiyun 	u8 dpcm_predictor;	/* 1: simple, 0: advanced */
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
84*4882a593Smuzhiyun 	u16 alpha;
85*4882a593Smuzhiyun 	u16 data_offset;
86*4882a593Smuzhiyun 	u32 ping_addr;
87*4882a593Smuzhiyun 	u32 pong_addr;
88*4882a593Smuzhiyun 	u8 eof_enabled;
89*4882a593Smuzhiyun 	u8 eol_enabled;
90*4882a593Smuzhiyun 	u8 checksum_enabled;
91*4882a593Smuzhiyun 	u8 enabled;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun struct isp_csi2_timing_cfg {
95*4882a593Smuzhiyun 	u8 ionum;			/* IO1 or IO2 as in CSI2_TIMING */
96*4882a593Smuzhiyun 	unsigned force_rx_mode:1;
97*4882a593Smuzhiyun 	unsigned stop_state_16x:1;
98*4882a593Smuzhiyun 	unsigned stop_state_4x:1;
99*4882a593Smuzhiyun 	u16 stop_state_counter;
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun struct isp_csi2_ctrl_cfg {
103*4882a593Smuzhiyun 	bool vp_clk_enable;
104*4882a593Smuzhiyun 	bool vp_only_enable;
105*4882a593Smuzhiyun 	u8 vp_out_ctrl;
106*4882a593Smuzhiyun 	enum isp_csi2_frame_mode frame_mode;
107*4882a593Smuzhiyun 	bool ecc_enable;
108*4882a593Smuzhiyun 	bool if_enable;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #define CSI2_PAD_SINK		0
112*4882a593Smuzhiyun #define CSI2_PAD_SOURCE		1
113*4882a593Smuzhiyun #define CSI2_PADS_NUM		2
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #define CSI2_OUTPUT_CCDC	(1 << 0)
116*4882a593Smuzhiyun #define CSI2_OUTPUT_MEMORY	(1 << 1)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun struct isp_csi2_device {
119*4882a593Smuzhiyun 	struct v4l2_subdev subdev;
120*4882a593Smuzhiyun 	struct media_pad pads[CSI2_PADS_NUM];
121*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	struct isp_video video_out;
124*4882a593Smuzhiyun 	struct isp_device *isp;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	u8 available;		/* Is the IP present on the silicon? */
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* mem resources - enums as defined in enum isp_mem_resources */
129*4882a593Smuzhiyun 	u8 regs1;
130*4882a593Smuzhiyun 	u8 regs2;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	u32 output; /* output to CCDC, memory or both? */
133*4882a593Smuzhiyun 	bool dpcm_decompress;
134*4882a593Smuzhiyun 	unsigned int frame_skip;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	struct isp_csiphy *phy;
137*4882a593Smuzhiyun 	struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
138*4882a593Smuzhiyun 	struct isp_csi2_timing_cfg timing[2];
139*4882a593Smuzhiyun 	struct isp_csi2_ctrl_cfg ctrl;
140*4882a593Smuzhiyun 	enum isp_pipeline_stream_state state;
141*4882a593Smuzhiyun 	wait_queue_head_t wait;
142*4882a593Smuzhiyun 	atomic_t stopping;
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
146*4882a593Smuzhiyun int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
147*4882a593Smuzhiyun int omap3isp_csi2_init(struct isp_device *isp);
148*4882a593Smuzhiyun void omap3isp_csi2_cleanup(struct isp_device *isp);
149*4882a593Smuzhiyun void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
150*4882a593Smuzhiyun int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
151*4882a593Smuzhiyun 				    struct v4l2_device *vdev);
152*4882a593Smuzhiyun #endif	/* OMAP3_ISP_CSI2_H */
153