1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ispccp2.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * TI OMAP3 ISP - CCP2 module 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 8*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments, Inc. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun * Sakari Ailus <sakari.ailus@iki.fi> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef OMAP3_ISP_CCP2_H 15*4882a593Smuzhiyun #define OMAP3_ISP_CCP2_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/videodev2.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct isp_device; 20*4882a593Smuzhiyun struct isp_csiphy; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Sink and source ccp2 pads */ 23*4882a593Smuzhiyun #define CCP2_PAD_SINK 0 24*4882a593Smuzhiyun #define CCP2_PAD_SOURCE 1 25*4882a593Smuzhiyun #define CCP2_PADS_NUM 2 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* CCP2 input media entity */ 28*4882a593Smuzhiyun enum ccp2_input_entity { 29*4882a593Smuzhiyun CCP2_INPUT_NONE, 30*4882a593Smuzhiyun CCP2_INPUT_SENSOR, 31*4882a593Smuzhiyun CCP2_INPUT_MEMORY, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* CCP2 output media entity */ 35*4882a593Smuzhiyun enum ccp2_output_entity { 36*4882a593Smuzhiyun CCP2_OUTPUT_NONE, 37*4882a593Smuzhiyun CCP2_OUTPUT_CCDC, 38*4882a593Smuzhiyun CCP2_OUTPUT_MEMORY, 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Logical channel configuration */ 43*4882a593Smuzhiyun struct isp_interface_lcx_config { 44*4882a593Smuzhiyun int crc; 45*4882a593Smuzhiyun u32 data_start; 46*4882a593Smuzhiyun u32 data_size; 47*4882a593Smuzhiyun u32 format; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Memory channel configuration */ 51*4882a593Smuzhiyun struct isp_interface_mem_config { 52*4882a593Smuzhiyun u32 dst_port; 53*4882a593Smuzhiyun u32 vsize_count; 54*4882a593Smuzhiyun u32 hsize_count; 55*4882a593Smuzhiyun u32 src_ofst; 56*4882a593Smuzhiyun u32 dst_ofst; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* CCP2 device */ 60*4882a593Smuzhiyun struct isp_ccp2_device { 61*4882a593Smuzhiyun struct v4l2_subdev subdev; 62*4882a593Smuzhiyun struct v4l2_mbus_framefmt formats[CCP2_PADS_NUM]; 63*4882a593Smuzhiyun struct media_pad pads[CCP2_PADS_NUM]; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun enum ccp2_input_entity input; 66*4882a593Smuzhiyun enum ccp2_output_entity output; 67*4882a593Smuzhiyun struct isp_interface_lcx_config if_cfg; 68*4882a593Smuzhiyun struct isp_interface_mem_config mem_cfg; 69*4882a593Smuzhiyun struct isp_video video_in; 70*4882a593Smuzhiyun struct isp_csiphy *phy; 71*4882a593Smuzhiyun struct regulator *vdds_csib; 72*4882a593Smuzhiyun enum isp_pipeline_stream_state state; 73*4882a593Smuzhiyun wait_queue_head_t wait; 74*4882a593Smuzhiyun atomic_t stopping; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Function declarations */ 78*4882a593Smuzhiyun int omap3isp_ccp2_init(struct isp_device *isp); 79*4882a593Smuzhiyun void omap3isp_ccp2_cleanup(struct isp_device *isp); 80*4882a593Smuzhiyun int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2, 81*4882a593Smuzhiyun struct v4l2_device *vdev); 82*4882a593Smuzhiyun void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2); 83*4882a593Smuzhiyun void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* OMAP3_ISP_CCP2_H */ 86