1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * omap_vout.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2005-2010 Texas Instruments.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
7*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any
8*4882a593Smuzhiyun * kind, whether express or implied.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Leveraged code from the OMAP2 camera driver
11*4882a593Smuzhiyun * Video-for-Linux (Version 2) camera capture driver for
12*4882a593Smuzhiyun * the OMAP24xx camera controller.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Author: Andy Lowe (source@mvista.com)
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * Copyright (C) 2004 MontaVista Software, Inc.
17*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * History:
20*4882a593Smuzhiyun * 20-APR-2006 Khasim Modified VRFB based Rotation,
21*4882a593Smuzhiyun * The image data is always read from 0 degree
22*4882a593Smuzhiyun * view and written
23*4882a593Smuzhiyun * to the virtual space of desired rotation angle
24*4882a593Smuzhiyun * 4-DEC-2006 Jian Changed to support better memory management
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * 17-Nov-2008 Hardik Changed driver to use video_ioctl2
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * 23-Feb-2010 Vaibhav H Modified to use new DSS2 interface
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <linux/init.h>
33*4882a593Smuzhiyun #include <linux/module.h>
34*4882a593Smuzhiyun #include <linux/vmalloc.h>
35*4882a593Smuzhiyun #include <linux/sched.h>
36*4882a593Smuzhiyun #include <linux/types.h>
37*4882a593Smuzhiyun #include <linux/platform_device.h>
38*4882a593Smuzhiyun #include <linux/irq.h>
39*4882a593Smuzhiyun #include <linux/videodev2.h>
40*4882a593Smuzhiyun #include <linux/dma-mapping.h>
41*4882a593Smuzhiyun #include <linux/slab.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include <media/v4l2-device.h>
44*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
45*4882a593Smuzhiyun #include <media/v4l2-event.h>
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #include <video/omapvrfb.h>
48*4882a593Smuzhiyun #include <video/omapfb_dss.h>
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #include "omap_voutlib.h"
51*4882a593Smuzhiyun #include "omap_voutdef.h"
52*4882a593Smuzhiyun #include "omap_vout_vrfb.h"
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun MODULE_AUTHOR("Texas Instruments");
55*4882a593Smuzhiyun MODULE_DESCRIPTION("OMAP Video for Linux Video out driver");
56*4882a593Smuzhiyun MODULE_LICENSE("GPL");
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Driver Configuration macros */
59*4882a593Smuzhiyun #define VOUT_NAME "omap_vout"
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun enum omap_vout_channels {
62*4882a593Smuzhiyun OMAP_VIDEO1,
63*4882a593Smuzhiyun OMAP_VIDEO2,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Variables configurable through module params*/
67*4882a593Smuzhiyun static bool vid1_static_vrfb_alloc;
68*4882a593Smuzhiyun static bool vid2_static_vrfb_alloc;
69*4882a593Smuzhiyun static bool debug;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Module parameters */
72*4882a593Smuzhiyun module_param(vid1_static_vrfb_alloc, bool, S_IRUGO);
73*4882a593Smuzhiyun MODULE_PARM_DESC(vid1_static_vrfb_alloc,
74*4882a593Smuzhiyun "Static allocation of the VRFB buffer for video1 device");
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun module_param(vid2_static_vrfb_alloc, bool, S_IRUGO);
77*4882a593Smuzhiyun MODULE_PARM_DESC(vid2_static_vrfb_alloc,
78*4882a593Smuzhiyun "Static allocation of the VRFB buffer for video2 device");
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun module_param(debug, bool, S_IRUGO);
81*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-1)");
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* list of image formats supported by OMAP2 video pipelines */
84*4882a593Smuzhiyun static const struct v4l2_fmtdesc omap_formats[] = {
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun /* Note: V4L2 defines RGB565 as:
87*4882a593Smuzhiyun *
88*4882a593Smuzhiyun * Byte 0 Byte 1
89*4882a593Smuzhiyun * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
90*4882a593Smuzhiyun *
91*4882a593Smuzhiyun * We interpret RGB565 as:
92*4882a593Smuzhiyun *
93*4882a593Smuzhiyun * Byte 0 Byte 1
94*4882a593Smuzhiyun * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_RGB565,
97*4882a593Smuzhiyun },
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun /* Note: V4L2 defines RGB32 as: RGB-8-8-8-8 we use
100*4882a593Smuzhiyun * this for RGB24 unpack mode, the last 8 bits are ignored
101*4882a593Smuzhiyun * */
102*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_RGB32,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun /* Note: V4L2 defines RGB24 as: RGB-8-8-8 we use
106*4882a593Smuzhiyun * this for RGB24 packed mode
107*4882a593Smuzhiyun *
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_RGB24,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_YUYV,
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_UYVY,
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define NUM_OUTPUT_FORMATS (ARRAY_SIZE(omap_formats))
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun * Try format
123*4882a593Smuzhiyun */
omap_vout_try_format(struct v4l2_pix_format * pix)124*4882a593Smuzhiyun static int omap_vout_try_format(struct v4l2_pix_format *pix)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun int ifmt, bpp = 0;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun pix->height = clamp(pix->height, (u32)VID_MIN_HEIGHT,
129*4882a593Smuzhiyun (u32)VID_MAX_HEIGHT);
130*4882a593Smuzhiyun pix->width = clamp(pix->width, (u32)VID_MIN_WIDTH, (u32)VID_MAX_WIDTH);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun for (ifmt = 0; ifmt < NUM_OUTPUT_FORMATS; ifmt++) {
133*4882a593Smuzhiyun if (pix->pixelformat == omap_formats[ifmt].pixelformat)
134*4882a593Smuzhiyun break;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (ifmt == NUM_OUTPUT_FORMATS)
138*4882a593Smuzhiyun ifmt = 0;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun pix->pixelformat = omap_formats[ifmt].pixelformat;
141*4882a593Smuzhiyun pix->field = V4L2_FIELD_NONE;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun switch (pix->pixelformat) {
144*4882a593Smuzhiyun case V4L2_PIX_FMT_YUYV:
145*4882a593Smuzhiyun case V4L2_PIX_FMT_UYVY:
146*4882a593Smuzhiyun default:
147*4882a593Smuzhiyun pix->colorspace = V4L2_COLORSPACE_SRGB;
148*4882a593Smuzhiyun bpp = YUYV_BPP;
149*4882a593Smuzhiyun break;
150*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB565:
151*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB565X:
152*4882a593Smuzhiyun pix->colorspace = V4L2_COLORSPACE_SRGB;
153*4882a593Smuzhiyun bpp = RGB565_BPP;
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB24:
156*4882a593Smuzhiyun pix->colorspace = V4L2_COLORSPACE_SRGB;
157*4882a593Smuzhiyun bpp = RGB24_BPP;
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB32:
160*4882a593Smuzhiyun case V4L2_PIX_FMT_BGR32:
161*4882a593Smuzhiyun pix->colorspace = V4L2_COLORSPACE_SRGB;
162*4882a593Smuzhiyun bpp = RGB32_BPP;
163*4882a593Smuzhiyun break;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun pix->bytesperline = pix->width * bpp;
166*4882a593Smuzhiyun pix->sizeimage = pix->bytesperline * pix->height;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return bpp;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /*
172*4882a593Smuzhiyun * Convert V4L2 rotation to DSS rotation
173*4882a593Smuzhiyun * V4L2 understand 0, 90, 180, 270.
174*4882a593Smuzhiyun * Convert to 0, 1, 2 and 3 respectively for DSS
175*4882a593Smuzhiyun */
v4l2_rot_to_dss_rot(int v4l2_rotation,enum dss_rotation * rotation,bool mirror)176*4882a593Smuzhiyun static int v4l2_rot_to_dss_rot(int v4l2_rotation,
177*4882a593Smuzhiyun enum dss_rotation *rotation, bool mirror)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun int ret = 0;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun switch (v4l2_rotation) {
182*4882a593Smuzhiyun case 90:
183*4882a593Smuzhiyun *rotation = dss_rotation_90_degree;
184*4882a593Smuzhiyun break;
185*4882a593Smuzhiyun case 180:
186*4882a593Smuzhiyun *rotation = dss_rotation_180_degree;
187*4882a593Smuzhiyun break;
188*4882a593Smuzhiyun case 270:
189*4882a593Smuzhiyun *rotation = dss_rotation_270_degree;
190*4882a593Smuzhiyun break;
191*4882a593Smuzhiyun case 0:
192*4882a593Smuzhiyun *rotation = dss_rotation_0_degree;
193*4882a593Smuzhiyun break;
194*4882a593Smuzhiyun default:
195*4882a593Smuzhiyun ret = -EINVAL;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun return ret;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
omap_vout_calculate_offset(struct omap_vout_device * vout)200*4882a593Smuzhiyun static int omap_vout_calculate_offset(struct omap_vout_device *vout)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun struct omapvideo_info *ovid;
203*4882a593Smuzhiyun struct v4l2_rect *crop = &vout->crop;
204*4882a593Smuzhiyun struct v4l2_pix_format *pix = &vout->pix;
205*4882a593Smuzhiyun int *cropped_offset = &vout->cropped_offset;
206*4882a593Smuzhiyun int ps = 2, line_length = 0;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun ovid = &vout->vid_info;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun if (ovid->rotation_type == VOUT_ROT_VRFB) {
211*4882a593Smuzhiyun omap_vout_calculate_vrfb_offset(vout);
212*4882a593Smuzhiyun } else {
213*4882a593Smuzhiyun vout->line_length = line_length = pix->width;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (V4L2_PIX_FMT_YUYV == pix->pixelformat ||
216*4882a593Smuzhiyun V4L2_PIX_FMT_UYVY == pix->pixelformat)
217*4882a593Smuzhiyun ps = 2;
218*4882a593Smuzhiyun else if (V4L2_PIX_FMT_RGB32 == pix->pixelformat)
219*4882a593Smuzhiyun ps = 4;
220*4882a593Smuzhiyun else if (V4L2_PIX_FMT_RGB24 == pix->pixelformat)
221*4882a593Smuzhiyun ps = 3;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun vout->ps = ps;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun *cropped_offset = (line_length * ps) *
226*4882a593Smuzhiyun crop->top + crop->left * ps;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "%s Offset:%x\n",
230*4882a593Smuzhiyun __func__, vout->cropped_offset);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun return 0;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /*
236*4882a593Smuzhiyun * Convert V4L2 pixel format to DSS pixel format
237*4882a593Smuzhiyun */
video_mode_to_dss_mode(struct omap_vout_device * vout)238*4882a593Smuzhiyun static int video_mode_to_dss_mode(struct omap_vout_device *vout)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct omap_overlay *ovl;
241*4882a593Smuzhiyun struct omapvideo_info *ovid;
242*4882a593Smuzhiyun struct v4l2_pix_format *pix = &vout->pix;
243*4882a593Smuzhiyun enum omap_color_mode mode;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun ovid = &vout->vid_info;
246*4882a593Smuzhiyun ovl = ovid->overlays[0];
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun switch (pix->pixelformat) {
249*4882a593Smuzhiyun case V4L2_PIX_FMT_YUYV:
250*4882a593Smuzhiyun mode = OMAP_DSS_COLOR_YUV2;
251*4882a593Smuzhiyun break;
252*4882a593Smuzhiyun case V4L2_PIX_FMT_UYVY:
253*4882a593Smuzhiyun mode = OMAP_DSS_COLOR_UYVY;
254*4882a593Smuzhiyun break;
255*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB565:
256*4882a593Smuzhiyun mode = OMAP_DSS_COLOR_RGB16;
257*4882a593Smuzhiyun break;
258*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB24:
259*4882a593Smuzhiyun mode = OMAP_DSS_COLOR_RGB24P;
260*4882a593Smuzhiyun break;
261*4882a593Smuzhiyun case V4L2_PIX_FMT_RGB32:
262*4882a593Smuzhiyun mode = (ovl->id == OMAP_DSS_VIDEO1) ?
263*4882a593Smuzhiyun OMAP_DSS_COLOR_RGB24U : OMAP_DSS_COLOR_ARGB32;
264*4882a593Smuzhiyun break;
265*4882a593Smuzhiyun case V4L2_PIX_FMT_BGR32:
266*4882a593Smuzhiyun mode = OMAP_DSS_COLOR_RGBX32;
267*4882a593Smuzhiyun break;
268*4882a593Smuzhiyun default:
269*4882a593Smuzhiyun mode = -EINVAL;
270*4882a593Smuzhiyun break;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun return mode;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /*
276*4882a593Smuzhiyun * Setup the overlay
277*4882a593Smuzhiyun */
omapvid_setup_overlay(struct omap_vout_device * vout,struct omap_overlay * ovl,int posx,int posy,int outw,int outh,u32 addr)278*4882a593Smuzhiyun static int omapvid_setup_overlay(struct omap_vout_device *vout,
279*4882a593Smuzhiyun struct omap_overlay *ovl, int posx, int posy, int outw,
280*4882a593Smuzhiyun int outh, u32 addr)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun int ret = 0;
283*4882a593Smuzhiyun struct omap_overlay_info info;
284*4882a593Smuzhiyun int cropheight, cropwidth, pixwidth;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 &&
287*4882a593Smuzhiyun (outw != vout->pix.width || outh != vout->pix.height)) {
288*4882a593Smuzhiyun ret = -EINVAL;
289*4882a593Smuzhiyun goto setup_ovl_err;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun vout->dss_mode = video_mode_to_dss_mode(vout);
293*4882a593Smuzhiyun if (vout->dss_mode == -EINVAL) {
294*4882a593Smuzhiyun ret = -EINVAL;
295*4882a593Smuzhiyun goto setup_ovl_err;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* Setup the input plane parameters according to
299*4882a593Smuzhiyun * rotation value selected.
300*4882a593Smuzhiyun */
301*4882a593Smuzhiyun if (is_rotation_90_or_270(vout)) {
302*4882a593Smuzhiyun cropheight = vout->crop.width;
303*4882a593Smuzhiyun cropwidth = vout->crop.height;
304*4882a593Smuzhiyun pixwidth = vout->pix.height;
305*4882a593Smuzhiyun } else {
306*4882a593Smuzhiyun cropheight = vout->crop.height;
307*4882a593Smuzhiyun cropwidth = vout->crop.width;
308*4882a593Smuzhiyun pixwidth = vout->pix.width;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun ovl->get_overlay_info(ovl, &info);
312*4882a593Smuzhiyun info.paddr = addr;
313*4882a593Smuzhiyun info.width = cropwidth;
314*4882a593Smuzhiyun info.height = cropheight;
315*4882a593Smuzhiyun info.color_mode = vout->dss_mode;
316*4882a593Smuzhiyun info.mirror = vout->mirror;
317*4882a593Smuzhiyun info.pos_x = posx;
318*4882a593Smuzhiyun info.pos_y = posy;
319*4882a593Smuzhiyun info.out_width = outw;
320*4882a593Smuzhiyun info.out_height = outh;
321*4882a593Smuzhiyun info.global_alpha = vout->win.global_alpha;
322*4882a593Smuzhiyun if (!is_rotation_enabled(vout)) {
323*4882a593Smuzhiyun info.rotation = 0;
324*4882a593Smuzhiyun info.rotation_type = OMAP_DSS_ROT_DMA;
325*4882a593Smuzhiyun info.screen_width = pixwidth;
326*4882a593Smuzhiyun } else {
327*4882a593Smuzhiyun info.rotation = vout->rotation;
328*4882a593Smuzhiyun info.rotation_type = OMAP_DSS_ROT_VRFB;
329*4882a593Smuzhiyun info.screen_width = 2048;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
333*4882a593Smuzhiyun "%s enable=%d addr=%pad width=%d\n height=%d color_mode=%d\n"
334*4882a593Smuzhiyun "rotation=%d mirror=%d posx=%d posy=%d out_width = %d \n"
335*4882a593Smuzhiyun "out_height=%d rotation_type=%d screen_width=%d\n", __func__,
336*4882a593Smuzhiyun ovl->is_enabled(ovl), &info.paddr, info.width, info.height,
337*4882a593Smuzhiyun info.color_mode, info.rotation, info.mirror, info.pos_x,
338*4882a593Smuzhiyun info.pos_y, info.out_width, info.out_height, info.rotation_type,
339*4882a593Smuzhiyun info.screen_width);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = ovl->set_overlay_info(ovl, &info);
342*4882a593Smuzhiyun if (ret)
343*4882a593Smuzhiyun goto setup_ovl_err;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun setup_ovl_err:
348*4882a593Smuzhiyun v4l2_warn(&vout->vid_dev->v4l2_dev, "setup_overlay failed\n");
349*4882a593Smuzhiyun return ret;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /*
353*4882a593Smuzhiyun * Initialize the overlay structure
354*4882a593Smuzhiyun */
omapvid_init(struct omap_vout_device * vout,u32 addr)355*4882a593Smuzhiyun static int omapvid_init(struct omap_vout_device *vout, u32 addr)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun int ret = 0, i;
358*4882a593Smuzhiyun struct v4l2_window *win;
359*4882a593Smuzhiyun struct omap_overlay *ovl;
360*4882a593Smuzhiyun int posx, posy, outw, outh;
361*4882a593Smuzhiyun struct omap_video_timings *timing;
362*4882a593Smuzhiyun struct omapvideo_info *ovid = &vout->vid_info;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun win = &vout->win;
365*4882a593Smuzhiyun for (i = 0; i < ovid->num_overlays; i++) {
366*4882a593Smuzhiyun struct omap_dss_device *dssdev;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun ovl = ovid->overlays[i];
369*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun if (!dssdev)
372*4882a593Smuzhiyun return -EINVAL;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun timing = &dssdev->panel.timings;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun outw = win->w.width;
377*4882a593Smuzhiyun outh = win->w.height;
378*4882a593Smuzhiyun switch (vout->rotation) {
379*4882a593Smuzhiyun case dss_rotation_90_degree:
380*4882a593Smuzhiyun /* Invert the height and width for 90
381*4882a593Smuzhiyun * and 270 degree rotation
382*4882a593Smuzhiyun */
383*4882a593Smuzhiyun swap(outw, outh);
384*4882a593Smuzhiyun posy = (timing->y_res - win->w.width) - win->w.left;
385*4882a593Smuzhiyun posx = win->w.top;
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun case dss_rotation_180_degree:
389*4882a593Smuzhiyun posx = (timing->x_res - win->w.width) - win->w.left;
390*4882a593Smuzhiyun posy = (timing->y_res - win->w.height) - win->w.top;
391*4882a593Smuzhiyun break;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun case dss_rotation_270_degree:
394*4882a593Smuzhiyun swap(outw, outh);
395*4882a593Smuzhiyun posy = win->w.left;
396*4882a593Smuzhiyun posx = (timing->x_res - win->w.height) - win->w.top;
397*4882a593Smuzhiyun break;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun default:
400*4882a593Smuzhiyun posx = win->w.left;
401*4882a593Smuzhiyun posy = win->w.top;
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun ret = omapvid_setup_overlay(vout, ovl, posx, posy,
406*4882a593Smuzhiyun outw, outh, addr);
407*4882a593Smuzhiyun if (ret)
408*4882a593Smuzhiyun goto omapvid_init_err;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun return 0;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun omapvid_init_err:
413*4882a593Smuzhiyun v4l2_warn(&vout->vid_dev->v4l2_dev, "apply_changes failed\n");
414*4882a593Smuzhiyun return ret;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /*
418*4882a593Smuzhiyun * Apply the changes set the go bit of DSS
419*4882a593Smuzhiyun */
omapvid_apply_changes(struct omap_vout_device * vout)420*4882a593Smuzhiyun static int omapvid_apply_changes(struct omap_vout_device *vout)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun int i;
423*4882a593Smuzhiyun struct omap_overlay *ovl;
424*4882a593Smuzhiyun struct omapvideo_info *ovid = &vout->vid_info;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun for (i = 0; i < ovid->num_overlays; i++) {
427*4882a593Smuzhiyun struct omap_dss_device *dssdev;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun ovl = ovid->overlays[i];
430*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
431*4882a593Smuzhiyun if (!dssdev)
432*4882a593Smuzhiyun return -EINVAL;
433*4882a593Smuzhiyun ovl->manager->apply(ovl->manager);
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun return 0;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
omapvid_handle_interlace_display(struct omap_vout_device * vout,unsigned int irqstatus,u64 ts)439*4882a593Smuzhiyun static int omapvid_handle_interlace_display(struct omap_vout_device *vout,
440*4882a593Smuzhiyun unsigned int irqstatus, u64 ts)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun u32 fid;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (vout->first_int) {
445*4882a593Smuzhiyun vout->first_int = 0;
446*4882a593Smuzhiyun goto err;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun if (irqstatus & DISPC_IRQ_EVSYNC_ODD)
450*4882a593Smuzhiyun fid = 1;
451*4882a593Smuzhiyun else if (irqstatus & DISPC_IRQ_EVSYNC_EVEN)
452*4882a593Smuzhiyun fid = 0;
453*4882a593Smuzhiyun else
454*4882a593Smuzhiyun goto err;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun vout->field_id ^= 1;
457*4882a593Smuzhiyun if (fid != vout->field_id) {
458*4882a593Smuzhiyun if (fid == 0)
459*4882a593Smuzhiyun vout->field_id = fid;
460*4882a593Smuzhiyun } else if (0 == fid) {
461*4882a593Smuzhiyun if (vout->cur_frm == vout->next_frm)
462*4882a593Smuzhiyun goto err;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun vout->cur_frm->vbuf.vb2_buf.timestamp = ts;
465*4882a593Smuzhiyun vout->cur_frm->vbuf.sequence = vout->sequence++;
466*4882a593Smuzhiyun vb2_buffer_done(&vout->cur_frm->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
467*4882a593Smuzhiyun vout->cur_frm = vout->next_frm;
468*4882a593Smuzhiyun } else {
469*4882a593Smuzhiyun if (list_empty(&vout->dma_queue) ||
470*4882a593Smuzhiyun (vout->cur_frm != vout->next_frm))
471*4882a593Smuzhiyun goto err;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun return vout->field_id;
475*4882a593Smuzhiyun err:
476*4882a593Smuzhiyun return 0;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
omap_vout_isr(void * arg,unsigned int irqstatus)479*4882a593Smuzhiyun static void omap_vout_isr(void *arg, unsigned int irqstatus)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun int ret, fid, mgr_id;
482*4882a593Smuzhiyun u32 addr, irq;
483*4882a593Smuzhiyun struct omap_overlay *ovl;
484*4882a593Smuzhiyun u64 ts;
485*4882a593Smuzhiyun struct omapvideo_info *ovid;
486*4882a593Smuzhiyun struct omap_dss_device *cur_display;
487*4882a593Smuzhiyun struct omap_vout_device *vout = (struct omap_vout_device *)arg;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun ovid = &vout->vid_info;
490*4882a593Smuzhiyun ovl = ovid->overlays[0];
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun mgr_id = ovl->manager->id;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* get the display device attached to the overlay */
495*4882a593Smuzhiyun cur_display = ovl->get_device(ovl);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun if (!cur_display)
498*4882a593Smuzhiyun return;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun spin_lock(&vout->vbq_lock);
501*4882a593Smuzhiyun ts = ktime_get_ns();
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun switch (cur_display->type) {
504*4882a593Smuzhiyun case OMAP_DISPLAY_TYPE_DSI:
505*4882a593Smuzhiyun case OMAP_DISPLAY_TYPE_DPI:
506*4882a593Smuzhiyun case OMAP_DISPLAY_TYPE_DVI:
507*4882a593Smuzhiyun if (mgr_id == OMAP_DSS_CHANNEL_LCD)
508*4882a593Smuzhiyun irq = DISPC_IRQ_VSYNC;
509*4882a593Smuzhiyun else if (mgr_id == OMAP_DSS_CHANNEL_LCD2)
510*4882a593Smuzhiyun irq = DISPC_IRQ_VSYNC2;
511*4882a593Smuzhiyun else
512*4882a593Smuzhiyun goto vout_isr_err;
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun if (!(irqstatus & irq))
515*4882a593Smuzhiyun goto vout_isr_err;
516*4882a593Smuzhiyun break;
517*4882a593Smuzhiyun case OMAP_DISPLAY_TYPE_VENC:
518*4882a593Smuzhiyun fid = omapvid_handle_interlace_display(vout, irqstatus,
519*4882a593Smuzhiyun ts);
520*4882a593Smuzhiyun if (!fid)
521*4882a593Smuzhiyun goto vout_isr_err;
522*4882a593Smuzhiyun break;
523*4882a593Smuzhiyun case OMAP_DISPLAY_TYPE_HDMI:
524*4882a593Smuzhiyun if (!(irqstatus & DISPC_IRQ_EVSYNC_EVEN))
525*4882a593Smuzhiyun goto vout_isr_err;
526*4882a593Smuzhiyun break;
527*4882a593Smuzhiyun default:
528*4882a593Smuzhiyun goto vout_isr_err;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (!vout->first_int && (vout->cur_frm != vout->next_frm)) {
532*4882a593Smuzhiyun vout->cur_frm->vbuf.vb2_buf.timestamp = ts;
533*4882a593Smuzhiyun vout->cur_frm->vbuf.sequence = vout->sequence++;
534*4882a593Smuzhiyun vb2_buffer_done(&vout->cur_frm->vbuf.vb2_buf, VB2_BUF_STATE_DONE);
535*4882a593Smuzhiyun vout->cur_frm = vout->next_frm;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun vout->first_int = 0;
539*4882a593Smuzhiyun if (list_empty(&vout->dma_queue))
540*4882a593Smuzhiyun goto vout_isr_err;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun vout->next_frm = list_entry(vout->dma_queue.next,
543*4882a593Smuzhiyun struct omap_vout_buffer, queue);
544*4882a593Smuzhiyun list_del(&vout->next_frm->queue);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun addr = (unsigned long)vout->queued_buf_addr[vout->next_frm->vbuf.vb2_buf.index]
547*4882a593Smuzhiyun + vout->cropped_offset;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun /* First save the configuration in ovelray structure */
550*4882a593Smuzhiyun ret = omapvid_init(vout, addr);
551*4882a593Smuzhiyun if (ret) {
552*4882a593Smuzhiyun printk(KERN_ERR VOUT_NAME
553*4882a593Smuzhiyun "failed to set overlay info\n");
554*4882a593Smuzhiyun goto vout_isr_err;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun /* Enable the pipeline and set the Go bit */
558*4882a593Smuzhiyun ret = omapvid_apply_changes(vout);
559*4882a593Smuzhiyun if (ret)
560*4882a593Smuzhiyun printk(KERN_ERR VOUT_NAME "failed to change mode\n");
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun vout_isr_err:
563*4882a593Smuzhiyun spin_unlock(&vout->vbq_lock);
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun /*
568*4882a593Smuzhiyun * V4L2 ioctls
569*4882a593Smuzhiyun */
vidioc_querycap(struct file * file,void * fh,struct v4l2_capability * cap)570*4882a593Smuzhiyun static int vidioc_querycap(struct file *file, void *fh,
571*4882a593Smuzhiyun struct v4l2_capability *cap)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun strscpy(cap->driver, VOUT_NAME, sizeof(cap->driver));
576*4882a593Smuzhiyun strscpy(cap->card, vout->vfd->name, sizeof(cap->card));
577*4882a593Smuzhiyun snprintf(cap->bus_info, sizeof(cap->bus_info),
578*4882a593Smuzhiyun "platform:%s.%d", VOUT_NAME, vout->vid);
579*4882a593Smuzhiyun return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
vidioc_enum_fmt_vid_out(struct file * file,void * fh,struct v4l2_fmtdesc * fmt)582*4882a593Smuzhiyun static int vidioc_enum_fmt_vid_out(struct file *file, void *fh,
583*4882a593Smuzhiyun struct v4l2_fmtdesc *fmt)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun int index = fmt->index;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (index >= NUM_OUTPUT_FORMATS)
588*4882a593Smuzhiyun return -EINVAL;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun fmt->flags = omap_formats[index].flags;
591*4882a593Smuzhiyun fmt->pixelformat = omap_formats[index].pixelformat;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun return 0;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
vidioc_g_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)596*4882a593Smuzhiyun static int vidioc_g_fmt_vid_out(struct file *file, void *fh,
597*4882a593Smuzhiyun struct v4l2_format *f)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun f->fmt.pix = vout->pix;
602*4882a593Smuzhiyun return 0;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
vidioc_try_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)606*4882a593Smuzhiyun static int vidioc_try_fmt_vid_out(struct file *file, void *fh,
607*4882a593Smuzhiyun struct v4l2_format *f)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun struct omap_overlay *ovl;
610*4882a593Smuzhiyun struct omapvideo_info *ovid;
611*4882a593Smuzhiyun struct omap_video_timings *timing;
612*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
613*4882a593Smuzhiyun struct omap_dss_device *dssdev;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun ovid = &vout->vid_info;
616*4882a593Smuzhiyun ovl = ovid->overlays[0];
617*4882a593Smuzhiyun /* get the display device attached to the overlay */
618*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (!dssdev)
621*4882a593Smuzhiyun return -EINVAL;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun timing = &dssdev->panel.timings;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->y_res;
626*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->x_res;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun omap_vout_try_format(&f->fmt.pix);
629*4882a593Smuzhiyun return 0;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
vidioc_s_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)632*4882a593Smuzhiyun static int vidioc_s_fmt_vid_out(struct file *file, void *fh,
633*4882a593Smuzhiyun struct v4l2_format *f)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun int ret, bpp;
636*4882a593Smuzhiyun struct omap_overlay *ovl;
637*4882a593Smuzhiyun struct omapvideo_info *ovid;
638*4882a593Smuzhiyun struct omap_video_timings *timing;
639*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
640*4882a593Smuzhiyun struct omap_dss_device *dssdev;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun if (vb2_is_busy(&vout->vq))
643*4882a593Smuzhiyun return -EBUSY;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun ovid = &vout->vid_info;
646*4882a593Smuzhiyun ovl = ovid->overlays[0];
647*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun /* get the display device attached to the overlay */
650*4882a593Smuzhiyun if (!dssdev) {
651*4882a593Smuzhiyun ret = -EINVAL;
652*4882a593Smuzhiyun goto s_fmt_vid_out_exit;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun timing = &dssdev->panel.timings;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun /* We don't support RGB24-packed mode if vrfb rotation
657*4882a593Smuzhiyun * is enabled*/
658*4882a593Smuzhiyun if ((is_rotation_enabled(vout)) &&
659*4882a593Smuzhiyun f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) {
660*4882a593Smuzhiyun ret = -EINVAL;
661*4882a593Smuzhiyun goto s_fmt_vid_out_exit;
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun /* get the framebuffer parameters */
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun if (is_rotation_90_or_270(vout)) {
667*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->x_res;
668*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->y_res;
669*4882a593Smuzhiyun } else {
670*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->y_res;
671*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->x_res;
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun /* change to smaller size is OK */
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun bpp = omap_vout_try_format(&f->fmt.pix);
677*4882a593Smuzhiyun f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height * bpp;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /* try & set the new output format */
680*4882a593Smuzhiyun vout->bpp = bpp;
681*4882a593Smuzhiyun vout->pix = f->fmt.pix;
682*4882a593Smuzhiyun vout->vrfb_bpp = 1;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun /* If YUYV then vrfb bpp is 2, for others its 1 */
685*4882a593Smuzhiyun if (V4L2_PIX_FMT_YUYV == vout->pix.pixelformat ||
686*4882a593Smuzhiyun V4L2_PIX_FMT_UYVY == vout->pix.pixelformat)
687*4882a593Smuzhiyun vout->vrfb_bpp = 2;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun /* set default crop and win */
690*4882a593Smuzhiyun omap_vout_new_format(&vout->pix, &vout->fbuf, &vout->crop, &vout->win);
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun ret = 0;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun s_fmt_vid_out_exit:
695*4882a593Smuzhiyun return ret;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
vidioc_try_fmt_vid_overlay(struct file * file,void * fh,struct v4l2_format * f)698*4882a593Smuzhiyun static int vidioc_try_fmt_vid_overlay(struct file *file, void *fh,
699*4882a593Smuzhiyun struct v4l2_format *f)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun int ret = 0;
702*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
703*4882a593Smuzhiyun struct omap_overlay *ovl;
704*4882a593Smuzhiyun struct omapvideo_info *ovid;
705*4882a593Smuzhiyun struct v4l2_window *win = &f->fmt.win;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun ovid = &vout->vid_info;
708*4882a593Smuzhiyun ovl = ovid->overlays[0];
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun ret = omap_vout_try_window(&vout->fbuf, win);
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (!ret && !(ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA))
713*4882a593Smuzhiyun win->global_alpha = 0;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun return ret;
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun
vidioc_s_fmt_vid_overlay(struct file * file,void * fh,struct v4l2_format * f)718*4882a593Smuzhiyun static int vidioc_s_fmt_vid_overlay(struct file *file, void *fh,
719*4882a593Smuzhiyun struct v4l2_format *f)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun int ret = 0;
722*4882a593Smuzhiyun struct omap_overlay *ovl;
723*4882a593Smuzhiyun struct omapvideo_info *ovid;
724*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
725*4882a593Smuzhiyun struct v4l2_window *win = &f->fmt.win;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun ovid = &vout->vid_info;
728*4882a593Smuzhiyun ovl = ovid->overlays[0];
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun ret = omap_vout_new_window(&vout->crop, &vout->win, &vout->fbuf, win);
731*4882a593Smuzhiyun if (!ret) {
732*4882a593Smuzhiyun enum omap_dss_trans_key_type key_type =
733*4882a593Smuzhiyun OMAP_DSS_COLOR_KEY_GFX_DST;
734*4882a593Smuzhiyun int enable;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun /* Video1 plane does not support global alpha on OMAP3 */
737*4882a593Smuzhiyun if (ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA)
738*4882a593Smuzhiyun vout->win.global_alpha = win->global_alpha;
739*4882a593Smuzhiyun else
740*4882a593Smuzhiyun win->global_alpha = 0;
741*4882a593Smuzhiyun if (vout->fbuf.flags & (V4L2_FBUF_FLAG_CHROMAKEY |
742*4882a593Smuzhiyun V4L2_FBUF_FLAG_SRC_CHROMAKEY))
743*4882a593Smuzhiyun enable = 1;
744*4882a593Smuzhiyun else
745*4882a593Smuzhiyun enable = 0;
746*4882a593Smuzhiyun if (vout->fbuf.flags & V4L2_FBUF_FLAG_SRC_CHROMAKEY)
747*4882a593Smuzhiyun key_type = OMAP_DSS_COLOR_KEY_VID_SRC;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun if (ovl->manager && ovl->manager->get_manager_info &&
750*4882a593Smuzhiyun ovl->manager->set_manager_info) {
751*4882a593Smuzhiyun struct omap_overlay_manager_info info;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun ovl->manager->get_manager_info(ovl->manager, &info);
754*4882a593Smuzhiyun info.trans_enabled = enable;
755*4882a593Smuzhiyun info.trans_key_type = key_type;
756*4882a593Smuzhiyun info.trans_key = vout->win.chromakey;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun if (ovl->manager->set_manager_info(ovl->manager, &info))
759*4882a593Smuzhiyun return -EINVAL;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun return ret;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
vidioc_g_fmt_vid_overlay(struct file * file,void * fh,struct v4l2_format * f)765*4882a593Smuzhiyun static int vidioc_g_fmt_vid_overlay(struct file *file, void *fh,
766*4882a593Smuzhiyun struct v4l2_format *f)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun struct omap_overlay *ovl;
769*4882a593Smuzhiyun struct omapvideo_info *ovid;
770*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
771*4882a593Smuzhiyun struct v4l2_window *win = &f->fmt.win;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun ovid = &vout->vid_info;
774*4882a593Smuzhiyun ovl = ovid->overlays[0];
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun win->w = vout->win.w;
777*4882a593Smuzhiyun win->field = vout->win.field;
778*4882a593Smuzhiyun win->chromakey = vout->win.chromakey;
779*4882a593Smuzhiyun if (ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA)
780*4882a593Smuzhiyun win->global_alpha = vout->win.global_alpha;
781*4882a593Smuzhiyun else
782*4882a593Smuzhiyun win->global_alpha = 0;
783*4882a593Smuzhiyun win->clips = NULL;
784*4882a593Smuzhiyun win->clipcount = 0;
785*4882a593Smuzhiyun win->bitmap = NULL;
786*4882a593Smuzhiyun return 0;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
vidioc_g_selection(struct file * file,void * fh,struct v4l2_selection * sel)789*4882a593Smuzhiyun static int vidioc_g_selection(struct file *file, void *fh, struct v4l2_selection *sel)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
792*4882a593Smuzhiyun struct v4l2_pix_format *pix = &vout->pix;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
795*4882a593Smuzhiyun return -EINVAL;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun switch (sel->target) {
798*4882a593Smuzhiyun case V4L2_SEL_TGT_CROP:
799*4882a593Smuzhiyun sel->r = vout->crop;
800*4882a593Smuzhiyun break;
801*4882a593Smuzhiyun case V4L2_SEL_TGT_CROP_DEFAULT:
802*4882a593Smuzhiyun omap_vout_default_crop(&vout->pix, &vout->fbuf, &sel->r);
803*4882a593Smuzhiyun break;
804*4882a593Smuzhiyun case V4L2_SEL_TGT_CROP_BOUNDS:
805*4882a593Smuzhiyun /* Width and height are always even */
806*4882a593Smuzhiyun sel->r.width = pix->width & ~1;
807*4882a593Smuzhiyun sel->r.height = pix->height & ~1;
808*4882a593Smuzhiyun break;
809*4882a593Smuzhiyun default:
810*4882a593Smuzhiyun return -EINVAL;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun return 0;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
vidioc_s_selection(struct file * file,void * fh,struct v4l2_selection * sel)815*4882a593Smuzhiyun static int vidioc_s_selection(struct file *file, void *fh, struct v4l2_selection *sel)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun int ret = -EINVAL;
818*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
819*4882a593Smuzhiyun struct omapvideo_info *ovid;
820*4882a593Smuzhiyun struct omap_overlay *ovl;
821*4882a593Smuzhiyun struct omap_video_timings *timing;
822*4882a593Smuzhiyun struct omap_dss_device *dssdev;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
825*4882a593Smuzhiyun return -EINVAL;
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun if (sel->target != V4L2_SEL_TGT_CROP)
828*4882a593Smuzhiyun return -EINVAL;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (vb2_is_busy(&vout->vq))
831*4882a593Smuzhiyun return -EBUSY;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun ovid = &vout->vid_info;
834*4882a593Smuzhiyun ovl = ovid->overlays[0];
835*4882a593Smuzhiyun /* get the display device attached to the overlay */
836*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun if (!dssdev) {
839*4882a593Smuzhiyun ret = -EINVAL;
840*4882a593Smuzhiyun goto s_crop_err;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun timing = &dssdev->panel.timings;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun if (is_rotation_90_or_270(vout)) {
846*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->x_res;
847*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->y_res;
848*4882a593Smuzhiyun } else {
849*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->y_res;
850*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->x_res;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun ret = omap_vout_new_crop(&vout->pix, &vout->crop, &vout->win,
854*4882a593Smuzhiyun &vout->fbuf, &sel->r);
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun s_crop_err:
857*4882a593Smuzhiyun return ret;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
omap_vout_s_ctrl(struct v4l2_ctrl * ctrl)860*4882a593Smuzhiyun static int omap_vout_s_ctrl(struct v4l2_ctrl *ctrl)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun struct omap_vout_device *vout =
863*4882a593Smuzhiyun container_of(ctrl->handler, struct omap_vout_device, ctrl_handler);
864*4882a593Smuzhiyun int ret = 0;
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun switch (ctrl->id) {
867*4882a593Smuzhiyun case V4L2_CID_ROTATE: {
868*4882a593Smuzhiyun struct omapvideo_info *ovid;
869*4882a593Smuzhiyun int rotation = ctrl->val;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun ovid = &vout->vid_info;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun if (rotation && ovid->rotation_type == VOUT_ROT_NONE) {
874*4882a593Smuzhiyun ret = -ERANGE;
875*4882a593Smuzhiyun break;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun if (rotation && vout->pix.pixelformat == V4L2_PIX_FMT_RGB24) {
879*4882a593Smuzhiyun ret = -EINVAL;
880*4882a593Smuzhiyun break;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun if (v4l2_rot_to_dss_rot(rotation, &vout->rotation,
884*4882a593Smuzhiyun vout->mirror)) {
885*4882a593Smuzhiyun ret = -EINVAL;
886*4882a593Smuzhiyun break;
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun break;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun case V4L2_CID_BG_COLOR:
891*4882a593Smuzhiyun {
892*4882a593Smuzhiyun struct omap_overlay *ovl;
893*4882a593Smuzhiyun unsigned int color = ctrl->val;
894*4882a593Smuzhiyun struct omap_overlay_manager_info info;
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun ovl = vout->vid_info.overlays[0];
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun if (!ovl->manager || !ovl->manager->get_manager_info) {
899*4882a593Smuzhiyun ret = -EINVAL;
900*4882a593Smuzhiyun break;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun ovl->manager->get_manager_info(ovl->manager, &info);
904*4882a593Smuzhiyun info.default_color = color;
905*4882a593Smuzhiyun if (ovl->manager->set_manager_info(ovl->manager, &info)) {
906*4882a593Smuzhiyun ret = -EINVAL;
907*4882a593Smuzhiyun break;
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun break;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun case V4L2_CID_VFLIP:
912*4882a593Smuzhiyun {
913*4882a593Smuzhiyun struct omapvideo_info *ovid;
914*4882a593Smuzhiyun unsigned int mirror = ctrl->val;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun ovid = &vout->vid_info;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun if (mirror && ovid->rotation_type == VOUT_ROT_NONE) {
919*4882a593Smuzhiyun ret = -ERANGE;
920*4882a593Smuzhiyun break;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun if (mirror && vout->pix.pixelformat == V4L2_PIX_FMT_RGB24) {
924*4882a593Smuzhiyun ret = -EINVAL;
925*4882a593Smuzhiyun break;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun vout->mirror = mirror;
928*4882a593Smuzhiyun break;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun default:
931*4882a593Smuzhiyun return -EINVAL;
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun return ret;
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun static const struct v4l2_ctrl_ops omap_vout_ctrl_ops = {
937*4882a593Smuzhiyun .s_ctrl = omap_vout_s_ctrl,
938*4882a593Smuzhiyun };
939*4882a593Smuzhiyun
omap_vout_vb2_queue_setup(struct vb2_queue * vq,unsigned int * nbufs,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])940*4882a593Smuzhiyun static int omap_vout_vb2_queue_setup(struct vb2_queue *vq,
941*4882a593Smuzhiyun unsigned int *nbufs,
942*4882a593Smuzhiyun unsigned int *num_planes, unsigned int sizes[],
943*4882a593Smuzhiyun struct device *alloc_devs[])
944*4882a593Smuzhiyun {
945*4882a593Smuzhiyun struct omap_vout_device *vout = vb2_get_drv_priv(vq);
946*4882a593Smuzhiyun int size = vout->pix.sizeimage;
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun if (is_rotation_enabled(vout) && vq->num_buffers + *nbufs > VRFB_NUM_BUFS) {
949*4882a593Smuzhiyun *nbufs = VRFB_NUM_BUFS - vq->num_buffers;
950*4882a593Smuzhiyun if (*nbufs == 0)
951*4882a593Smuzhiyun return -EINVAL;
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun if (*num_planes)
955*4882a593Smuzhiyun return sizes[0] < size ? -EINVAL : 0;
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun *num_planes = 1;
958*4882a593Smuzhiyun sizes[0] = size;
959*4882a593Smuzhiyun return 0;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
omap_vout_vb2_prepare(struct vb2_buffer * vb)962*4882a593Smuzhiyun static int omap_vout_vb2_prepare(struct vb2_buffer *vb)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun struct omap_vout_device *vout = vb2_get_drv_priv(vb->vb2_queue);
965*4882a593Smuzhiyun struct omapvideo_info *ovid = &vout->vid_info;
966*4882a593Smuzhiyun struct omap_vout_buffer *voutbuf = vb2_to_omap_vout_buffer(vb);
967*4882a593Smuzhiyun dma_addr_t buf_phy_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun if (vb2_plane_size(vb, 0) < vout->pix.sizeimage) {
970*4882a593Smuzhiyun v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
971*4882a593Smuzhiyun "%s data will not fit into plane (%lu < %u)\n",
972*4882a593Smuzhiyun __func__, vb2_plane_size(vb, 0), vout->pix.sizeimage);
973*4882a593Smuzhiyun return -EINVAL;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun vb2_set_plane_payload(vb, 0, vout->pix.sizeimage);
977*4882a593Smuzhiyun voutbuf->vbuf.field = V4L2_FIELD_NONE;
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun vout->queued_buf_addr[vb->index] = (u8 *)buf_phy_addr;
980*4882a593Smuzhiyun if (ovid->rotation_type == VOUT_ROT_VRFB)
981*4882a593Smuzhiyun return omap_vout_prepare_vrfb(vout, vb);
982*4882a593Smuzhiyun return 0;
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
omap_vout_vb2_queue(struct vb2_buffer * vb)985*4882a593Smuzhiyun static void omap_vout_vb2_queue(struct vb2_buffer *vb)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun struct omap_vout_device *vout = vb2_get_drv_priv(vb->vb2_queue);
988*4882a593Smuzhiyun struct omap_vout_buffer *voutbuf = vb2_to_omap_vout_buffer(vb);
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun list_add_tail(&voutbuf->queue, &vout->dma_queue);
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun
omap_vout_vb2_start_streaming(struct vb2_queue * vq,unsigned int count)993*4882a593Smuzhiyun static int omap_vout_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
994*4882a593Smuzhiyun {
995*4882a593Smuzhiyun struct omap_vout_device *vout = vb2_get_drv_priv(vq);
996*4882a593Smuzhiyun struct omapvideo_info *ovid = &vout->vid_info;
997*4882a593Smuzhiyun struct omap_vout_buffer *buf, *tmp;
998*4882a593Smuzhiyun u32 addr = 0, mask = 0;
999*4882a593Smuzhiyun int ret, j;
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun /* Get the next frame from the buffer queue */
1002*4882a593Smuzhiyun vout->next_frm = vout->cur_frm = list_entry(vout->dma_queue.next,
1003*4882a593Smuzhiyun struct omap_vout_buffer, queue);
1004*4882a593Smuzhiyun /* Remove buffer from the buffer queue */
1005*4882a593Smuzhiyun list_del(&vout->cur_frm->queue);
1006*4882a593Smuzhiyun /* Initialize field_id and started member */
1007*4882a593Smuzhiyun vout->field_id = 0;
1008*4882a593Smuzhiyun vout->first_int = 1;
1009*4882a593Smuzhiyun vout->sequence = 0;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun if (omap_vout_calculate_offset(vout)) {
1012*4882a593Smuzhiyun ret = -EINVAL;
1013*4882a593Smuzhiyun goto out;
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun if (ovid->rotation_type == VOUT_ROT_VRFB)
1016*4882a593Smuzhiyun if (omap_vout_vrfb_buffer_setup(vout, &count, 0)) {
1017*4882a593Smuzhiyun ret = -ENOMEM;
1018*4882a593Smuzhiyun goto out;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun addr = (unsigned long)vout->queued_buf_addr[vout->cur_frm->vbuf.vb2_buf.index]
1022*4882a593Smuzhiyun + vout->cropped_offset;
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD
1025*4882a593Smuzhiyun | DISPC_IRQ_VSYNC2;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun /* First save the configuration in overlay structure */
1028*4882a593Smuzhiyun ret = omapvid_init(vout, addr);
1029*4882a593Smuzhiyun if (ret) {
1030*4882a593Smuzhiyun v4l2_err(&vout->vid_dev->v4l2_dev,
1031*4882a593Smuzhiyun "failed to set overlay info\n");
1032*4882a593Smuzhiyun goto streamon_err1;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun omap_dispc_register_isr(omap_vout_isr, vout, mask);
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun /* Enable the pipeline and set the Go bit */
1038*4882a593Smuzhiyun ret = omapvid_apply_changes(vout);
1039*4882a593Smuzhiyun if (ret)
1040*4882a593Smuzhiyun v4l2_err(&vout->vid_dev->v4l2_dev, "failed to change mode\n");
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun for (j = 0; j < ovid->num_overlays; j++) {
1043*4882a593Smuzhiyun struct omap_overlay *ovl = ovid->overlays[j];
1044*4882a593Smuzhiyun struct omap_dss_device *dssdev = ovl->get_device(ovl);
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun if (dssdev) {
1047*4882a593Smuzhiyun ret = ovl->enable(ovl);
1048*4882a593Smuzhiyun if (ret)
1049*4882a593Smuzhiyun goto streamon_err1;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun return 0;
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun streamon_err1:
1055*4882a593Smuzhiyun mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD
1056*4882a593Smuzhiyun | DISPC_IRQ_VSYNC2;
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun omap_dispc_unregister_isr(omap_vout_isr, vout, mask);
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun for (j = 0; j < ovid->num_overlays; j++) {
1061*4882a593Smuzhiyun struct omap_overlay *ovl = ovid->overlays[j];
1062*4882a593Smuzhiyun struct omap_dss_device *dssdev = ovl->get_device(ovl);
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun if (dssdev)
1065*4882a593Smuzhiyun ovl->disable(ovl);
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun /* Turn of the pipeline */
1068*4882a593Smuzhiyun if (omapvid_apply_changes(vout))
1069*4882a593Smuzhiyun v4l2_err(&vout->vid_dev->v4l2_dev,
1070*4882a593Smuzhiyun "failed to change mode in streamoff\n");
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun out:
1073*4882a593Smuzhiyun vb2_buffer_done(&vout->cur_frm->vbuf.vb2_buf, VB2_BUF_STATE_QUEUED);
1074*4882a593Smuzhiyun list_for_each_entry_safe(buf, tmp, &vout->dma_queue, queue) {
1075*4882a593Smuzhiyun list_del(&buf->queue);
1076*4882a593Smuzhiyun vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_QUEUED);
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun return ret;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun
omap_vout_vb2_stop_streaming(struct vb2_queue * vq)1081*4882a593Smuzhiyun static void omap_vout_vb2_stop_streaming(struct vb2_queue *vq)
1082*4882a593Smuzhiyun {
1083*4882a593Smuzhiyun struct omap_vout_device *vout = vb2_get_drv_priv(vq);
1084*4882a593Smuzhiyun struct omapvideo_info *ovid = &vout->vid_info;
1085*4882a593Smuzhiyun struct omap_vout_buffer *buf, *tmp;
1086*4882a593Smuzhiyun u32 mask = 0;
1087*4882a593Smuzhiyun int j;
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD
1090*4882a593Smuzhiyun | DISPC_IRQ_VSYNC2;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun omap_dispc_unregister_isr(omap_vout_isr, vout, mask);
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun for (j = 0; j < ovid->num_overlays; j++) {
1095*4882a593Smuzhiyun struct omap_overlay *ovl = ovid->overlays[j];
1096*4882a593Smuzhiyun struct omap_dss_device *dssdev = ovl->get_device(ovl);
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun if (dssdev)
1099*4882a593Smuzhiyun ovl->disable(ovl);
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun /* Turn of the pipeline */
1102*4882a593Smuzhiyun if (omapvid_apply_changes(vout))
1103*4882a593Smuzhiyun v4l2_err(&vout->vid_dev->v4l2_dev,
1104*4882a593Smuzhiyun "failed to change mode in streamoff\n");
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun if (vout->next_frm != vout->cur_frm)
1107*4882a593Smuzhiyun vb2_buffer_done(&vout->next_frm->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
1108*4882a593Smuzhiyun vb2_buffer_done(&vout->cur_frm->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
1109*4882a593Smuzhiyun list_for_each_entry_safe(buf, tmp, &vout->dma_queue, queue) {
1110*4882a593Smuzhiyun list_del(&buf->queue);
1111*4882a593Smuzhiyun vb2_buffer_done(&buf->vbuf.vb2_buf, VB2_BUF_STATE_ERROR);
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun
vidioc_s_fbuf(struct file * file,void * fh,const struct v4l2_framebuffer * a)1115*4882a593Smuzhiyun static int vidioc_s_fbuf(struct file *file, void *fh,
1116*4882a593Smuzhiyun const struct v4l2_framebuffer *a)
1117*4882a593Smuzhiyun {
1118*4882a593Smuzhiyun int enable = 0;
1119*4882a593Smuzhiyun struct omap_overlay *ovl;
1120*4882a593Smuzhiyun struct omapvideo_info *ovid;
1121*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
1122*4882a593Smuzhiyun struct omap_overlay_manager_info info;
1123*4882a593Smuzhiyun enum omap_dss_trans_key_type key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun ovid = &vout->vid_info;
1126*4882a593Smuzhiyun ovl = ovid->overlays[0];
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun /* OMAP DSS doesn't support Source and Destination color
1129*4882a593Smuzhiyun key together */
1130*4882a593Smuzhiyun if ((a->flags & V4L2_FBUF_FLAG_SRC_CHROMAKEY) &&
1131*4882a593Smuzhiyun (a->flags & V4L2_FBUF_FLAG_CHROMAKEY))
1132*4882a593Smuzhiyun return -EINVAL;
1133*4882a593Smuzhiyun /* OMAP DSS Doesn't support the Destination color key
1134*4882a593Smuzhiyun and alpha blending together */
1135*4882a593Smuzhiyun if ((a->flags & V4L2_FBUF_FLAG_CHROMAKEY) &&
1136*4882a593Smuzhiyun (a->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA))
1137*4882a593Smuzhiyun return -EINVAL;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun if ((a->flags & V4L2_FBUF_FLAG_SRC_CHROMAKEY)) {
1140*4882a593Smuzhiyun vout->fbuf.flags |= V4L2_FBUF_FLAG_SRC_CHROMAKEY;
1141*4882a593Smuzhiyun key_type = OMAP_DSS_COLOR_KEY_VID_SRC;
1142*4882a593Smuzhiyun } else
1143*4882a593Smuzhiyun vout->fbuf.flags &= ~V4L2_FBUF_FLAG_SRC_CHROMAKEY;
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun if ((a->flags & V4L2_FBUF_FLAG_CHROMAKEY)) {
1146*4882a593Smuzhiyun vout->fbuf.flags |= V4L2_FBUF_FLAG_CHROMAKEY;
1147*4882a593Smuzhiyun key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
1148*4882a593Smuzhiyun } else
1149*4882a593Smuzhiyun vout->fbuf.flags &= ~V4L2_FBUF_FLAG_CHROMAKEY;
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun if (a->flags & (V4L2_FBUF_FLAG_CHROMAKEY |
1152*4882a593Smuzhiyun V4L2_FBUF_FLAG_SRC_CHROMAKEY))
1153*4882a593Smuzhiyun enable = 1;
1154*4882a593Smuzhiyun else
1155*4882a593Smuzhiyun enable = 0;
1156*4882a593Smuzhiyun if (ovl->manager && ovl->manager->get_manager_info &&
1157*4882a593Smuzhiyun ovl->manager->set_manager_info) {
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun ovl->manager->get_manager_info(ovl->manager, &info);
1160*4882a593Smuzhiyun info.trans_enabled = enable;
1161*4882a593Smuzhiyun info.trans_key_type = key_type;
1162*4882a593Smuzhiyun info.trans_key = vout->win.chromakey;
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun if (ovl->manager->set_manager_info(ovl->manager, &info))
1165*4882a593Smuzhiyun return -EINVAL;
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun if (a->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) {
1168*4882a593Smuzhiyun vout->fbuf.flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
1169*4882a593Smuzhiyun enable = 1;
1170*4882a593Smuzhiyun } else {
1171*4882a593Smuzhiyun vout->fbuf.flags &= ~V4L2_FBUF_FLAG_LOCAL_ALPHA;
1172*4882a593Smuzhiyun enable = 0;
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun if (ovl->manager && ovl->manager->get_manager_info &&
1175*4882a593Smuzhiyun ovl->manager->set_manager_info) {
1176*4882a593Smuzhiyun ovl->manager->get_manager_info(ovl->manager, &info);
1177*4882a593Smuzhiyun /* enable this only if there is no zorder cap */
1178*4882a593Smuzhiyun if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
1179*4882a593Smuzhiyun info.partial_alpha_enabled = enable;
1180*4882a593Smuzhiyun if (ovl->manager->set_manager_info(ovl->manager, &info))
1181*4882a593Smuzhiyun return -EINVAL;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun return 0;
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
vidioc_g_fbuf(struct file * file,void * fh,struct v4l2_framebuffer * a)1187*4882a593Smuzhiyun static int vidioc_g_fbuf(struct file *file, void *fh,
1188*4882a593Smuzhiyun struct v4l2_framebuffer *a)
1189*4882a593Smuzhiyun {
1190*4882a593Smuzhiyun struct omap_overlay *ovl;
1191*4882a593Smuzhiyun struct omapvideo_info *ovid;
1192*4882a593Smuzhiyun struct omap_vout_device *vout = video_drvdata(file);
1193*4882a593Smuzhiyun struct omap_overlay_manager_info info;
1194*4882a593Smuzhiyun struct omap_video_timings *timing;
1195*4882a593Smuzhiyun struct omap_dss_device *dssdev;
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun ovid = &vout->vid_info;
1198*4882a593Smuzhiyun ovl = ovid->overlays[0];
1199*4882a593Smuzhiyun /* get the display device attached to the overlay */
1200*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun if (!dssdev)
1203*4882a593Smuzhiyun return -EINVAL;
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun timing = &dssdev->panel.timings;
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun vout->fbuf.fmt.height = timing->y_res;
1208*4882a593Smuzhiyun vout->fbuf.fmt.width = timing->x_res;
1209*4882a593Smuzhiyun a->fmt.field = V4L2_FIELD_NONE;
1210*4882a593Smuzhiyun a->fmt.colorspace = V4L2_COLORSPACE_SRGB;
1211*4882a593Smuzhiyun a->fmt.pixelformat = V4L2_PIX_FMT_RGBA32;
1212*4882a593Smuzhiyun a->fmt.height = vout->fbuf.fmt.height;
1213*4882a593Smuzhiyun a->fmt.width = vout->fbuf.fmt.width;
1214*4882a593Smuzhiyun a->fmt.bytesperline = vout->fbuf.fmt.width * 4;
1215*4882a593Smuzhiyun a->fmt.sizeimage = a->fmt.height * a->fmt.bytesperline;
1216*4882a593Smuzhiyun a->base = vout->fbuf.base;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun a->flags = vout->fbuf.flags;
1219*4882a593Smuzhiyun a->capability = vout->fbuf.capability;
1220*4882a593Smuzhiyun a->flags &= ~(V4L2_FBUF_FLAG_SRC_CHROMAKEY | V4L2_FBUF_FLAG_CHROMAKEY |
1221*4882a593Smuzhiyun V4L2_FBUF_FLAG_LOCAL_ALPHA);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun if (ovl->manager && ovl->manager->get_manager_info) {
1224*4882a593Smuzhiyun ovl->manager->get_manager_info(ovl->manager, &info);
1225*4882a593Smuzhiyun if (info.trans_key_type == OMAP_DSS_COLOR_KEY_VID_SRC)
1226*4882a593Smuzhiyun a->flags |= V4L2_FBUF_FLAG_SRC_CHROMAKEY;
1227*4882a593Smuzhiyun if (info.trans_key_type == OMAP_DSS_COLOR_KEY_GFX_DST)
1228*4882a593Smuzhiyun a->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
1229*4882a593Smuzhiyun if (info.partial_alpha_enabled)
1230*4882a593Smuzhiyun a->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun return 0;
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun
vidioc_enum_output(struct file * file,void * priv_fh,struct v4l2_output * out)1236*4882a593Smuzhiyun static int vidioc_enum_output(struct file *file, void *priv_fh,
1237*4882a593Smuzhiyun struct v4l2_output *out)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun if (out->index)
1240*4882a593Smuzhiyun return -EINVAL;
1241*4882a593Smuzhiyun snprintf(out->name, sizeof(out->name), "Overlay");
1242*4882a593Smuzhiyun out->type = V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY;
1243*4882a593Smuzhiyun return 0;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
vidioc_g_output(struct file * file,void * priv_fh,unsigned int * i)1246*4882a593Smuzhiyun static int vidioc_g_output(struct file *file, void *priv_fh, unsigned int *i)
1247*4882a593Smuzhiyun {
1248*4882a593Smuzhiyun *i = 0;
1249*4882a593Smuzhiyun return 0;
1250*4882a593Smuzhiyun }
1251*4882a593Smuzhiyun
vidioc_s_output(struct file * file,void * priv_fh,unsigned int i)1252*4882a593Smuzhiyun static int vidioc_s_output(struct file *file, void *priv_fh, unsigned int i)
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun return i ? -EINVAL : 0;
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun static const struct v4l2_ioctl_ops vout_ioctl_ops = {
1258*4882a593Smuzhiyun .vidioc_querycap = vidioc_querycap,
1259*4882a593Smuzhiyun .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
1260*4882a593Smuzhiyun .vidioc_g_fmt_vid_out = vidioc_g_fmt_vid_out,
1261*4882a593Smuzhiyun .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
1262*4882a593Smuzhiyun .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
1263*4882a593Smuzhiyun .vidioc_s_fbuf = vidioc_s_fbuf,
1264*4882a593Smuzhiyun .vidioc_g_fbuf = vidioc_g_fbuf,
1265*4882a593Smuzhiyun .vidioc_try_fmt_vid_out_overlay = vidioc_try_fmt_vid_overlay,
1266*4882a593Smuzhiyun .vidioc_s_fmt_vid_out_overlay = vidioc_s_fmt_vid_overlay,
1267*4882a593Smuzhiyun .vidioc_g_fmt_vid_out_overlay = vidioc_g_fmt_vid_overlay,
1268*4882a593Smuzhiyun .vidioc_g_selection = vidioc_g_selection,
1269*4882a593Smuzhiyun .vidioc_s_selection = vidioc_s_selection,
1270*4882a593Smuzhiyun .vidioc_enum_output = vidioc_enum_output,
1271*4882a593Smuzhiyun .vidioc_g_output = vidioc_g_output,
1272*4882a593Smuzhiyun .vidioc_s_output = vidioc_s_output,
1273*4882a593Smuzhiyun .vidioc_reqbufs = vb2_ioctl_reqbufs,
1274*4882a593Smuzhiyun .vidioc_create_bufs = vb2_ioctl_create_bufs,
1275*4882a593Smuzhiyun .vidioc_querybuf = vb2_ioctl_querybuf,
1276*4882a593Smuzhiyun .vidioc_qbuf = vb2_ioctl_qbuf,
1277*4882a593Smuzhiyun .vidioc_dqbuf = vb2_ioctl_dqbuf,
1278*4882a593Smuzhiyun .vidioc_expbuf = vb2_ioctl_expbuf,
1279*4882a593Smuzhiyun .vidioc_streamon = vb2_ioctl_streamon,
1280*4882a593Smuzhiyun .vidioc_streamoff = vb2_ioctl_streamoff,
1281*4882a593Smuzhiyun .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1282*4882a593Smuzhiyun .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1283*4882a593Smuzhiyun };
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun static const struct v4l2_file_operations omap_vout_fops = {
1286*4882a593Smuzhiyun .owner = THIS_MODULE,
1287*4882a593Smuzhiyun .unlocked_ioctl = video_ioctl2,
1288*4882a593Smuzhiyun .poll = vb2_fop_poll,
1289*4882a593Smuzhiyun .mmap = vb2_fop_mmap,
1290*4882a593Smuzhiyun .open = v4l2_fh_open,
1291*4882a593Smuzhiyun .release = vb2_fop_release,
1292*4882a593Smuzhiyun };
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun static const struct vb2_ops omap_vout_vb2_ops = {
1295*4882a593Smuzhiyun .queue_setup = omap_vout_vb2_queue_setup,
1296*4882a593Smuzhiyun .buf_queue = omap_vout_vb2_queue,
1297*4882a593Smuzhiyun .buf_prepare = omap_vout_vb2_prepare,
1298*4882a593Smuzhiyun .start_streaming = omap_vout_vb2_start_streaming,
1299*4882a593Smuzhiyun .stop_streaming = omap_vout_vb2_stop_streaming,
1300*4882a593Smuzhiyun .wait_prepare = vb2_ops_wait_prepare,
1301*4882a593Smuzhiyun .wait_finish = vb2_ops_wait_finish,
1302*4882a593Smuzhiyun };
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun /* Init functions used during driver initialization */
1305*4882a593Smuzhiyun /* Initial setup of video_data */
omap_vout_setup_video_data(struct omap_vout_device * vout)1306*4882a593Smuzhiyun static int __init omap_vout_setup_video_data(struct omap_vout_device *vout)
1307*4882a593Smuzhiyun {
1308*4882a593Smuzhiyun struct video_device *vfd;
1309*4882a593Smuzhiyun struct v4l2_pix_format *pix;
1310*4882a593Smuzhiyun struct omap_overlay *ovl = vout->vid_info.overlays[0];
1311*4882a593Smuzhiyun struct omap_dss_device *display = ovl->get_device(ovl);
1312*4882a593Smuzhiyun struct v4l2_ctrl_handler *hdl;
1313*4882a593Smuzhiyun struct vb2_queue *vq;
1314*4882a593Smuzhiyun int ret;
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun /* set the default pix */
1317*4882a593Smuzhiyun pix = &vout->pix;
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun /* Set the default picture of QVGA */
1320*4882a593Smuzhiyun pix->width = QQVGA_WIDTH;
1321*4882a593Smuzhiyun pix->height = QQVGA_HEIGHT;
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun /* Default pixel format is RGB 5-6-5 */
1324*4882a593Smuzhiyun pix->pixelformat = V4L2_PIX_FMT_RGB565;
1325*4882a593Smuzhiyun pix->field = V4L2_FIELD_NONE;
1326*4882a593Smuzhiyun pix->bytesperline = pix->width * 2;
1327*4882a593Smuzhiyun pix->sizeimage = pix->bytesperline * pix->height;
1328*4882a593Smuzhiyun pix->colorspace = V4L2_COLORSPACE_SRGB;
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun vout->bpp = RGB565_BPP;
1331*4882a593Smuzhiyun vout->fbuf.fmt.width = display->panel.timings.x_res;
1332*4882a593Smuzhiyun vout->fbuf.fmt.height = display->panel.timings.y_res;
1333*4882a593Smuzhiyun vout->cropped_offset = 0;
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun /* Set the data structures for the overlay parameters*/
1336*4882a593Smuzhiyun vout->fbuf.flags = V4L2_FBUF_FLAG_OVERLAY;
1337*4882a593Smuzhiyun vout->fbuf.capability = V4L2_FBUF_CAP_LOCAL_ALPHA |
1338*4882a593Smuzhiyun V4L2_FBUF_CAP_SRC_CHROMAKEY | V4L2_FBUF_CAP_CHROMAKEY |
1339*4882a593Smuzhiyun V4L2_FBUF_CAP_EXTERNOVERLAY;
1340*4882a593Smuzhiyun if (ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) {
1341*4882a593Smuzhiyun vout->win.global_alpha = 255;
1342*4882a593Smuzhiyun vout->fbuf.capability |= V4L2_FBUF_CAP_GLOBAL_ALPHA;
1343*4882a593Smuzhiyun vout->fbuf.flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA;
1344*4882a593Smuzhiyun } else {
1345*4882a593Smuzhiyun vout->win.global_alpha = 0;
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun vout->win.field = V4L2_FIELD_NONE;
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun omap_vout_new_format(pix, &vout->fbuf, &vout->crop, &vout->win);
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun hdl = &vout->ctrl_handler;
1352*4882a593Smuzhiyun v4l2_ctrl_handler_init(hdl, 3);
1353*4882a593Smuzhiyun if (vout->vid_info.rotation_type == VOUT_ROT_VRFB) {
1354*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &omap_vout_ctrl_ops,
1355*4882a593Smuzhiyun V4L2_CID_ROTATE, 0, 270, 90, 0);
1356*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &omap_vout_ctrl_ops,
1357*4882a593Smuzhiyun V4L2_CID_VFLIP, 0, 1, 1, 0);
1358*4882a593Smuzhiyun }
1359*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &omap_vout_ctrl_ops,
1360*4882a593Smuzhiyun V4L2_CID_BG_COLOR, 0, 0xffffff, 1, 0);
1361*4882a593Smuzhiyun if (hdl->error)
1362*4882a593Smuzhiyun return hdl->error;
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun vout->rotation = 0;
1365*4882a593Smuzhiyun vout->mirror = false;
1366*4882a593Smuzhiyun INIT_LIST_HEAD(&vout->dma_queue);
1367*4882a593Smuzhiyun if (vout->vid_info.rotation_type == VOUT_ROT_VRFB)
1368*4882a593Smuzhiyun vout->vrfb_bpp = 2;
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun /* initialize the video_device struct */
1371*4882a593Smuzhiyun vfd = vout->vfd = video_device_alloc();
1372*4882a593Smuzhiyun
1373*4882a593Smuzhiyun if (!vfd) {
1374*4882a593Smuzhiyun printk(KERN_ERR VOUT_NAME
1375*4882a593Smuzhiyun ": could not allocate video device struct\n");
1376*4882a593Smuzhiyun v4l2_ctrl_handler_free(hdl);
1377*4882a593Smuzhiyun return -ENOMEM;
1378*4882a593Smuzhiyun }
1379*4882a593Smuzhiyun vfd->ctrl_handler = hdl;
1380*4882a593Smuzhiyun vfd->release = video_device_release;
1381*4882a593Smuzhiyun vfd->ioctl_ops = &vout_ioctl_ops;
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun strscpy(vfd->name, VOUT_NAME, sizeof(vfd->name));
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun vfd->fops = &omap_vout_fops;
1386*4882a593Smuzhiyun vfd->v4l2_dev = &vout->vid_dev->v4l2_dev;
1387*4882a593Smuzhiyun vfd->vfl_dir = VFL_DIR_TX;
1388*4882a593Smuzhiyun vfd->minor = -1;
1389*4882a593Smuzhiyun vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT |
1390*4882a593Smuzhiyun V4L2_CAP_VIDEO_OUTPUT_OVERLAY;
1391*4882a593Smuzhiyun mutex_init(&vout->lock);
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun vq = &vout->vq;
1394*4882a593Smuzhiyun vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1395*4882a593Smuzhiyun vq->io_modes = VB2_MMAP | VB2_DMABUF;
1396*4882a593Smuzhiyun vq->drv_priv = vout;
1397*4882a593Smuzhiyun vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1398*4882a593Smuzhiyun vq->buf_struct_size = sizeof(struct omap_vout_buffer);
1399*4882a593Smuzhiyun vq->dev = vfd->v4l2_dev->dev;
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun vq->ops = &omap_vout_vb2_ops;
1402*4882a593Smuzhiyun vq->mem_ops = &vb2_dma_contig_memops;
1403*4882a593Smuzhiyun vq->lock = &vout->lock;
1404*4882a593Smuzhiyun vq->min_buffers_needed = 1;
1405*4882a593Smuzhiyun vfd->queue = vq;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun ret = vb2_queue_init(vq);
1408*4882a593Smuzhiyun if (ret) {
1409*4882a593Smuzhiyun v4l2_ctrl_handler_free(hdl);
1410*4882a593Smuzhiyun video_device_release(vfd);
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun return ret;
1413*4882a593Smuzhiyun }
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun /* Setup video buffers */
omap_vout_setup_video_bufs(struct platform_device * pdev,int vid_num)1416*4882a593Smuzhiyun static int __init omap_vout_setup_video_bufs(struct platform_device *pdev,
1417*4882a593Smuzhiyun int vid_num)
1418*4882a593Smuzhiyun {
1419*4882a593Smuzhiyun struct omapvideo_info *ovid;
1420*4882a593Smuzhiyun struct omap_vout_device *vout;
1421*4882a593Smuzhiyun struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
1422*4882a593Smuzhiyun struct omap2video_device *vid_dev =
1423*4882a593Smuzhiyun container_of(v4l2_dev, struct omap2video_device, v4l2_dev);
1424*4882a593Smuzhiyun int ret = 0;
1425*4882a593Smuzhiyun
1426*4882a593Smuzhiyun vout = vid_dev->vouts[vid_num];
1427*4882a593Smuzhiyun ovid = &vout->vid_info;
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun if (ovid->rotation_type == VOUT_ROT_VRFB) {
1430*4882a593Smuzhiyun bool static_vrfb_allocation = (vid_num == 0) ?
1431*4882a593Smuzhiyun vid1_static_vrfb_alloc : vid2_static_vrfb_alloc;
1432*4882a593Smuzhiyun ret = omap_vout_setup_vrfb_bufs(pdev, vid_num,
1433*4882a593Smuzhiyun static_vrfb_allocation);
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun return ret;
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun /* Create video out devices */
omap_vout_create_video_devices(struct platform_device * pdev)1439*4882a593Smuzhiyun static int __init omap_vout_create_video_devices(struct platform_device *pdev)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun int ret = 0, k;
1442*4882a593Smuzhiyun struct omap_vout_device *vout;
1443*4882a593Smuzhiyun struct video_device *vfd = NULL;
1444*4882a593Smuzhiyun struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
1445*4882a593Smuzhiyun struct omap2video_device *vid_dev = container_of(v4l2_dev,
1446*4882a593Smuzhiyun struct omap2video_device, v4l2_dev);
1447*4882a593Smuzhiyun struct omap_overlay *ovl = vid_dev->overlays[0];
1448*4882a593Smuzhiyun struct omap_overlay_info info;
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun ovl->get_overlay_info(ovl, &info);
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun for (k = 0; k < pdev->num_resources; k++) {
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun vout = kzalloc(sizeof(struct omap_vout_device), GFP_KERNEL);
1455*4882a593Smuzhiyun if (!vout) {
1456*4882a593Smuzhiyun dev_err(&pdev->dev, ": could not allocate memory\n");
1457*4882a593Smuzhiyun return -ENOMEM;
1458*4882a593Smuzhiyun }
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun vout->vid = k;
1461*4882a593Smuzhiyun vid_dev->vouts[k] = vout;
1462*4882a593Smuzhiyun vout->vid_dev = vid_dev;
1463*4882a593Smuzhiyun /* Select video2 if only 1 overlay is controlled by V4L2 */
1464*4882a593Smuzhiyun if (pdev->num_resources == 1)
1465*4882a593Smuzhiyun vout->vid_info.overlays[0] = vid_dev->overlays[k + 2];
1466*4882a593Smuzhiyun else
1467*4882a593Smuzhiyun /* Else select video1 and video2 one by one. */
1468*4882a593Smuzhiyun vout->vid_info.overlays[0] = vid_dev->overlays[k + 1];
1469*4882a593Smuzhiyun vout->vid_info.num_overlays = 1;
1470*4882a593Smuzhiyun vout->vid_info.id = k + 1;
1471*4882a593Smuzhiyun spin_lock_init(&vout->vbq_lock);
1472*4882a593Smuzhiyun /*
1473*4882a593Smuzhiyun * Set the framebuffer base, this allows applications to find
1474*4882a593Smuzhiyun * the fb corresponding to this overlay.
1475*4882a593Smuzhiyun *
1476*4882a593Smuzhiyun * To be precise: fbuf.base should match smem_start of
1477*4882a593Smuzhiyun * struct fb_fix_screeninfo.
1478*4882a593Smuzhiyun */
1479*4882a593Smuzhiyun vout->fbuf.base = (void *)info.paddr;
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun /* Set VRFB as rotation_type for omap2 and omap3 */
1482*4882a593Smuzhiyun if (omap_vout_dss_omap24xx() || omap_vout_dss_omap34xx())
1483*4882a593Smuzhiyun vout->vid_info.rotation_type = VOUT_ROT_VRFB;
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun /* Setup the default configuration for the video devices
1486*4882a593Smuzhiyun */
1487*4882a593Smuzhiyun if (omap_vout_setup_video_data(vout) != 0) {
1488*4882a593Smuzhiyun ret = -ENOMEM;
1489*4882a593Smuzhiyun goto error;
1490*4882a593Smuzhiyun }
1491*4882a593Smuzhiyun
1492*4882a593Smuzhiyun /* Allocate default number of buffers for the video streaming
1493*4882a593Smuzhiyun * and reserve the VRFB space for rotation
1494*4882a593Smuzhiyun */
1495*4882a593Smuzhiyun if (omap_vout_setup_video_bufs(pdev, k) != 0) {
1496*4882a593Smuzhiyun ret = -ENOMEM;
1497*4882a593Smuzhiyun goto error1;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun /* Register the Video device with V4L2
1501*4882a593Smuzhiyun */
1502*4882a593Smuzhiyun vfd = vout->vfd;
1503*4882a593Smuzhiyun if (video_register_device(vfd, VFL_TYPE_VIDEO, -1) < 0) {
1504*4882a593Smuzhiyun dev_err(&pdev->dev,
1505*4882a593Smuzhiyun ": Could not register Video for Linux device\n");
1506*4882a593Smuzhiyun vfd->minor = -1;
1507*4882a593Smuzhiyun ret = -ENODEV;
1508*4882a593Smuzhiyun goto error2;
1509*4882a593Smuzhiyun }
1510*4882a593Smuzhiyun video_set_drvdata(vfd, vout);
1511*4882a593Smuzhiyun
1512*4882a593Smuzhiyun dev_info(&pdev->dev,
1513*4882a593Smuzhiyun ": registered and initialized video device %d\n",
1514*4882a593Smuzhiyun vfd->minor);
1515*4882a593Smuzhiyun if (k == (pdev->num_resources - 1))
1516*4882a593Smuzhiyun return 0;
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun continue;
1519*4882a593Smuzhiyun error2:
1520*4882a593Smuzhiyun if (vout->vid_info.rotation_type == VOUT_ROT_VRFB)
1521*4882a593Smuzhiyun omap_vout_release_vrfb(vout);
1522*4882a593Smuzhiyun error1:
1523*4882a593Smuzhiyun video_device_release(vfd);
1524*4882a593Smuzhiyun error:
1525*4882a593Smuzhiyun kfree(vout);
1526*4882a593Smuzhiyun return ret;
1527*4882a593Smuzhiyun }
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun return -ENODEV;
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun /* Driver functions */
omap_vout_cleanup_device(struct omap_vout_device * vout)1532*4882a593Smuzhiyun static void omap_vout_cleanup_device(struct omap_vout_device *vout)
1533*4882a593Smuzhiyun {
1534*4882a593Smuzhiyun struct video_device *vfd;
1535*4882a593Smuzhiyun struct omapvideo_info *ovid;
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun if (!vout)
1538*4882a593Smuzhiyun return;
1539*4882a593Smuzhiyun
1540*4882a593Smuzhiyun vfd = vout->vfd;
1541*4882a593Smuzhiyun ovid = &vout->vid_info;
1542*4882a593Smuzhiyun if (vfd) {
1543*4882a593Smuzhiyun if (!video_is_registered(vfd)) {
1544*4882a593Smuzhiyun /*
1545*4882a593Smuzhiyun * The device was never registered, so release the
1546*4882a593Smuzhiyun * video_device struct directly.
1547*4882a593Smuzhiyun */
1548*4882a593Smuzhiyun video_device_release(vfd);
1549*4882a593Smuzhiyun } else {
1550*4882a593Smuzhiyun /*
1551*4882a593Smuzhiyun * The unregister function will release the video_device
1552*4882a593Smuzhiyun * struct as well as unregistering it.
1553*4882a593Smuzhiyun */
1554*4882a593Smuzhiyun video_unregister_device(vfd);
1555*4882a593Smuzhiyun }
1556*4882a593Smuzhiyun }
1557*4882a593Smuzhiyun v4l2_ctrl_handler_free(&vout->ctrl_handler);
1558*4882a593Smuzhiyun if (ovid->rotation_type == VOUT_ROT_VRFB) {
1559*4882a593Smuzhiyun omap_vout_release_vrfb(vout);
1560*4882a593Smuzhiyun /* Free the VRFB buffer if allocated
1561*4882a593Smuzhiyun * init time
1562*4882a593Smuzhiyun */
1563*4882a593Smuzhiyun if (vout->vrfb_static_allocation)
1564*4882a593Smuzhiyun omap_vout_free_vrfb_buffers(vout);
1565*4882a593Smuzhiyun }
1566*4882a593Smuzhiyun
1567*4882a593Smuzhiyun kfree(vout);
1568*4882a593Smuzhiyun }
1569*4882a593Smuzhiyun
omap_vout_remove(struct platform_device * pdev)1570*4882a593Smuzhiyun static int omap_vout_remove(struct platform_device *pdev)
1571*4882a593Smuzhiyun {
1572*4882a593Smuzhiyun int k;
1573*4882a593Smuzhiyun struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
1574*4882a593Smuzhiyun struct omap2video_device *vid_dev = container_of(v4l2_dev, struct
1575*4882a593Smuzhiyun omap2video_device, v4l2_dev);
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun v4l2_device_unregister(v4l2_dev);
1578*4882a593Smuzhiyun for (k = 0; k < pdev->num_resources; k++)
1579*4882a593Smuzhiyun omap_vout_cleanup_device(vid_dev->vouts[k]);
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun for (k = 0; k < vid_dev->num_displays; k++) {
1582*4882a593Smuzhiyun if (vid_dev->displays[k]->state != OMAP_DSS_DISPLAY_DISABLED)
1583*4882a593Smuzhiyun vid_dev->displays[k]->driver->disable(vid_dev->displays[k]);
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun omap_dss_put_device(vid_dev->displays[k]);
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun kfree(vid_dev);
1588*4882a593Smuzhiyun return 0;
1589*4882a593Smuzhiyun }
1590*4882a593Smuzhiyun
omap_vout_probe(struct platform_device * pdev)1591*4882a593Smuzhiyun static int __init omap_vout_probe(struct platform_device *pdev)
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun int ret = 0, i;
1594*4882a593Smuzhiyun struct omap_overlay *ovl;
1595*4882a593Smuzhiyun struct omap_dss_device *dssdev = NULL;
1596*4882a593Smuzhiyun struct omap_dss_device *def_display;
1597*4882a593Smuzhiyun struct omap2video_device *vid_dev = NULL;
1598*4882a593Smuzhiyun
1599*4882a593Smuzhiyun if (omapdss_is_initialized() == false)
1600*4882a593Smuzhiyun return -EPROBE_DEFER;
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun ret = omapdss_compat_init();
1603*4882a593Smuzhiyun if (ret) {
1604*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to init dss\n");
1605*4882a593Smuzhiyun return ret;
1606*4882a593Smuzhiyun }
1607*4882a593Smuzhiyun
1608*4882a593Smuzhiyun if (pdev->num_resources == 0) {
1609*4882a593Smuzhiyun dev_err(&pdev->dev, "probed for an unknown device\n");
1610*4882a593Smuzhiyun ret = -ENODEV;
1611*4882a593Smuzhiyun goto err_dss_init;
1612*4882a593Smuzhiyun }
1613*4882a593Smuzhiyun
1614*4882a593Smuzhiyun vid_dev = kzalloc(sizeof(struct omap2video_device), GFP_KERNEL);
1615*4882a593Smuzhiyun if (vid_dev == NULL) {
1616*4882a593Smuzhiyun ret = -ENOMEM;
1617*4882a593Smuzhiyun goto err_dss_init;
1618*4882a593Smuzhiyun }
1619*4882a593Smuzhiyun
1620*4882a593Smuzhiyun vid_dev->num_displays = 0;
1621*4882a593Smuzhiyun for_each_dss_dev(dssdev) {
1622*4882a593Smuzhiyun omap_dss_get_device(dssdev);
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun if (!dssdev->driver) {
1625*4882a593Smuzhiyun dev_warn(&pdev->dev, "no driver for display: %s\n",
1626*4882a593Smuzhiyun dssdev->name);
1627*4882a593Smuzhiyun omap_dss_put_device(dssdev);
1628*4882a593Smuzhiyun continue;
1629*4882a593Smuzhiyun }
1630*4882a593Smuzhiyun
1631*4882a593Smuzhiyun vid_dev->displays[vid_dev->num_displays++] = dssdev;
1632*4882a593Smuzhiyun }
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun if (vid_dev->num_displays == 0) {
1635*4882a593Smuzhiyun dev_err(&pdev->dev, "no displays\n");
1636*4882a593Smuzhiyun ret = -EINVAL;
1637*4882a593Smuzhiyun goto probe_err0;
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun vid_dev->num_overlays = omap_dss_get_num_overlays();
1641*4882a593Smuzhiyun for (i = 0; i < vid_dev->num_overlays; i++)
1642*4882a593Smuzhiyun vid_dev->overlays[i] = omap_dss_get_overlay(i);
1643*4882a593Smuzhiyun
1644*4882a593Smuzhiyun vid_dev->num_managers = omap_dss_get_num_overlay_managers();
1645*4882a593Smuzhiyun for (i = 0; i < vid_dev->num_managers; i++)
1646*4882a593Smuzhiyun vid_dev->managers[i] = omap_dss_get_overlay_manager(i);
1647*4882a593Smuzhiyun
1648*4882a593Smuzhiyun /* Get the Video1 overlay and video2 overlay.
1649*4882a593Smuzhiyun * Setup the Display attached to that overlays
1650*4882a593Smuzhiyun */
1651*4882a593Smuzhiyun for (i = 1; i < vid_dev->num_overlays; i++) {
1652*4882a593Smuzhiyun ovl = omap_dss_get_overlay(i);
1653*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
1654*4882a593Smuzhiyun
1655*4882a593Smuzhiyun if (dssdev) {
1656*4882a593Smuzhiyun def_display = dssdev;
1657*4882a593Smuzhiyun } else {
1658*4882a593Smuzhiyun dev_warn(&pdev->dev, "cannot find display\n");
1659*4882a593Smuzhiyun def_display = NULL;
1660*4882a593Smuzhiyun }
1661*4882a593Smuzhiyun if (def_display) {
1662*4882a593Smuzhiyun struct omap_dss_driver *dssdrv = def_display->driver;
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun ret = dssdrv->enable(def_display);
1665*4882a593Smuzhiyun if (ret) {
1666*4882a593Smuzhiyun /* Here we are not considering a error
1667*4882a593Smuzhiyun * as display may be enabled by frame
1668*4882a593Smuzhiyun * buffer driver
1669*4882a593Smuzhiyun */
1670*4882a593Smuzhiyun dev_warn(&pdev->dev,
1671*4882a593Smuzhiyun "'%s' Display already enabled\n",
1672*4882a593Smuzhiyun def_display->name);
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun }
1675*4882a593Smuzhiyun }
1676*4882a593Smuzhiyun
1677*4882a593Smuzhiyun if (v4l2_device_register(&pdev->dev, &vid_dev->v4l2_dev) < 0) {
1678*4882a593Smuzhiyun dev_err(&pdev->dev, "v4l2_device_register failed\n");
1679*4882a593Smuzhiyun ret = -ENODEV;
1680*4882a593Smuzhiyun goto probe_err1;
1681*4882a593Smuzhiyun }
1682*4882a593Smuzhiyun
1683*4882a593Smuzhiyun ret = omap_vout_create_video_devices(pdev);
1684*4882a593Smuzhiyun if (ret)
1685*4882a593Smuzhiyun goto probe_err2;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun for (i = 0; i < vid_dev->num_displays; i++) {
1688*4882a593Smuzhiyun struct omap_dss_device *display = vid_dev->displays[i];
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun if (display->driver->update)
1691*4882a593Smuzhiyun display->driver->update(display, 0, 0,
1692*4882a593Smuzhiyun display->panel.timings.x_res,
1693*4882a593Smuzhiyun display->panel.timings.y_res);
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun return 0;
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun probe_err2:
1698*4882a593Smuzhiyun v4l2_device_unregister(&vid_dev->v4l2_dev);
1699*4882a593Smuzhiyun probe_err1:
1700*4882a593Smuzhiyun for (i = 1; i < vid_dev->num_overlays; i++) {
1701*4882a593Smuzhiyun def_display = NULL;
1702*4882a593Smuzhiyun ovl = omap_dss_get_overlay(i);
1703*4882a593Smuzhiyun dssdev = ovl->get_device(ovl);
1704*4882a593Smuzhiyun
1705*4882a593Smuzhiyun if (dssdev)
1706*4882a593Smuzhiyun def_display = dssdev;
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun if (def_display && def_display->driver)
1709*4882a593Smuzhiyun def_display->driver->disable(def_display);
1710*4882a593Smuzhiyun }
1711*4882a593Smuzhiyun probe_err0:
1712*4882a593Smuzhiyun kfree(vid_dev);
1713*4882a593Smuzhiyun err_dss_init:
1714*4882a593Smuzhiyun omapdss_compat_uninit();
1715*4882a593Smuzhiyun return ret;
1716*4882a593Smuzhiyun }
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun static struct platform_driver omap_vout_driver = {
1719*4882a593Smuzhiyun .driver = {
1720*4882a593Smuzhiyun .name = VOUT_NAME,
1721*4882a593Smuzhiyun },
1722*4882a593Smuzhiyun .remove = omap_vout_remove,
1723*4882a593Smuzhiyun };
1724*4882a593Smuzhiyun
omap_vout_init(void)1725*4882a593Smuzhiyun static int __init omap_vout_init(void)
1726*4882a593Smuzhiyun {
1727*4882a593Smuzhiyun if (platform_driver_probe(&omap_vout_driver, omap_vout_probe) != 0) {
1728*4882a593Smuzhiyun printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n");
1729*4882a593Smuzhiyun return -EINVAL;
1730*4882a593Smuzhiyun }
1731*4882a593Smuzhiyun return 0;
1732*4882a593Smuzhiyun }
1733*4882a593Smuzhiyun
omap_vout_cleanup(void)1734*4882a593Smuzhiyun static void omap_vout_cleanup(void)
1735*4882a593Smuzhiyun {
1736*4882a593Smuzhiyun platform_driver_unregister(&omap_vout_driver);
1737*4882a593Smuzhiyun }
1738*4882a593Smuzhiyun
1739*4882a593Smuzhiyun late_initcall(omap_vout_init);
1740*4882a593Smuzhiyun module_exit(omap_vout_cleanup);
1741