xref: /OK3568_Linux_fs/kernel/drivers/media/platform/marvell-ccic/mmp-driver.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Support for the camera device found on Marvell MMP processors; known
4*4882a593Smuzhiyun  * to work with the Armada 610 as used in the OLPC 1.75 system.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright 2011 Jonathan Corbet <corbet@lwn.net>
7*4882a593Smuzhiyun  * Copyright 2018 Lubomir Rintel <lkundrak@v3.sk>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/spinlock.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/videodev2.h>
17*4882a593Smuzhiyun #include <media/v4l2-device.h>
18*4882a593Smuzhiyun #include <linux/platform_data/media/mmp-camera.h>
19*4882a593Smuzhiyun #include <linux/device.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/pm_runtime.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun #include <linux/list.h>
26*4882a593Smuzhiyun #include <linux/pm.h>
27*4882a593Smuzhiyun #include <linux/clk.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include "mcam-core.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun MODULE_ALIAS("platform:mmp-camera");
32*4882a593Smuzhiyun MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
33*4882a593Smuzhiyun MODULE_LICENSE("GPL");
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static char *mcam_clks[] = {"axi", "func", "phy"};
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun struct mmp_camera {
38*4882a593Smuzhiyun 	struct platform_device *pdev;
39*4882a593Smuzhiyun 	struct mcam_camera mcam;
40*4882a593Smuzhiyun 	struct list_head devlist;
41*4882a593Smuzhiyun 	struct clk *mipi_clk;
42*4882a593Smuzhiyun 	int irq;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
mcam_to_cam(struct mcam_camera * mcam)45*4882a593Smuzhiyun static inline struct mmp_camera *mcam_to_cam(struct mcam_camera *mcam)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	return container_of(mcam, struct mmp_camera, mcam);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun  * calc the dphy register values
52*4882a593Smuzhiyun  * There are three dphy registers being used.
53*4882a593Smuzhiyun  * dphy[0] - CSI2_DPHY3
54*4882a593Smuzhiyun  * dphy[1] - CSI2_DPHY5
55*4882a593Smuzhiyun  * dphy[2] - CSI2_DPHY6
56*4882a593Smuzhiyun  * CSI2_DPHY3 and CSI2_DPHY6 can be set with a default value
57*4882a593Smuzhiyun  * or be calculated dynamically
58*4882a593Smuzhiyun  */
mmpcam_calc_dphy(struct mcam_camera * mcam)59*4882a593Smuzhiyun static void mmpcam_calc_dphy(struct mcam_camera *mcam)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct mmp_camera *cam = mcam_to_cam(mcam);
62*4882a593Smuzhiyun 	struct mmp_camera_platform_data *pdata = cam->pdev->dev.platform_data;
63*4882a593Smuzhiyun 	struct device *dev = &cam->pdev->dev;
64*4882a593Smuzhiyun 	unsigned long tx_clk_esc;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	/*
67*4882a593Smuzhiyun 	 * If CSI2_DPHY3 is calculated dynamically,
68*4882a593Smuzhiyun 	 * pdata->lane_clk should be already set
69*4882a593Smuzhiyun 	 * either in the board driver statically
70*4882a593Smuzhiyun 	 * or in the sensor driver dynamically.
71*4882a593Smuzhiyun 	 */
72*4882a593Smuzhiyun 	/*
73*4882a593Smuzhiyun 	 * dphy[0] - CSI2_DPHY3:
74*4882a593Smuzhiyun 	 *  bit 0 ~ bit 7: HS Term Enable.
75*4882a593Smuzhiyun 	 *   defines the time that the DPHY
76*4882a593Smuzhiyun 	 *   wait before enabling the data
77*4882a593Smuzhiyun 	 *   lane termination after detecting
78*4882a593Smuzhiyun 	 *   that the sensor has driven the data
79*4882a593Smuzhiyun 	 *   lanes to the LP00 bridge state.
80*4882a593Smuzhiyun 	 *   The value is calculated by:
81*4882a593Smuzhiyun 	 *   (Max T(D_TERM_EN)/Period(DDR)) - 1
82*4882a593Smuzhiyun 	 *  bit 8 ~ bit 15: HS_SETTLE
83*4882a593Smuzhiyun 	 *   Time interval during which the HS
84*4882a593Smuzhiyun 	 *   receiver shall ignore any Data Lane
85*4882a593Smuzhiyun 	 *   HS transitions.
86*4882a593Smuzhiyun 	 *   The value has been calibrated on
87*4882a593Smuzhiyun 	 *   different boards. It seems to work well.
88*4882a593Smuzhiyun 	 *
89*4882a593Smuzhiyun 	 *  More detail please refer
90*4882a593Smuzhiyun 	 *  MIPI Alliance Spectification for D-PHY
91*4882a593Smuzhiyun 	 *  document for explanation of HS-SETTLE
92*4882a593Smuzhiyun 	 *  and D-TERM-EN.
93*4882a593Smuzhiyun 	 */
94*4882a593Smuzhiyun 	switch (pdata->dphy3_algo) {
95*4882a593Smuzhiyun 	case DPHY3_ALGO_PXA910:
96*4882a593Smuzhiyun 		/*
97*4882a593Smuzhiyun 		 * Calculate CSI2_DPHY3 algo for PXA910
98*4882a593Smuzhiyun 		 */
99*4882a593Smuzhiyun 		pdata->dphy[0] =
100*4882a593Smuzhiyun 			(((1 + (pdata->lane_clk * 80) / 1000) & 0xff) << 8)
101*4882a593Smuzhiyun 			| (1 + pdata->lane_clk * 35 / 1000);
102*4882a593Smuzhiyun 		break;
103*4882a593Smuzhiyun 	case DPHY3_ALGO_PXA2128:
104*4882a593Smuzhiyun 		/*
105*4882a593Smuzhiyun 		 * Calculate CSI2_DPHY3 algo for PXA2128
106*4882a593Smuzhiyun 		 */
107*4882a593Smuzhiyun 		pdata->dphy[0] =
108*4882a593Smuzhiyun 			(((2 + (pdata->lane_clk * 110) / 1000) & 0xff) << 8)
109*4882a593Smuzhiyun 			| (1 + pdata->lane_clk * 35 / 1000);
110*4882a593Smuzhiyun 		break;
111*4882a593Smuzhiyun 	default:
112*4882a593Smuzhiyun 		/*
113*4882a593Smuzhiyun 		 * Use default CSI2_DPHY3 value for PXA688/PXA988
114*4882a593Smuzhiyun 		 */
115*4882a593Smuzhiyun 		dev_dbg(dev, "camera: use the default CSI2_DPHY3 value\n");
116*4882a593Smuzhiyun 	}
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/*
119*4882a593Smuzhiyun 	 * mipi_clk will never be changed, it is a fixed value on MMP
120*4882a593Smuzhiyun 	 */
121*4882a593Smuzhiyun 	if (IS_ERR(cam->mipi_clk))
122*4882a593Smuzhiyun 		return;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* get the escape clk, this is hard coded */
125*4882a593Smuzhiyun 	clk_prepare_enable(cam->mipi_clk);
126*4882a593Smuzhiyun 	tx_clk_esc = (clk_get_rate(cam->mipi_clk) / 1000000) / 12;
127*4882a593Smuzhiyun 	clk_disable_unprepare(cam->mipi_clk);
128*4882a593Smuzhiyun 	/*
129*4882a593Smuzhiyun 	 * dphy[2] - CSI2_DPHY6:
130*4882a593Smuzhiyun 	 * bit 0 ~ bit 7: CK Term Enable
131*4882a593Smuzhiyun 	 *  Time for the Clock Lane receiver to enable the HS line
132*4882a593Smuzhiyun 	 *  termination. The value is calculated similarly with
133*4882a593Smuzhiyun 	 *  HS Term Enable
134*4882a593Smuzhiyun 	 * bit 8 ~ bit 15: CK Settle
135*4882a593Smuzhiyun 	 *  Time interval during which the HS receiver shall ignore
136*4882a593Smuzhiyun 	 *  any Clock Lane HS transitions.
137*4882a593Smuzhiyun 	 *  The value is calibrated on the boards.
138*4882a593Smuzhiyun 	 */
139*4882a593Smuzhiyun 	pdata->dphy[2] =
140*4882a593Smuzhiyun 		((((534 * tx_clk_esc) / 2000 - 1) & 0xff) << 8)
141*4882a593Smuzhiyun 		| (((38 * tx_clk_esc) / 1000 - 1) & 0xff);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	dev_dbg(dev, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
144*4882a593Smuzhiyun 		pdata->dphy[0], pdata->dphy[1], pdata->dphy[2]);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
mmpcam_irq(int irq,void * data)147*4882a593Smuzhiyun static irqreturn_t mmpcam_irq(int irq, void *data)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	struct mcam_camera *mcam = data;
150*4882a593Smuzhiyun 	unsigned int irqs, handled;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	spin_lock(&mcam->dev_lock);
153*4882a593Smuzhiyun 	irqs = mcam_reg_read(mcam, REG_IRQSTAT);
154*4882a593Smuzhiyun 	handled = mccic_irq(mcam, irqs);
155*4882a593Smuzhiyun 	spin_unlock(&mcam->dev_lock);
156*4882a593Smuzhiyun 	return IRQ_RETVAL(handled);
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
mcam_init_clk(struct mcam_camera * mcam)159*4882a593Smuzhiyun static void mcam_init_clk(struct mcam_camera *mcam)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	unsigned int i;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	for (i = 0; i < NR_MCAM_CLK; i++) {
164*4882a593Smuzhiyun 		if (mcam_clks[i] != NULL) {
165*4882a593Smuzhiyun 			/* Some clks are not necessary on some boards
166*4882a593Smuzhiyun 			 * We still try to run even it fails getting clk
167*4882a593Smuzhiyun 			 */
168*4882a593Smuzhiyun 			mcam->clk[i] = devm_clk_get(mcam->dev, mcam_clks[i]);
169*4882a593Smuzhiyun 			if (IS_ERR(mcam->clk[i]))
170*4882a593Smuzhiyun 				dev_warn(mcam->dev, "Could not get clk: %s\n",
171*4882a593Smuzhiyun 						mcam_clks[i]);
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
mmpcam_probe(struct platform_device * pdev)176*4882a593Smuzhiyun static int mmpcam_probe(struct platform_device *pdev)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct mmp_camera *cam;
179*4882a593Smuzhiyun 	struct mcam_camera *mcam;
180*4882a593Smuzhiyun 	struct resource *res;
181*4882a593Smuzhiyun 	struct fwnode_handle *ep;
182*4882a593Smuzhiyun 	struct mmp_camera_platform_data *pdata;
183*4882a593Smuzhiyun 	int ret;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	cam = devm_kzalloc(&pdev->dev, sizeof(*cam), GFP_KERNEL);
186*4882a593Smuzhiyun 	if (cam == NULL)
187*4882a593Smuzhiyun 		return -ENOMEM;
188*4882a593Smuzhiyun 	platform_set_drvdata(pdev, cam);
189*4882a593Smuzhiyun 	cam->pdev = pdev;
190*4882a593Smuzhiyun 	INIT_LIST_HEAD(&cam->devlist);
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	mcam = &cam->mcam;
193*4882a593Smuzhiyun 	mcam->calc_dphy = mmpcam_calc_dphy;
194*4882a593Smuzhiyun 	mcam->dev = &pdev->dev;
195*4882a593Smuzhiyun 	pdata = pdev->dev.platform_data;
196*4882a593Smuzhiyun 	if (pdata) {
197*4882a593Smuzhiyun 		mcam->mclk_src = pdata->mclk_src;
198*4882a593Smuzhiyun 		mcam->mclk_div = pdata->mclk_div;
199*4882a593Smuzhiyun 		mcam->bus_type = pdata->bus_type;
200*4882a593Smuzhiyun 		mcam->dphy = pdata->dphy;
201*4882a593Smuzhiyun 		mcam->lane = pdata->lane;
202*4882a593Smuzhiyun 	} else {
203*4882a593Smuzhiyun 		/*
204*4882a593Smuzhiyun 		 * These are values that used to be hardcoded in mcam-core and
205*4882a593Smuzhiyun 		 * work well on a OLPC XO 1.75 with a parallel bus sensor.
206*4882a593Smuzhiyun 		 * If it turns out other setups make sense, the values should
207*4882a593Smuzhiyun 		 * be obtained from the device tree.
208*4882a593Smuzhiyun 		 */
209*4882a593Smuzhiyun 		mcam->mclk_src = 3;
210*4882a593Smuzhiyun 		mcam->mclk_div = 2;
211*4882a593Smuzhiyun 	}
212*4882a593Smuzhiyun 	if (mcam->bus_type == V4L2_MBUS_CSI2_DPHY) {
213*4882a593Smuzhiyun 		cam->mipi_clk = devm_clk_get(mcam->dev, "mipi");
214*4882a593Smuzhiyun 		if ((IS_ERR(cam->mipi_clk) && mcam->dphy[2] == 0))
215*4882a593Smuzhiyun 			return PTR_ERR(cam->mipi_clk);
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 	mcam->mipi_enabled = false;
218*4882a593Smuzhiyun 	mcam->chip_id = MCAM_ARMADA610;
219*4882a593Smuzhiyun 	mcam->buffer_mode = B_DMA_sg;
220*4882a593Smuzhiyun 	strscpy(mcam->bus_info, "platform:mmp-camera", sizeof(mcam->bus_info));
221*4882a593Smuzhiyun 	spin_lock_init(&mcam->dev_lock);
222*4882a593Smuzhiyun 	/*
223*4882a593Smuzhiyun 	 * Get our I/O memory.
224*4882a593Smuzhiyun 	 */
225*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226*4882a593Smuzhiyun 	mcam->regs = devm_ioremap_resource(&pdev->dev, res);
227*4882a593Smuzhiyun 	if (IS_ERR(mcam->regs))
228*4882a593Smuzhiyun 		return PTR_ERR(mcam->regs);
229*4882a593Smuzhiyun 	mcam->regs_size = resource_size(res);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	mcam_init_clk(mcam);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	/*
234*4882a593Smuzhiyun 	 * Create a match of the sensor against its OF node.
235*4882a593Smuzhiyun 	 */
236*4882a593Smuzhiyun 	ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(pdev->dev.of_node),
237*4882a593Smuzhiyun 					    NULL);
238*4882a593Smuzhiyun 	if (!ep)
239*4882a593Smuzhiyun 		return -ENODEV;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	mcam->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
242*4882a593Smuzhiyun 	mcam->asd.match.fwnode = fwnode_graph_get_remote_port_parent(ep);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	fwnode_handle_put(ep);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/*
247*4882a593Smuzhiyun 	 * Register the device with the core.
248*4882a593Smuzhiyun 	 */
249*4882a593Smuzhiyun 	ret = mccic_register(mcam);
250*4882a593Smuzhiyun 	if (ret)
251*4882a593Smuzhiyun 		return ret;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	/*
254*4882a593Smuzhiyun 	 * Add OF clock provider.
255*4882a593Smuzhiyun 	 */
256*4882a593Smuzhiyun 	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
257*4882a593Smuzhiyun 								mcam->mclk);
258*4882a593Smuzhiyun 	if (ret) {
259*4882a593Smuzhiyun 		dev_err(&pdev->dev, "can't add DT clock provider\n");
260*4882a593Smuzhiyun 		goto out;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	/*
264*4882a593Smuzhiyun 	 * Finally, set up our IRQ now that the core is ready to
265*4882a593Smuzhiyun 	 * deal with it.
266*4882a593Smuzhiyun 	 */
267*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
268*4882a593Smuzhiyun 	if (res == NULL) {
269*4882a593Smuzhiyun 		ret = -ENODEV;
270*4882a593Smuzhiyun 		goto out;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 	cam->irq = res->start;
273*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, cam->irq, mmpcam_irq, IRQF_SHARED,
274*4882a593Smuzhiyun 					"mmp-camera", mcam);
275*4882a593Smuzhiyun 	if (ret)
276*4882a593Smuzhiyun 		goto out;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
279*4882a593Smuzhiyun 	return 0;
280*4882a593Smuzhiyun out:
281*4882a593Smuzhiyun 	fwnode_handle_put(mcam->asd.match.fwnode);
282*4882a593Smuzhiyun 	mccic_shutdown(mcam);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	return ret;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 
mmpcam_remove(struct mmp_camera * cam)288*4882a593Smuzhiyun static int mmpcam_remove(struct mmp_camera *cam)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	struct mcam_camera *mcam = &cam->mcam;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	mccic_shutdown(mcam);
293*4882a593Smuzhiyun 	pm_runtime_force_suspend(mcam->dev);
294*4882a593Smuzhiyun 	return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
mmpcam_platform_remove(struct platform_device * pdev)297*4882a593Smuzhiyun static int mmpcam_platform_remove(struct platform_device *pdev)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun 	struct mmp_camera *cam = platform_get_drvdata(pdev);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	if (cam == NULL)
302*4882a593Smuzhiyun 		return -ENODEV;
303*4882a593Smuzhiyun 	return mmpcam_remove(cam);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun /*
307*4882a593Smuzhiyun  * Suspend/resume support.
308*4882a593Smuzhiyun  */
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun #ifdef CONFIG_PM
mmpcam_runtime_resume(struct device * dev)311*4882a593Smuzhiyun static int mmpcam_runtime_resume(struct device *dev)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun 	struct mmp_camera *cam = dev_get_drvdata(dev);
314*4882a593Smuzhiyun 	struct mcam_camera *mcam = &cam->mcam;
315*4882a593Smuzhiyun 	unsigned int i;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	for (i = 0; i < NR_MCAM_CLK; i++) {
318*4882a593Smuzhiyun 		if (!IS_ERR(mcam->clk[i]))
319*4882a593Smuzhiyun 			clk_prepare_enable(mcam->clk[i]);
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun 
mmpcam_runtime_suspend(struct device * dev)325*4882a593Smuzhiyun static int mmpcam_runtime_suspend(struct device *dev)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun 	struct mmp_camera *cam = dev_get_drvdata(dev);
328*4882a593Smuzhiyun 	struct mcam_camera *mcam = &cam->mcam;
329*4882a593Smuzhiyun 	int i;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	for (i = NR_MCAM_CLK - 1; i >= 0; i--) {
332*4882a593Smuzhiyun 		if (!IS_ERR(mcam->clk[i]))
333*4882a593Smuzhiyun 			clk_disable_unprepare(mcam->clk[i]);
334*4882a593Smuzhiyun 	}
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	return 0;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
mmpcam_suspend(struct device * dev)339*4882a593Smuzhiyun static int __maybe_unused mmpcam_suspend(struct device *dev)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	struct mmp_camera *cam = dev_get_drvdata(dev);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	if (!pm_runtime_suspended(dev))
344*4882a593Smuzhiyun 		mccic_suspend(&cam->mcam);
345*4882a593Smuzhiyun 	return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
mmpcam_resume(struct device * dev)348*4882a593Smuzhiyun static int __maybe_unused mmpcam_resume(struct device *dev)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun 	struct mmp_camera *cam = dev_get_drvdata(dev);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	if (!pm_runtime_suspended(dev))
353*4882a593Smuzhiyun 		return mccic_resume(&cam->mcam);
354*4882a593Smuzhiyun 	return 0;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun #endif
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun static const struct dev_pm_ops mmpcam_pm_ops = {
359*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(mmpcam_runtime_suspend, mmpcam_runtime_resume, NULL)
360*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(mmpcam_suspend, mmpcam_resume)
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun static const struct of_device_id mmpcam_of_match[] = {
364*4882a593Smuzhiyun 	{ .compatible = "marvell,mmp2-ccic", },
365*4882a593Smuzhiyun 	{},
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mmpcam_of_match);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun static struct platform_driver mmpcam_driver = {
370*4882a593Smuzhiyun 	.probe		= mmpcam_probe,
371*4882a593Smuzhiyun 	.remove		= mmpcam_platform_remove,
372*4882a593Smuzhiyun 	.driver = {
373*4882a593Smuzhiyun 		.name	= "mmp-camera",
374*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(mmpcam_of_match),
375*4882a593Smuzhiyun 		.pm = &mmpcam_pm_ops,
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun module_platform_driver(mmpcam_driver);
380