1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef FIMC_LITE_H_
7*4882a593Smuzhiyun #define FIMC_LITE_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/sizes.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/irqreturn.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/sched.h>
14*4882a593Smuzhiyun #include <linux/spinlock.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <linux/videodev2.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <media/media-entity.h>
19*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
20*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
21*4882a593Smuzhiyun #include <media/v4l2-device.h>
22*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
23*4882a593Smuzhiyun #include <media/drv-intf/exynos-fimc.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define FIMC_LITE_DRV_NAME "exynos-fimc-lite"
26*4882a593Smuzhiyun #define FLITE_CLK_NAME "flite"
27*4882a593Smuzhiyun #define FIMC_LITE_MAX_DEVS 3
28*4882a593Smuzhiyun #define FLITE_REQ_BUFS_MIN 2
29*4882a593Smuzhiyun #define FLITE_DEFAULT_WIDTH 640
30*4882a593Smuzhiyun #define FLITE_DEFAULT_HEIGHT 480
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Bit index definitions for struct fimc_lite::state */
33*4882a593Smuzhiyun enum {
34*4882a593Smuzhiyun ST_FLITE_LPM,
35*4882a593Smuzhiyun ST_FLITE_PENDING,
36*4882a593Smuzhiyun ST_FLITE_RUN,
37*4882a593Smuzhiyun ST_FLITE_STREAM,
38*4882a593Smuzhiyun ST_FLITE_SUSPENDED,
39*4882a593Smuzhiyun ST_FLITE_OFF,
40*4882a593Smuzhiyun ST_FLITE_IN_USE,
41*4882a593Smuzhiyun ST_FLITE_CONFIG,
42*4882a593Smuzhiyun ST_SENSOR_STREAM,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define FLITE_SD_PAD_SINK 0
46*4882a593Smuzhiyun #define FLITE_SD_PAD_SOURCE_DMA 1
47*4882a593Smuzhiyun #define FLITE_SD_PAD_SOURCE_ISP 2
48*4882a593Smuzhiyun #define FLITE_SD_PADS_NUM 3
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /**
51*4882a593Smuzhiyun * struct flite_drvdata - FIMC-LITE IP variant data structure
52*4882a593Smuzhiyun * @max_width: maximum camera interface input width in pixels
53*4882a593Smuzhiyun * @max_height: maximum camera interface input height in pixels
54*4882a593Smuzhiyun * @out_width_align: minimum output width alignment in pixels
55*4882a593Smuzhiyun * @win_hor_offs_align: minimum camera interface crop window horizontal
56*4882a593Smuzhiyun * offset alignment in pixels
57*4882a593Smuzhiyun * @out_hor_offs_align: minimum output DMA compose rectangle horizontal
58*4882a593Smuzhiyun * offset alignment in pixels
59*4882a593Smuzhiyun * @max_dma_bufs: number of output DMA buffer start address registers
60*4882a593Smuzhiyun * @num_instances: total number of FIMC-LITE IP instances available
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun struct flite_drvdata {
63*4882a593Smuzhiyun unsigned short max_width;
64*4882a593Smuzhiyun unsigned short max_height;
65*4882a593Smuzhiyun unsigned short out_width_align;
66*4882a593Smuzhiyun unsigned short win_hor_offs_align;
67*4882a593Smuzhiyun unsigned short out_hor_offs_align;
68*4882a593Smuzhiyun unsigned short max_dma_bufs;
69*4882a593Smuzhiyun unsigned short num_instances;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct fimc_lite_events {
73*4882a593Smuzhiyun unsigned int data_overflow;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define FLITE_MAX_PLANES 1
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun * struct flite_frame - source/target frame properties
80*4882a593Smuzhiyun * @f_width: full pixel width
81*4882a593Smuzhiyun * @f_height: full pixel height
82*4882a593Smuzhiyun * @rect: crop/composition rectangle
83*4882a593Smuzhiyun * @fmt: pointer to pixel format description data structure
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun struct flite_frame {
86*4882a593Smuzhiyun u16 f_width;
87*4882a593Smuzhiyun u16 f_height;
88*4882a593Smuzhiyun struct v4l2_rect rect;
89*4882a593Smuzhiyun const struct fimc_fmt *fmt;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /**
93*4882a593Smuzhiyun * struct flite_buffer - video buffer structure
94*4882a593Smuzhiyun * @vb: vb2 buffer
95*4882a593Smuzhiyun * @list: list head for the buffers queue
96*4882a593Smuzhiyun * @paddr: DMA buffer start address
97*4882a593Smuzhiyun * @index: DMA start address register's index
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun struct flite_buffer {
100*4882a593Smuzhiyun struct vb2_v4l2_buffer vb;
101*4882a593Smuzhiyun struct list_head list;
102*4882a593Smuzhiyun dma_addr_t paddr;
103*4882a593Smuzhiyun unsigned short index;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /**
107*4882a593Smuzhiyun * struct fimc_lite - fimc lite structure
108*4882a593Smuzhiyun * @pdev: pointer to FIMC-LITE platform device
109*4882a593Smuzhiyun * @dd: SoC specific driver data structure
110*4882a593Smuzhiyun * @ve: exynos video device entity structure
111*4882a593Smuzhiyun * @v4l2_dev: pointer to top the level v4l2_device
112*4882a593Smuzhiyun * @fh: v4l2 file handle
113*4882a593Smuzhiyun * @subdev: FIMC-LITE subdev
114*4882a593Smuzhiyun * @vd_pad: media (sink) pad for the capture video node
115*4882a593Smuzhiyun * @subdev_pads: the subdev media pads
116*4882a593Smuzhiyun * @sensor: sensor subdev attached to FIMC-LITE directly or through MIPI-CSIS
117*4882a593Smuzhiyun * @ctrl_handler: v4l2 control handler
118*4882a593Smuzhiyun * @test_pattern: test pattern controls
119*4882a593Smuzhiyun * @index: FIMC-LITE platform device index
120*4882a593Smuzhiyun * @pipeline: video capture pipeline data structure
121*4882a593Smuzhiyun * @pipeline_ops: media pipeline ops for the video node driver
122*4882a593Smuzhiyun * @slock: spinlock protecting this data structure and the hw registers
123*4882a593Smuzhiyun * @lock: mutex serializing video device and the subdev operations
124*4882a593Smuzhiyun * @clock: FIMC-LITE gate clock
125*4882a593Smuzhiyun * @regs: memory mapped io registers
126*4882a593Smuzhiyun * @irq_queue: interrupt handler waitqueue
127*4882a593Smuzhiyun * @payload: image size in bytes (w x h x bpp)
128*4882a593Smuzhiyun * @inp_frame: camera input frame structure
129*4882a593Smuzhiyun * @out_frame: DMA output frame structure
130*4882a593Smuzhiyun * @out_path: output data path (DMA or FIFO)
131*4882a593Smuzhiyun * @source_subdev_grp_id: source subdev group id
132*4882a593Smuzhiyun * @state: driver state flags
133*4882a593Smuzhiyun * @pending_buf_q: pending buffers queue head
134*4882a593Smuzhiyun * @active_buf_q: the queue head of buffers scheduled in hardware
135*4882a593Smuzhiyun * @vb_queue: vb2 buffers queue
136*4882a593Smuzhiyun * @buf_index: helps to keep track of the DMA start address register index
137*4882a593Smuzhiyun * @active_buf_count: number of video buffers scheduled in hardware
138*4882a593Smuzhiyun * @frame_count: the captured frames counter
139*4882a593Smuzhiyun * @reqbufs_count: the number of buffers requested with REQBUFS ioctl
140*4882a593Smuzhiyun */
141*4882a593Smuzhiyun struct fimc_lite {
142*4882a593Smuzhiyun struct platform_device *pdev;
143*4882a593Smuzhiyun struct flite_drvdata *dd;
144*4882a593Smuzhiyun struct exynos_video_entity ve;
145*4882a593Smuzhiyun struct v4l2_device *v4l2_dev;
146*4882a593Smuzhiyun struct v4l2_fh fh;
147*4882a593Smuzhiyun struct v4l2_subdev subdev;
148*4882a593Smuzhiyun struct media_pad vd_pad;
149*4882a593Smuzhiyun struct media_pad subdev_pads[FLITE_SD_PADS_NUM];
150*4882a593Smuzhiyun struct v4l2_subdev *sensor;
151*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
152*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
153*4882a593Smuzhiyun int index;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun struct mutex lock;
156*4882a593Smuzhiyun spinlock_t slock;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun struct clk *clock;
159*4882a593Smuzhiyun void __iomem *regs;
160*4882a593Smuzhiyun wait_queue_head_t irq_queue;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun unsigned long payload[FLITE_MAX_PLANES];
163*4882a593Smuzhiyun struct flite_frame inp_frame;
164*4882a593Smuzhiyun struct flite_frame out_frame;
165*4882a593Smuzhiyun atomic_t out_path;
166*4882a593Smuzhiyun unsigned int source_subdev_grp_id;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun unsigned long state;
169*4882a593Smuzhiyun struct list_head pending_buf_q;
170*4882a593Smuzhiyun struct list_head active_buf_q;
171*4882a593Smuzhiyun struct vb2_queue vb_queue;
172*4882a593Smuzhiyun unsigned short buf_index;
173*4882a593Smuzhiyun unsigned int frame_count;
174*4882a593Smuzhiyun unsigned int reqbufs_count;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun struct fimc_lite_events events;
177*4882a593Smuzhiyun bool streaming;
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
fimc_lite_active(struct fimc_lite * fimc)180*4882a593Smuzhiyun static inline bool fimc_lite_active(struct fimc_lite *fimc)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun unsigned long flags;
183*4882a593Smuzhiyun bool ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun spin_lock_irqsave(&fimc->slock, flags);
186*4882a593Smuzhiyun ret = fimc->state & (1 << ST_FLITE_RUN) ||
187*4882a593Smuzhiyun fimc->state & (1 << ST_FLITE_PENDING);
188*4882a593Smuzhiyun spin_unlock_irqrestore(&fimc->slock, flags);
189*4882a593Smuzhiyun return ret;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
fimc_lite_active_queue_add(struct fimc_lite * dev,struct flite_buffer * buf)192*4882a593Smuzhiyun static inline void fimc_lite_active_queue_add(struct fimc_lite *dev,
193*4882a593Smuzhiyun struct flite_buffer *buf)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun list_add_tail(&buf->list, &dev->active_buf_q);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
fimc_lite_active_queue_pop(struct fimc_lite * dev)198*4882a593Smuzhiyun static inline struct flite_buffer *fimc_lite_active_queue_pop(
199*4882a593Smuzhiyun struct fimc_lite *dev)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct flite_buffer *buf = list_entry(dev->active_buf_q.next,
202*4882a593Smuzhiyun struct flite_buffer, list);
203*4882a593Smuzhiyun list_del(&buf->list);
204*4882a593Smuzhiyun return buf;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
fimc_lite_pending_queue_add(struct fimc_lite * dev,struct flite_buffer * buf)207*4882a593Smuzhiyun static inline void fimc_lite_pending_queue_add(struct fimc_lite *dev,
208*4882a593Smuzhiyun struct flite_buffer *buf)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun list_add_tail(&buf->list, &dev->pending_buf_q);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
fimc_lite_pending_queue_pop(struct fimc_lite * dev)213*4882a593Smuzhiyun static inline struct flite_buffer *fimc_lite_pending_queue_pop(
214*4882a593Smuzhiyun struct fimc_lite *dev)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct flite_buffer *buf = list_entry(dev->pending_buf_q.next,
217*4882a593Smuzhiyun struct flite_buffer, list);
218*4882a593Smuzhiyun list_del(&buf->list);
219*4882a593Smuzhiyun return buf;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #endif /* FIMC_LITE_H_ */
223