xref: /OK3568_Linux_fs/kernel/drivers/media/platform/exynos4-is/fimc-lite.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Samsung EXYNOS FIMC-LITE (camera host interface) driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun  * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/bug.h>
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/list.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/of.h>
19*4882a593Smuzhiyun #include <linux/types.h>
20*4882a593Smuzhiyun #include <linux/platform_device.h>
21*4882a593Smuzhiyun #include <linux/pm_runtime.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/videodev2.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <media/v4l2-device.h>
26*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
27*4882a593Smuzhiyun #include <media/v4l2-mem2mem.h>
28*4882a593Smuzhiyun #include <media/v4l2-rect.h>
29*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
30*4882a593Smuzhiyun #include <media/videobuf2-dma-contig.h>
31*4882a593Smuzhiyun #include <media/drv-intf/exynos-fimc.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "common.h"
34*4882a593Smuzhiyun #include "fimc-core.h"
35*4882a593Smuzhiyun #include "fimc-lite.h"
36*4882a593Smuzhiyun #include "fimc-lite-reg.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static int debug;
39*4882a593Smuzhiyun module_param(debug, int, 0644);
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun static const struct fimc_fmt fimc_lite_formats[] = {
42*4882a593Smuzhiyun 	{
43*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_YUYV,
44*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
45*4882a593Smuzhiyun 		.depth		= { 16 },
46*4882a593Smuzhiyun 		.color		= FIMC_FMT_YCBYCR422,
47*4882a593Smuzhiyun 		.memplanes	= 1,
48*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
49*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_YUV,
50*4882a593Smuzhiyun 	}, {
51*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_UYVY,
52*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
53*4882a593Smuzhiyun 		.depth		= { 16 },
54*4882a593Smuzhiyun 		.color		= FIMC_FMT_CBYCRY422,
55*4882a593Smuzhiyun 		.memplanes	= 1,
56*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8,
57*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_YUV,
58*4882a593Smuzhiyun 	}, {
59*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_VYUY,
60*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
61*4882a593Smuzhiyun 		.depth		= { 16 },
62*4882a593Smuzhiyun 		.color		= FIMC_FMT_CRYCBY422,
63*4882a593Smuzhiyun 		.memplanes	= 1,
64*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_VYUY8_2X8,
65*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_YUV,
66*4882a593Smuzhiyun 	}, {
67*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_YVYU,
68*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
69*4882a593Smuzhiyun 		.depth		= { 16 },
70*4882a593Smuzhiyun 		.color		= FIMC_FMT_YCRYCB422,
71*4882a593Smuzhiyun 		.memplanes	= 1,
72*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_YVYU8_2X8,
73*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_YUV,
74*4882a593Smuzhiyun 	}, {
75*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG8,
76*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_SRGB,
77*4882a593Smuzhiyun 		.depth		= { 8 },
78*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW8,
79*4882a593Smuzhiyun 		.memplanes	= 1,
80*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
81*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_RAW_BAYER,
82*4882a593Smuzhiyun 	}, {
83*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG10,
84*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_SRGB,
85*4882a593Smuzhiyun 		.depth		= { 16 },
86*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW10,
87*4882a593Smuzhiyun 		.memplanes	= 1,
88*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
89*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_RAW_BAYER,
90*4882a593Smuzhiyun 	}, {
91*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG12,
92*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_SRGB,
93*4882a593Smuzhiyun 		.depth		= { 16 },
94*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW12,
95*4882a593Smuzhiyun 		.memplanes	= 1,
96*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
97*4882a593Smuzhiyun 		.flags		= FMT_FLAGS_RAW_BAYER,
98*4882a593Smuzhiyun 	},
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /**
102*4882a593Smuzhiyun  * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
103*4882a593Smuzhiyun  * @pixelformat: fourcc to match, ignored if null
104*4882a593Smuzhiyun  * @mbus_code: media bus code to match, ignored if null
105*4882a593Smuzhiyun  * @mask: the color format flags to match
106*4882a593Smuzhiyun  * @index: index to the fimc_lite_formats array, ignored if negative
107*4882a593Smuzhiyun  */
fimc_lite_find_format(const u32 * pixelformat,const u32 * mbus_code,unsigned int mask,int index)108*4882a593Smuzhiyun static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
109*4882a593Smuzhiyun 			const u32 *mbus_code, unsigned int mask, int index)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	const struct fimc_fmt *fmt, *def_fmt = NULL;
112*4882a593Smuzhiyun 	unsigned int i;
113*4882a593Smuzhiyun 	int id = 0;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
116*4882a593Smuzhiyun 		return NULL;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
119*4882a593Smuzhiyun 		fmt = &fimc_lite_formats[i];
120*4882a593Smuzhiyun 		if (mask && !(fmt->flags & mask))
121*4882a593Smuzhiyun 			continue;
122*4882a593Smuzhiyun 		if (pixelformat && fmt->fourcc == *pixelformat)
123*4882a593Smuzhiyun 			return fmt;
124*4882a593Smuzhiyun 		if (mbus_code && fmt->mbus_code == *mbus_code)
125*4882a593Smuzhiyun 			return fmt;
126*4882a593Smuzhiyun 		if (index == id)
127*4882a593Smuzhiyun 			def_fmt = fmt;
128*4882a593Smuzhiyun 		id++;
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 	return def_fmt;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
fimc_lite_hw_init(struct fimc_lite * fimc,bool isp_output)133*4882a593Smuzhiyun static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct fimc_source_info *si;
136*4882a593Smuzhiyun 	unsigned long flags;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	if (fimc->sensor == NULL)
139*4882a593Smuzhiyun 		return -ENXIO;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
142*4882a593Smuzhiyun 		return -EINVAL;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/* Get sensor configuration data from the sensor subdev */
145*4882a593Smuzhiyun 	si = v4l2_get_subdev_hostdata(fimc->sensor);
146*4882a593Smuzhiyun 	if (!si)
147*4882a593Smuzhiyun 		return -EINVAL;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	flite_hw_set_camera_bus(fimc, si);
152*4882a593Smuzhiyun 	flite_hw_set_source_format(fimc, &fimc->inp_frame);
153*4882a593Smuzhiyun 	flite_hw_set_window_offset(fimc, &fimc->inp_frame);
154*4882a593Smuzhiyun 	flite_hw_set_dma_buf_mask(fimc, 0);
155*4882a593Smuzhiyun 	flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
156*4882a593Smuzhiyun 	flite_hw_set_interrupt_mask(fimc);
157*4882a593Smuzhiyun 	flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (debug > 0)
160*4882a593Smuzhiyun 		flite_hw_dump_regs(fimc, __func__);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun  * Reinitialize the driver so it is ready to start the streaming again.
168*4882a593Smuzhiyun  * Set fimc->state to indicate stream off and the hardware shut down state.
169*4882a593Smuzhiyun  * If not suspending (@suspend is false), return any buffers to videobuf2.
170*4882a593Smuzhiyun  * Otherwise put any owned buffers onto the pending buffers queue, so they
171*4882a593Smuzhiyun  * can be re-spun when the device is being resumed. Also perform FIMC
172*4882a593Smuzhiyun  * software reset and disable streaming on the whole pipeline if required.
173*4882a593Smuzhiyun  */
fimc_lite_reinit(struct fimc_lite * fimc,bool suspend)174*4882a593Smuzhiyun static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct flite_buffer *buf;
177*4882a593Smuzhiyun 	unsigned long flags;
178*4882a593Smuzhiyun 	bool streaming;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
181*4882a593Smuzhiyun 	streaming = fimc->state & (1 << ST_SENSOR_STREAM);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
184*4882a593Smuzhiyun 			 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
185*4882a593Smuzhiyun 	if (suspend)
186*4882a593Smuzhiyun 		fimc->state |= (1 << ST_FLITE_SUSPENDED);
187*4882a593Smuzhiyun 	else
188*4882a593Smuzhiyun 		fimc->state &= ~(1 << ST_FLITE_PENDING |
189*4882a593Smuzhiyun 				 1 << ST_FLITE_SUSPENDED);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/* Release unused buffers */
192*4882a593Smuzhiyun 	while (!suspend && !list_empty(&fimc->pending_buf_q)) {
193*4882a593Smuzhiyun 		buf = fimc_lite_pending_queue_pop(fimc);
194*4882a593Smuzhiyun 		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
195*4882a593Smuzhiyun 	}
196*4882a593Smuzhiyun 	/* If suspending put unused buffers onto pending queue */
197*4882a593Smuzhiyun 	while (!list_empty(&fimc->active_buf_q)) {
198*4882a593Smuzhiyun 		buf = fimc_lite_active_queue_pop(fimc);
199*4882a593Smuzhiyun 		if (suspend)
200*4882a593Smuzhiyun 			fimc_lite_pending_queue_add(fimc, buf);
201*4882a593Smuzhiyun 		else
202*4882a593Smuzhiyun 			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	flite_hw_reset(fimc);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	if (!streaming)
210*4882a593Smuzhiyun 		return 0;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	return fimc_pipeline_call(&fimc->ve, set_stream, 0);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
fimc_lite_stop_capture(struct fimc_lite * fimc,bool suspend)215*4882a593Smuzhiyun static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun 	unsigned long flags;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	if (!fimc_lite_active(fimc))
220*4882a593Smuzhiyun 		return 0;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
223*4882a593Smuzhiyun 	set_bit(ST_FLITE_OFF, &fimc->state);
224*4882a593Smuzhiyun 	flite_hw_capture_stop(fimc);
225*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	wait_event_timeout(fimc->irq_queue,
228*4882a593Smuzhiyun 			   !test_bit(ST_FLITE_OFF, &fimc->state),
229*4882a593Smuzhiyun 			   (2*HZ/10)); /* 200 ms */
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return fimc_lite_reinit(fimc, suspend);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* Must be called  with fimc.slock spinlock held. */
fimc_lite_config_update(struct fimc_lite * fimc)235*4882a593Smuzhiyun static void fimc_lite_config_update(struct fimc_lite *fimc)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	flite_hw_set_window_offset(fimc, &fimc->inp_frame);
238*4882a593Smuzhiyun 	flite_hw_set_dma_window(fimc, &fimc->out_frame);
239*4882a593Smuzhiyun 	flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
240*4882a593Smuzhiyun 	clear_bit(ST_FLITE_CONFIG, &fimc->state);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
flite_irq_handler(int irq,void * priv)243*4882a593Smuzhiyun static irqreturn_t flite_irq_handler(int irq, void *priv)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun 	struct fimc_lite *fimc = priv;
246*4882a593Smuzhiyun 	struct flite_buffer *vbuf;
247*4882a593Smuzhiyun 	unsigned long flags;
248*4882a593Smuzhiyun 	u32 intsrc;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	intsrc = flite_hw_get_interrupt_source(fimc);
253*4882a593Smuzhiyun 	flite_hw_clear_pending_irq(fimc);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
256*4882a593Smuzhiyun 		wake_up(&fimc->irq_queue);
257*4882a593Smuzhiyun 		goto done;
258*4882a593Smuzhiyun 	}
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
261*4882a593Smuzhiyun 		clear_bit(ST_FLITE_RUN, &fimc->state);
262*4882a593Smuzhiyun 		fimc->events.data_overflow++;
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
266*4882a593Smuzhiyun 		flite_hw_clear_last_capture_end(fimc);
267*4882a593Smuzhiyun 		clear_bit(ST_FLITE_STREAM, &fimc->state);
268*4882a593Smuzhiyun 		wake_up(&fimc->irq_queue);
269*4882a593Smuzhiyun 	}
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
272*4882a593Smuzhiyun 		goto done;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
275*4882a593Smuzhiyun 	    test_bit(ST_FLITE_RUN, &fimc->state) &&
276*4882a593Smuzhiyun 	    !list_empty(&fimc->pending_buf_q)) {
277*4882a593Smuzhiyun 		vbuf = fimc_lite_pending_queue_pop(fimc);
278*4882a593Smuzhiyun 		flite_hw_set_dma_buffer(fimc, vbuf);
279*4882a593Smuzhiyun 		fimc_lite_active_queue_add(fimc, vbuf);
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMEND) &&
283*4882a593Smuzhiyun 	    test_bit(ST_FLITE_RUN, &fimc->state) &&
284*4882a593Smuzhiyun 	    !list_empty(&fimc->active_buf_q)) {
285*4882a593Smuzhiyun 		vbuf = fimc_lite_active_queue_pop(fimc);
286*4882a593Smuzhiyun 		vbuf->vb.vb2_buf.timestamp = ktime_get_ns();
287*4882a593Smuzhiyun 		vbuf->vb.sequence = fimc->frame_count++;
288*4882a593Smuzhiyun 		flite_hw_mask_dma_buffer(fimc, vbuf->index);
289*4882a593Smuzhiyun 		vb2_buffer_done(&vbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
290*4882a593Smuzhiyun 	}
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	if (test_bit(ST_FLITE_CONFIG, &fimc->state))
293*4882a593Smuzhiyun 		fimc_lite_config_update(fimc);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if (list_empty(&fimc->pending_buf_q)) {
296*4882a593Smuzhiyun 		flite_hw_capture_stop(fimc);
297*4882a593Smuzhiyun 		clear_bit(ST_FLITE_STREAM, &fimc->state);
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun done:
300*4882a593Smuzhiyun 	set_bit(ST_FLITE_RUN, &fimc->state);
301*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
302*4882a593Smuzhiyun 	return IRQ_HANDLED;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
start_streaming(struct vb2_queue * q,unsigned int count)305*4882a593Smuzhiyun static int start_streaming(struct vb2_queue *q, unsigned int count)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct fimc_lite *fimc = q->drv_priv;
308*4882a593Smuzhiyun 	unsigned long flags;
309*4882a593Smuzhiyun 	int ret;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	fimc->buf_index = 0;
314*4882a593Smuzhiyun 	fimc->frame_count = 0;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	ret = fimc_lite_hw_init(fimc, false);
319*4882a593Smuzhiyun 	if (ret) {
320*4882a593Smuzhiyun 		fimc_lite_reinit(fimc, false);
321*4882a593Smuzhiyun 		return ret;
322*4882a593Smuzhiyun 	}
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	set_bit(ST_FLITE_PENDING, &fimc->state);
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	if (!list_empty(&fimc->active_buf_q) &&
327*4882a593Smuzhiyun 	    !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
328*4882a593Smuzhiyun 		flite_hw_capture_start(fimc);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 		if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
331*4882a593Smuzhiyun 			fimc_pipeline_call(&fimc->ve, set_stream, 1);
332*4882a593Smuzhiyun 	}
333*4882a593Smuzhiyun 	if (debug > 0)
334*4882a593Smuzhiyun 		flite_hw_dump_regs(fimc, __func__);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	return 0;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
stop_streaming(struct vb2_queue * q)339*4882a593Smuzhiyun static void stop_streaming(struct vb2_queue *q)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	struct fimc_lite *fimc = q->drv_priv;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	if (!fimc_lite_active(fimc))
344*4882a593Smuzhiyun 		return;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	fimc_lite_stop_capture(fimc, false);
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
queue_setup(struct vb2_queue * vq,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])349*4882a593Smuzhiyun static int queue_setup(struct vb2_queue *vq,
350*4882a593Smuzhiyun 		       unsigned int *num_buffers, unsigned int *num_planes,
351*4882a593Smuzhiyun 		       unsigned int sizes[], struct device *alloc_devs[])
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct fimc_lite *fimc = vq->drv_priv;
354*4882a593Smuzhiyun 	struct flite_frame *frame = &fimc->out_frame;
355*4882a593Smuzhiyun 	const struct fimc_fmt *fmt = frame->fmt;
356*4882a593Smuzhiyun 	unsigned long wh = frame->f_width * frame->f_height;
357*4882a593Smuzhiyun 	int i;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	if (fmt == NULL)
360*4882a593Smuzhiyun 		return -EINVAL;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (*num_planes) {
363*4882a593Smuzhiyun 		if (*num_planes != fmt->memplanes)
364*4882a593Smuzhiyun 			return -EINVAL;
365*4882a593Smuzhiyun 		for (i = 0; i < *num_planes; i++)
366*4882a593Smuzhiyun 			if (sizes[i] < (wh * fmt->depth[i]) / 8)
367*4882a593Smuzhiyun 				return -EINVAL;
368*4882a593Smuzhiyun 		return 0;
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	*num_planes = fmt->memplanes;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	for (i = 0; i < fmt->memplanes; i++)
374*4882a593Smuzhiyun 		sizes[i] = (wh * fmt->depth[i]) / 8;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	return 0;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
buffer_prepare(struct vb2_buffer * vb)379*4882a593Smuzhiyun static int buffer_prepare(struct vb2_buffer *vb)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct vb2_queue *vq = vb->vb2_queue;
382*4882a593Smuzhiyun 	struct fimc_lite *fimc = vq->drv_priv;
383*4882a593Smuzhiyun 	int i;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	if (fimc->out_frame.fmt == NULL)
386*4882a593Smuzhiyun 		return -EINVAL;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) {
389*4882a593Smuzhiyun 		unsigned long size = fimc->payload[i];
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 		if (vb2_plane_size(vb, i) < size) {
392*4882a593Smuzhiyun 			v4l2_err(&fimc->ve.vdev,
393*4882a593Smuzhiyun 				 "User buffer too small (%ld < %ld)\n",
394*4882a593Smuzhiyun 				 vb2_plane_size(vb, i), size);
395*4882a593Smuzhiyun 			return -EINVAL;
396*4882a593Smuzhiyun 		}
397*4882a593Smuzhiyun 		vb2_set_plane_payload(vb, i, size);
398*4882a593Smuzhiyun 	}
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	return 0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
buffer_queue(struct vb2_buffer * vb)403*4882a593Smuzhiyun static void buffer_queue(struct vb2_buffer *vb)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
406*4882a593Smuzhiyun 	struct flite_buffer *buf
407*4882a593Smuzhiyun 		= container_of(vbuf, struct flite_buffer, vb);
408*4882a593Smuzhiyun 	struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
409*4882a593Smuzhiyun 	unsigned long flags;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
412*4882a593Smuzhiyun 	buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	buf->index = fimc->buf_index++;
415*4882a593Smuzhiyun 	if (fimc->buf_index >= fimc->reqbufs_count)
416*4882a593Smuzhiyun 		fimc->buf_index = 0;
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
419*4882a593Smuzhiyun 	    !test_bit(ST_FLITE_STREAM, &fimc->state) &&
420*4882a593Smuzhiyun 	    list_empty(&fimc->active_buf_q)) {
421*4882a593Smuzhiyun 		flite_hw_set_dma_buffer(fimc, buf);
422*4882a593Smuzhiyun 		fimc_lite_active_queue_add(fimc, buf);
423*4882a593Smuzhiyun 	} else {
424*4882a593Smuzhiyun 		fimc_lite_pending_queue_add(fimc, buf);
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	if (vb2_is_streaming(&fimc->vb_queue) &&
428*4882a593Smuzhiyun 	    !list_empty(&fimc->pending_buf_q) &&
429*4882a593Smuzhiyun 	    !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
430*4882a593Smuzhiyun 		flite_hw_capture_start(fimc);
431*4882a593Smuzhiyun 		spin_unlock_irqrestore(&fimc->slock, flags);
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 		if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
434*4882a593Smuzhiyun 			fimc_pipeline_call(&fimc->ve, set_stream, 1);
435*4882a593Smuzhiyun 		return;
436*4882a593Smuzhiyun 	}
437*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static const struct vb2_ops fimc_lite_qops = {
441*4882a593Smuzhiyun 	.queue_setup	 = queue_setup,
442*4882a593Smuzhiyun 	.buf_prepare	 = buffer_prepare,
443*4882a593Smuzhiyun 	.buf_queue	 = buffer_queue,
444*4882a593Smuzhiyun 	.wait_prepare	 = vb2_ops_wait_prepare,
445*4882a593Smuzhiyun 	.wait_finish	 = vb2_ops_wait_finish,
446*4882a593Smuzhiyun 	.start_streaming = start_streaming,
447*4882a593Smuzhiyun 	.stop_streaming	 = stop_streaming,
448*4882a593Smuzhiyun };
449*4882a593Smuzhiyun 
fimc_lite_clear_event_counters(struct fimc_lite * fimc)450*4882a593Smuzhiyun static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	unsigned long flags;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
455*4882a593Smuzhiyun 	memset(&fimc->events, 0, sizeof(fimc->events));
456*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun 
fimc_lite_open(struct file * file)459*4882a593Smuzhiyun static int fimc_lite_open(struct file *file)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
462*4882a593Smuzhiyun 	struct media_entity *me = &fimc->ve.vdev.entity;
463*4882a593Smuzhiyun 	int ret;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
466*4882a593Smuzhiyun 	if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
467*4882a593Smuzhiyun 		ret = -EBUSY;
468*4882a593Smuzhiyun 		goto unlock;
469*4882a593Smuzhiyun 	}
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	set_bit(ST_FLITE_IN_USE, &fimc->state);
472*4882a593Smuzhiyun 	ret = pm_runtime_resume_and_get(&fimc->pdev->dev);
473*4882a593Smuzhiyun 	if (ret < 0)
474*4882a593Smuzhiyun 		goto err_in_use;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	ret = v4l2_fh_open(file);
477*4882a593Smuzhiyun 	if (ret < 0)
478*4882a593Smuzhiyun 		goto err_pm;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	if (!v4l2_fh_is_singular_file(file) ||
481*4882a593Smuzhiyun 	    atomic_read(&fimc->out_path) != FIMC_IO_DMA)
482*4882a593Smuzhiyun 		goto unlock;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	mutex_lock(&me->graph_obj.mdev->graph_mutex);
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	ret = fimc_pipeline_call(&fimc->ve, open, me, true);
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	/* Mark video pipeline ending at this video node as in use. */
489*4882a593Smuzhiyun 	if (ret == 0)
490*4882a593Smuzhiyun 		me->use_count++;
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	mutex_unlock(&me->graph_obj.mdev->graph_mutex);
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	if (!ret) {
495*4882a593Smuzhiyun 		fimc_lite_clear_event_counters(fimc);
496*4882a593Smuzhiyun 		goto unlock;
497*4882a593Smuzhiyun 	}
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	v4l2_fh_release(file);
500*4882a593Smuzhiyun err_pm:
501*4882a593Smuzhiyun 	pm_runtime_put_sync(&fimc->pdev->dev);
502*4882a593Smuzhiyun err_in_use:
503*4882a593Smuzhiyun 	clear_bit(ST_FLITE_IN_USE, &fimc->state);
504*4882a593Smuzhiyun unlock:
505*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
506*4882a593Smuzhiyun 	return ret;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun 
fimc_lite_release(struct file * file)509*4882a593Smuzhiyun static int fimc_lite_release(struct file *file)
510*4882a593Smuzhiyun {
511*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
512*4882a593Smuzhiyun 	struct media_entity *entity = &fimc->ve.vdev.entity;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	if (v4l2_fh_is_singular_file(file) &&
517*4882a593Smuzhiyun 	    atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
518*4882a593Smuzhiyun 		if (fimc->streaming) {
519*4882a593Smuzhiyun 			media_pipeline_stop(entity);
520*4882a593Smuzhiyun 			fimc->streaming = false;
521*4882a593Smuzhiyun 		}
522*4882a593Smuzhiyun 		fimc_lite_stop_capture(fimc, false);
523*4882a593Smuzhiyun 		fimc_pipeline_call(&fimc->ve, close);
524*4882a593Smuzhiyun 		clear_bit(ST_FLITE_IN_USE, &fimc->state);
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 		mutex_lock(&entity->graph_obj.mdev->graph_mutex);
527*4882a593Smuzhiyun 		entity->use_count--;
528*4882a593Smuzhiyun 		mutex_unlock(&entity->graph_obj.mdev->graph_mutex);
529*4882a593Smuzhiyun 	}
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	_vb2_fop_release(file, NULL);
532*4882a593Smuzhiyun 	pm_runtime_put(&fimc->pdev->dev);
533*4882a593Smuzhiyun 	clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
536*4882a593Smuzhiyun 	return 0;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun static const struct v4l2_file_operations fimc_lite_fops = {
540*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
541*4882a593Smuzhiyun 	.open		= fimc_lite_open,
542*4882a593Smuzhiyun 	.release	= fimc_lite_release,
543*4882a593Smuzhiyun 	.poll		= vb2_fop_poll,
544*4882a593Smuzhiyun 	.unlocked_ioctl	= video_ioctl2,
545*4882a593Smuzhiyun 	.mmap		= vb2_fop_mmap,
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun /*
549*4882a593Smuzhiyun  * Format and crop negotiation helpers
550*4882a593Smuzhiyun  */
551*4882a593Smuzhiyun 
fimc_lite_subdev_try_fmt(struct fimc_lite * fimc,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)552*4882a593Smuzhiyun static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc,
553*4882a593Smuzhiyun 					struct v4l2_subdev_pad_config *cfg,
554*4882a593Smuzhiyun 					struct v4l2_subdev_format *format)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	struct flite_drvdata *dd = fimc->dd;
557*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format->format;
558*4882a593Smuzhiyun 	const struct fimc_fmt *fmt = NULL;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	if (format->pad == FLITE_SD_PAD_SINK) {
561*4882a593Smuzhiyun 		v4l_bound_align_image(&mf->width, 8, dd->max_width,
562*4882a593Smuzhiyun 				ffs(dd->out_width_align) - 1,
563*4882a593Smuzhiyun 				&mf->height, 0, dd->max_height, 0, 0);
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 		fmt = fimc_lite_find_format(NULL, &mf->code, 0, 0);
566*4882a593Smuzhiyun 		if (WARN_ON(!fmt))
567*4882a593Smuzhiyun 			return NULL;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 		mf->colorspace = fmt->colorspace;
570*4882a593Smuzhiyun 		mf->code = fmt->mbus_code;
571*4882a593Smuzhiyun 	} else {
572*4882a593Smuzhiyun 		struct flite_frame *sink = &fimc->inp_frame;
573*4882a593Smuzhiyun 		struct v4l2_mbus_framefmt *sink_fmt;
574*4882a593Smuzhiyun 		struct v4l2_rect *rect;
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 		if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
577*4882a593Smuzhiyun 			sink_fmt = v4l2_subdev_get_try_format(&fimc->subdev, cfg,
578*4882a593Smuzhiyun 						FLITE_SD_PAD_SINK);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 			mf->code = sink_fmt->code;
581*4882a593Smuzhiyun 			mf->colorspace = sink_fmt->colorspace;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 			rect = v4l2_subdev_get_try_crop(&fimc->subdev, cfg,
584*4882a593Smuzhiyun 						FLITE_SD_PAD_SINK);
585*4882a593Smuzhiyun 		} else {
586*4882a593Smuzhiyun 			mf->code = sink->fmt->mbus_code;
587*4882a593Smuzhiyun 			mf->colorspace = sink->fmt->colorspace;
588*4882a593Smuzhiyun 			rect = &sink->rect;
589*4882a593Smuzhiyun 		}
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 		/* Allow changing format only on sink pad */
592*4882a593Smuzhiyun 		mf->width = rect->width;
593*4882a593Smuzhiyun 		mf->height = rect->height;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	mf->field = V4L2_FIELD_NONE;
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	v4l2_dbg(1, debug, &fimc->subdev, "code: %#x (%d), %dx%d\n",
599*4882a593Smuzhiyun 		 mf->code, mf->colorspace, mf->width, mf->height);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	return fmt;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun 
fimc_lite_try_crop(struct fimc_lite * fimc,struct v4l2_rect * r)604*4882a593Smuzhiyun static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun 	struct flite_frame *frame = &fimc->inp_frame;
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
609*4882a593Smuzhiyun 			      &r->height, 0, frame->f_height, 0, 0);
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	/* Adjust left/top if cropping rectangle got out of bounds */
612*4882a593Smuzhiyun 	r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
613*4882a593Smuzhiyun 	r->left = round_down(r->left, fimc->dd->win_hor_offs_align);
614*4882a593Smuzhiyun 	r->top  = clamp_t(u32, r->top, 0, frame->f_height - r->height);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
617*4882a593Smuzhiyun 		 r->left, r->top, r->width, r->height,
618*4882a593Smuzhiyun 		 frame->f_width, frame->f_height);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
fimc_lite_try_compose(struct fimc_lite * fimc,struct v4l2_rect * r)621*4882a593Smuzhiyun static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun 	struct flite_frame *frame = &fimc->out_frame;
624*4882a593Smuzhiyun 	struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	/* Scaling is not supported so we enforce compose rectangle size
627*4882a593Smuzhiyun 	   same as size of the sink crop rectangle. */
628*4882a593Smuzhiyun 	r->width = crop_rect->width;
629*4882a593Smuzhiyun 	r->height = crop_rect->height;
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/* Adjust left/top if the composing rectangle got out of bounds */
632*4882a593Smuzhiyun 	r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
633*4882a593Smuzhiyun 	r->left = round_down(r->left, fimc->dd->out_hor_offs_align);
634*4882a593Smuzhiyun 	r->top  = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
637*4882a593Smuzhiyun 		 r->left, r->top, r->width, r->height,
638*4882a593Smuzhiyun 		 frame->f_width, frame->f_height);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun /*
642*4882a593Smuzhiyun  * Video node ioctl operations
643*4882a593Smuzhiyun  */
fimc_lite_querycap(struct file * file,void * priv,struct v4l2_capability * cap)644*4882a593Smuzhiyun static int fimc_lite_querycap(struct file *file, void *priv,
645*4882a593Smuzhiyun 					struct v4l2_capability *cap)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	strscpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
650*4882a593Smuzhiyun 	strscpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card));
651*4882a593Smuzhiyun 	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
652*4882a593Smuzhiyun 					dev_name(&fimc->pdev->dev));
653*4882a593Smuzhiyun 	return 0;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
fimc_lite_enum_fmt(struct file * file,void * priv,struct v4l2_fmtdesc * f)656*4882a593Smuzhiyun static int fimc_lite_enum_fmt(struct file *file, void *priv,
657*4882a593Smuzhiyun 			      struct v4l2_fmtdesc *f)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun 	const struct fimc_fmt *fmt;
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (f->index >= ARRAY_SIZE(fimc_lite_formats))
662*4882a593Smuzhiyun 		return -EINVAL;
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	fmt = &fimc_lite_formats[f->index];
665*4882a593Smuzhiyun 	f->pixelformat = fmt->fourcc;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	return 0;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
fimc_lite_g_fmt_mplane(struct file * file,void * fh,struct v4l2_format * f)670*4882a593Smuzhiyun static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
671*4882a593Smuzhiyun 				  struct v4l2_format *f)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
674*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
675*4882a593Smuzhiyun 	struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
676*4882a593Smuzhiyun 	struct flite_frame *frame = &fimc->out_frame;
677*4882a593Smuzhiyun 	const struct fimc_fmt *fmt = frame->fmt;
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
680*4882a593Smuzhiyun 	plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	pixm->num_planes = fmt->memplanes;
683*4882a593Smuzhiyun 	pixm->pixelformat = fmt->fourcc;
684*4882a593Smuzhiyun 	pixm->width = frame->f_width;
685*4882a593Smuzhiyun 	pixm->height = frame->f_height;
686*4882a593Smuzhiyun 	pixm->field = V4L2_FIELD_NONE;
687*4882a593Smuzhiyun 	pixm->colorspace = fmt->colorspace;
688*4882a593Smuzhiyun 	return 0;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
fimc_lite_try_fmt(struct fimc_lite * fimc,struct v4l2_pix_format_mplane * pixm,const struct fimc_fmt ** ffmt)691*4882a593Smuzhiyun static int fimc_lite_try_fmt(struct fimc_lite *fimc,
692*4882a593Smuzhiyun 			     struct v4l2_pix_format_mplane *pixm,
693*4882a593Smuzhiyun 			     const struct fimc_fmt **ffmt)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun 	u32 bpl = pixm->plane_fmt[0].bytesperline;
696*4882a593Smuzhiyun 	struct flite_drvdata *dd = fimc->dd;
697*4882a593Smuzhiyun 	const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt;
698*4882a593Smuzhiyun 	const struct fimc_fmt *fmt;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	if (WARN_ON(inp_fmt == NULL))
701*4882a593Smuzhiyun 		return -EINVAL;
702*4882a593Smuzhiyun 	/*
703*4882a593Smuzhiyun 	 * We allow some flexibility only for YUV formats. In case of raw
704*4882a593Smuzhiyun 	 * raw Bayer the FIMC-LITE's output format must match its camera
705*4882a593Smuzhiyun 	 * interface input format.
706*4882a593Smuzhiyun 	 */
707*4882a593Smuzhiyun 	if (inp_fmt->flags & FMT_FLAGS_YUV)
708*4882a593Smuzhiyun 		fmt = fimc_lite_find_format(&pixm->pixelformat, NULL,
709*4882a593Smuzhiyun 						inp_fmt->flags, 0);
710*4882a593Smuzhiyun 	else
711*4882a593Smuzhiyun 		fmt = inp_fmt;
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	if (WARN_ON(fmt == NULL))
714*4882a593Smuzhiyun 		return -EINVAL;
715*4882a593Smuzhiyun 	if (ffmt)
716*4882a593Smuzhiyun 		*ffmt = fmt;
717*4882a593Smuzhiyun 	v4l_bound_align_image(&pixm->width, 8, dd->max_width,
718*4882a593Smuzhiyun 			      ffs(dd->out_width_align) - 1,
719*4882a593Smuzhiyun 			      &pixm->height, 0, dd->max_height, 0, 0);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
722*4882a593Smuzhiyun 		pixm->plane_fmt[0].bytesperline = (pixm->width *
723*4882a593Smuzhiyun 						   fmt->depth[0]) / 8;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	if (pixm->plane_fmt[0].sizeimage == 0)
726*4882a593Smuzhiyun 		pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
727*4882a593Smuzhiyun 						fmt->depth[0]) / 8;
728*4882a593Smuzhiyun 	pixm->num_planes = fmt->memplanes;
729*4882a593Smuzhiyun 	pixm->pixelformat = fmt->fourcc;
730*4882a593Smuzhiyun 	pixm->colorspace = fmt->colorspace;
731*4882a593Smuzhiyun 	pixm->field = V4L2_FIELD_NONE;
732*4882a593Smuzhiyun 	return 0;
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun 
fimc_lite_try_fmt_mplane(struct file * file,void * fh,struct v4l2_format * f)735*4882a593Smuzhiyun static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
736*4882a593Smuzhiyun 				    struct v4l2_format *f)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
739*4882a593Smuzhiyun 	return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun 
fimc_lite_s_fmt_mplane(struct file * file,void * priv,struct v4l2_format * f)742*4882a593Smuzhiyun static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
743*4882a593Smuzhiyun 				  struct v4l2_format *f)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun 	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
746*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
747*4882a593Smuzhiyun 	struct flite_frame *frame = &fimc->out_frame;
748*4882a593Smuzhiyun 	const struct fimc_fmt *fmt = NULL;
749*4882a593Smuzhiyun 	int ret;
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	if (vb2_is_busy(&fimc->vb_queue))
752*4882a593Smuzhiyun 		return -EBUSY;
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
755*4882a593Smuzhiyun 	if (ret < 0)
756*4882a593Smuzhiyun 		return ret;
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	frame->fmt = fmt;
759*4882a593Smuzhiyun 	fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
760*4882a593Smuzhiyun 			       pixm->plane_fmt[0].sizeimage);
761*4882a593Smuzhiyun 	frame->f_width = pixm->width;
762*4882a593Smuzhiyun 	frame->f_height = pixm->height;
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun 	return 0;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun 
fimc_pipeline_validate(struct fimc_lite * fimc)767*4882a593Smuzhiyun static int fimc_pipeline_validate(struct fimc_lite *fimc)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &fimc->subdev;
770*4882a593Smuzhiyun 	struct v4l2_subdev_format sink_fmt, src_fmt;
771*4882a593Smuzhiyun 	struct media_pad *pad;
772*4882a593Smuzhiyun 	int ret;
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	while (1) {
775*4882a593Smuzhiyun 		/* Retrieve format at the sink pad */
776*4882a593Smuzhiyun 		pad = &sd->entity.pads[0];
777*4882a593Smuzhiyun 		if (!(pad->flags & MEDIA_PAD_FL_SINK))
778*4882a593Smuzhiyun 			break;
779*4882a593Smuzhiyun 		/* Don't call FIMC subdev operation to avoid nested locking */
780*4882a593Smuzhiyun 		if (sd == &fimc->subdev) {
781*4882a593Smuzhiyun 			struct flite_frame *ff = &fimc->out_frame;
782*4882a593Smuzhiyun 			sink_fmt.format.width = ff->f_width;
783*4882a593Smuzhiyun 			sink_fmt.format.height = ff->f_height;
784*4882a593Smuzhiyun 			sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code;
785*4882a593Smuzhiyun 		} else {
786*4882a593Smuzhiyun 			sink_fmt.pad = pad->index;
787*4882a593Smuzhiyun 			sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
788*4882a593Smuzhiyun 			ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
789*4882a593Smuzhiyun 					       &sink_fmt);
790*4882a593Smuzhiyun 			if (ret < 0 && ret != -ENOIOCTLCMD)
791*4882a593Smuzhiyun 				return -EPIPE;
792*4882a593Smuzhiyun 		}
793*4882a593Smuzhiyun 		/* Retrieve format at the source pad */
794*4882a593Smuzhiyun 		pad = media_entity_remote_pad(pad);
795*4882a593Smuzhiyun 		if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
796*4882a593Smuzhiyun 			break;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 		sd = media_entity_to_v4l2_subdev(pad->entity);
799*4882a593Smuzhiyun 		src_fmt.pad = pad->index;
800*4882a593Smuzhiyun 		src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
801*4882a593Smuzhiyun 		ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
802*4882a593Smuzhiyun 		if (ret < 0 && ret != -ENOIOCTLCMD)
803*4882a593Smuzhiyun 			return -EPIPE;
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 		if (src_fmt.format.width != sink_fmt.format.width ||
806*4882a593Smuzhiyun 		    src_fmt.format.height != sink_fmt.format.height ||
807*4882a593Smuzhiyun 		    src_fmt.format.code != sink_fmt.format.code)
808*4882a593Smuzhiyun 			return -EPIPE;
809*4882a593Smuzhiyun 	}
810*4882a593Smuzhiyun 	return 0;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun 
fimc_lite_streamon(struct file * file,void * priv,enum v4l2_buf_type type)813*4882a593Smuzhiyun static int fimc_lite_streamon(struct file *file, void *priv,
814*4882a593Smuzhiyun 			      enum v4l2_buf_type type)
815*4882a593Smuzhiyun {
816*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
817*4882a593Smuzhiyun 	struct media_entity *entity = &fimc->ve.vdev.entity;
818*4882a593Smuzhiyun 	int ret;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	if (fimc_lite_active(fimc))
821*4882a593Smuzhiyun 		return -EBUSY;
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun 	ret = media_pipeline_start(entity, &fimc->ve.pipe->mp);
824*4882a593Smuzhiyun 	if (ret < 0)
825*4882a593Smuzhiyun 		return ret;
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun 	ret = fimc_pipeline_validate(fimc);
828*4882a593Smuzhiyun 	if (ret < 0)
829*4882a593Smuzhiyun 		goto err_p_stop;
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	fimc->sensor = fimc_find_remote_sensor(&fimc->subdev.entity);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	ret = vb2_ioctl_streamon(file, priv, type);
834*4882a593Smuzhiyun 	if (!ret) {
835*4882a593Smuzhiyun 		fimc->streaming = true;
836*4882a593Smuzhiyun 		return ret;
837*4882a593Smuzhiyun 	}
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun err_p_stop:
840*4882a593Smuzhiyun 	media_pipeline_stop(entity);
841*4882a593Smuzhiyun 	return 0;
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun 
fimc_lite_streamoff(struct file * file,void * priv,enum v4l2_buf_type type)844*4882a593Smuzhiyun static int fimc_lite_streamoff(struct file *file, void *priv,
845*4882a593Smuzhiyun 			       enum v4l2_buf_type type)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
848*4882a593Smuzhiyun 	int ret;
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	ret = vb2_ioctl_streamoff(file, priv, type);
851*4882a593Smuzhiyun 	if (ret < 0)
852*4882a593Smuzhiyun 		return ret;
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun 	media_pipeline_stop(&fimc->ve.vdev.entity);
855*4882a593Smuzhiyun 	fimc->streaming = false;
856*4882a593Smuzhiyun 	return 0;
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun 
fimc_lite_reqbufs(struct file * file,void * priv,struct v4l2_requestbuffers * reqbufs)859*4882a593Smuzhiyun static int fimc_lite_reqbufs(struct file *file, void *priv,
860*4882a593Smuzhiyun 			     struct v4l2_requestbuffers *reqbufs)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
863*4882a593Smuzhiyun 	int ret;
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
866*4882a593Smuzhiyun 	ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
867*4882a593Smuzhiyun 	if (!ret)
868*4882a593Smuzhiyun 		fimc->reqbufs_count = reqbufs->count;
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	return ret;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun 
fimc_lite_g_selection(struct file * file,void * fh,struct v4l2_selection * sel)873*4882a593Smuzhiyun static int fimc_lite_g_selection(struct file *file, void *fh,
874*4882a593Smuzhiyun 				 struct v4l2_selection *sel)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
877*4882a593Smuzhiyun 	struct flite_frame *f = &fimc->out_frame;
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
880*4882a593Smuzhiyun 		return -EINVAL;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	switch (sel->target) {
883*4882a593Smuzhiyun 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
884*4882a593Smuzhiyun 	case V4L2_SEL_TGT_COMPOSE_DEFAULT:
885*4882a593Smuzhiyun 		sel->r.left = 0;
886*4882a593Smuzhiyun 		sel->r.top = 0;
887*4882a593Smuzhiyun 		sel->r.width = f->f_width;
888*4882a593Smuzhiyun 		sel->r.height = f->f_height;
889*4882a593Smuzhiyun 		return 0;
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	case V4L2_SEL_TGT_COMPOSE:
892*4882a593Smuzhiyun 		sel->r = f->rect;
893*4882a593Smuzhiyun 		return 0;
894*4882a593Smuzhiyun 	}
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	return -EINVAL;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun 
fimc_lite_s_selection(struct file * file,void * fh,struct v4l2_selection * sel)899*4882a593Smuzhiyun static int fimc_lite_s_selection(struct file *file, void *fh,
900*4882a593Smuzhiyun 				 struct v4l2_selection *sel)
901*4882a593Smuzhiyun {
902*4882a593Smuzhiyun 	struct fimc_lite *fimc = video_drvdata(file);
903*4882a593Smuzhiyun 	struct flite_frame *f = &fimc->out_frame;
904*4882a593Smuzhiyun 	struct v4l2_rect rect = sel->r;
905*4882a593Smuzhiyun 	unsigned long flags;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE ||
908*4882a593Smuzhiyun 	    sel->target != V4L2_SEL_TGT_COMPOSE)
909*4882a593Smuzhiyun 		return -EINVAL;
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	fimc_lite_try_compose(fimc, &rect);
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun 	if ((sel->flags & V4L2_SEL_FLAG_LE) &&
914*4882a593Smuzhiyun 	    !v4l2_rect_enclosed(&rect, &sel->r))
915*4882a593Smuzhiyun 		return -ERANGE;
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	if ((sel->flags & V4L2_SEL_FLAG_GE) &&
918*4882a593Smuzhiyun 	    !v4l2_rect_enclosed(&sel->r, &rect))
919*4882a593Smuzhiyun 		return -ERANGE;
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	sel->r = rect;
922*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
923*4882a593Smuzhiyun 	f->rect = rect;
924*4882a593Smuzhiyun 	set_bit(ST_FLITE_CONFIG, &fimc->state);
925*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun 	return 0;
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
931*4882a593Smuzhiyun 	.vidioc_querycap		= fimc_lite_querycap,
932*4882a593Smuzhiyun 	.vidioc_enum_fmt_vid_cap	= fimc_lite_enum_fmt,
933*4882a593Smuzhiyun 	.vidioc_try_fmt_vid_cap_mplane	= fimc_lite_try_fmt_mplane,
934*4882a593Smuzhiyun 	.vidioc_s_fmt_vid_cap_mplane	= fimc_lite_s_fmt_mplane,
935*4882a593Smuzhiyun 	.vidioc_g_fmt_vid_cap_mplane	= fimc_lite_g_fmt_mplane,
936*4882a593Smuzhiyun 	.vidioc_g_selection		= fimc_lite_g_selection,
937*4882a593Smuzhiyun 	.vidioc_s_selection		= fimc_lite_s_selection,
938*4882a593Smuzhiyun 	.vidioc_reqbufs			= fimc_lite_reqbufs,
939*4882a593Smuzhiyun 	.vidioc_querybuf		= vb2_ioctl_querybuf,
940*4882a593Smuzhiyun 	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
941*4882a593Smuzhiyun 	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
942*4882a593Smuzhiyun 	.vidioc_qbuf			= vb2_ioctl_qbuf,
943*4882a593Smuzhiyun 	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
944*4882a593Smuzhiyun 	.vidioc_streamon		= fimc_lite_streamon,
945*4882a593Smuzhiyun 	.vidioc_streamoff		= fimc_lite_streamoff,
946*4882a593Smuzhiyun };
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun /* Capture subdev media entity operations */
fimc_lite_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)949*4882a593Smuzhiyun static int fimc_lite_link_setup(struct media_entity *entity,
950*4882a593Smuzhiyun 				const struct media_pad *local,
951*4882a593Smuzhiyun 				const struct media_pad *remote, u32 flags)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
954*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
955*4882a593Smuzhiyun 	int ret = 0;
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun 	if (WARN_ON(fimc == NULL))
958*4882a593Smuzhiyun 		return 0;
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
961*4882a593Smuzhiyun 		 __func__, remote->entity->name, local->entity->name,
962*4882a593Smuzhiyun 		 flags, fimc->source_subdev_grp_id);
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	switch (local->index) {
965*4882a593Smuzhiyun 	case FLITE_SD_PAD_SINK:
966*4882a593Smuzhiyun 		if (flags & MEDIA_LNK_FL_ENABLED) {
967*4882a593Smuzhiyun 			if (fimc->source_subdev_grp_id == 0)
968*4882a593Smuzhiyun 				fimc->source_subdev_grp_id = sd->grp_id;
969*4882a593Smuzhiyun 			else
970*4882a593Smuzhiyun 				ret = -EBUSY;
971*4882a593Smuzhiyun 		} else {
972*4882a593Smuzhiyun 			fimc->source_subdev_grp_id = 0;
973*4882a593Smuzhiyun 			fimc->sensor = NULL;
974*4882a593Smuzhiyun 		}
975*4882a593Smuzhiyun 		break;
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	case FLITE_SD_PAD_SOURCE_DMA:
978*4882a593Smuzhiyun 		if (!(flags & MEDIA_LNK_FL_ENABLED))
979*4882a593Smuzhiyun 			atomic_set(&fimc->out_path, FIMC_IO_NONE);
980*4882a593Smuzhiyun 		else
981*4882a593Smuzhiyun 			atomic_set(&fimc->out_path, FIMC_IO_DMA);
982*4882a593Smuzhiyun 		break;
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	case FLITE_SD_PAD_SOURCE_ISP:
985*4882a593Smuzhiyun 		if (!(flags & MEDIA_LNK_FL_ENABLED))
986*4882a593Smuzhiyun 			atomic_set(&fimc->out_path, FIMC_IO_NONE);
987*4882a593Smuzhiyun 		else
988*4882a593Smuzhiyun 			atomic_set(&fimc->out_path, FIMC_IO_ISP);
989*4882a593Smuzhiyun 		break;
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	default:
992*4882a593Smuzhiyun 		v4l2_err(sd, "Invalid pad index\n");
993*4882a593Smuzhiyun 		ret = -EINVAL;
994*4882a593Smuzhiyun 	}
995*4882a593Smuzhiyun 	mb();
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	return ret;
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun static const struct media_entity_operations fimc_lite_subdev_media_ops = {
1001*4882a593Smuzhiyun 	.link_setup = fimc_lite_link_setup,
1002*4882a593Smuzhiyun };
1003*4882a593Smuzhiyun 
fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1004*4882a593Smuzhiyun static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
1005*4882a593Smuzhiyun 					   struct v4l2_subdev_pad_config *cfg,
1006*4882a593Smuzhiyun 					   struct v4l2_subdev_mbus_code_enum *code)
1007*4882a593Smuzhiyun {
1008*4882a593Smuzhiyun 	const struct fimc_fmt *fmt;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	fmt = fimc_lite_find_format(NULL, NULL, 0, code->index);
1011*4882a593Smuzhiyun 	if (!fmt)
1012*4882a593Smuzhiyun 		return -EINVAL;
1013*4882a593Smuzhiyun 	code->code = fmt->mbus_code;
1014*4882a593Smuzhiyun 	return 0;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
__fimc_lite_subdev_get_try_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,unsigned int pad)1017*4882a593Smuzhiyun static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt(
1018*4882a593Smuzhiyun 		struct v4l2_subdev *sd,
1019*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg, unsigned int pad)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun 	if (pad != FLITE_SD_PAD_SINK)
1022*4882a593Smuzhiyun 		pad = FLITE_SD_PAD_SOURCE_DMA;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	return v4l2_subdev_get_try_format(sd, cfg, pad);
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun 
fimc_lite_subdev_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1027*4882a593Smuzhiyun static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
1028*4882a593Smuzhiyun 				    struct v4l2_subdev_pad_config *cfg,
1029*4882a593Smuzhiyun 				    struct v4l2_subdev_format *fmt)
1030*4882a593Smuzhiyun {
1031*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1032*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &fmt->format;
1033*4882a593Smuzhiyun 	struct flite_frame *f = &fimc->inp_frame;
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1036*4882a593Smuzhiyun 		mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
1037*4882a593Smuzhiyun 		fmt->format = *mf;
1038*4882a593Smuzhiyun 		return 0;
1039*4882a593Smuzhiyun 	}
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1042*4882a593Smuzhiyun 	mf->colorspace = f->fmt->colorspace;
1043*4882a593Smuzhiyun 	mf->code = f->fmt->mbus_code;
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun 	if (fmt->pad == FLITE_SD_PAD_SINK) {
1046*4882a593Smuzhiyun 		/* full camera input frame size */
1047*4882a593Smuzhiyun 		mf->width = f->f_width;
1048*4882a593Smuzhiyun 		mf->height = f->f_height;
1049*4882a593Smuzhiyun 	} else {
1050*4882a593Smuzhiyun 		/* crop size */
1051*4882a593Smuzhiyun 		mf->width = f->rect.width;
1052*4882a593Smuzhiyun 		mf->height = f->rect.height;
1053*4882a593Smuzhiyun 	}
1054*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1055*4882a593Smuzhiyun 	return 0;
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun 
fimc_lite_subdev_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1058*4882a593Smuzhiyun static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
1059*4882a593Smuzhiyun 				    struct v4l2_subdev_pad_config *cfg,
1060*4882a593Smuzhiyun 				    struct v4l2_subdev_format *fmt)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1063*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &fmt->format;
1064*4882a593Smuzhiyun 	struct flite_frame *sink = &fimc->inp_frame;
1065*4882a593Smuzhiyun 	struct flite_frame *source = &fimc->out_frame;
1066*4882a593Smuzhiyun 	const struct fimc_fmt *ffmt;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
1069*4882a593Smuzhiyun 		 fmt->pad, mf->code, mf->width, mf->height);
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
1074*4882a593Smuzhiyun 	    sd->entity.stream_count > 0) ||
1075*4882a593Smuzhiyun 	    (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
1076*4882a593Smuzhiyun 	    vb2_is_busy(&fimc->vb_queue))) {
1077*4882a593Smuzhiyun 		mutex_unlock(&fimc->lock);
1078*4882a593Smuzhiyun 		return -EBUSY;
1079*4882a593Smuzhiyun 	}
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	ffmt = fimc_lite_subdev_try_fmt(fimc, cfg, fmt);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1084*4882a593Smuzhiyun 		struct v4l2_mbus_framefmt *src_fmt;
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 		mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
1087*4882a593Smuzhiyun 		*mf = fmt->format;
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 		if (fmt->pad == FLITE_SD_PAD_SINK) {
1090*4882a593Smuzhiyun 			unsigned int pad = FLITE_SD_PAD_SOURCE_DMA;
1091*4882a593Smuzhiyun 			src_fmt = __fimc_lite_subdev_get_try_fmt(sd, cfg, pad);
1092*4882a593Smuzhiyun 			*src_fmt = *mf;
1093*4882a593Smuzhiyun 		}
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 		mutex_unlock(&fimc->lock);
1096*4882a593Smuzhiyun 		return 0;
1097*4882a593Smuzhiyun 	}
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	if (fmt->pad == FLITE_SD_PAD_SINK) {
1100*4882a593Smuzhiyun 		sink->f_width = mf->width;
1101*4882a593Smuzhiyun 		sink->f_height = mf->height;
1102*4882a593Smuzhiyun 		sink->fmt = ffmt;
1103*4882a593Smuzhiyun 		/* Set sink crop rectangle */
1104*4882a593Smuzhiyun 		sink->rect.width = mf->width;
1105*4882a593Smuzhiyun 		sink->rect.height = mf->height;
1106*4882a593Smuzhiyun 		sink->rect.left = 0;
1107*4882a593Smuzhiyun 		sink->rect.top = 0;
1108*4882a593Smuzhiyun 		/* Reset source format and crop rectangle */
1109*4882a593Smuzhiyun 		source->rect = sink->rect;
1110*4882a593Smuzhiyun 		source->f_width = mf->width;
1111*4882a593Smuzhiyun 		source->f_height = mf->height;
1112*4882a593Smuzhiyun 	}
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1115*4882a593Smuzhiyun 	return 0;
1116*4882a593Smuzhiyun }
1117*4882a593Smuzhiyun 
fimc_lite_subdev_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1118*4882a593Smuzhiyun static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
1119*4882a593Smuzhiyun 					  struct v4l2_subdev_pad_config *cfg,
1120*4882a593Smuzhiyun 					  struct v4l2_subdev_selection *sel)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1123*4882a593Smuzhiyun 	struct flite_frame *f = &fimc->inp_frame;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	if ((sel->target != V4L2_SEL_TGT_CROP &&
1126*4882a593Smuzhiyun 	     sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
1127*4882a593Smuzhiyun 	     sel->pad != FLITE_SD_PAD_SINK)
1128*4882a593Smuzhiyun 		return -EINVAL;
1129*4882a593Smuzhiyun 
1130*4882a593Smuzhiyun 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1131*4882a593Smuzhiyun 		sel->r = *v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
1132*4882a593Smuzhiyun 		return 0;
1133*4882a593Smuzhiyun 	}
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1136*4882a593Smuzhiyun 	if (sel->target == V4L2_SEL_TGT_CROP) {
1137*4882a593Smuzhiyun 		sel->r = f->rect;
1138*4882a593Smuzhiyun 	} else {
1139*4882a593Smuzhiyun 		sel->r.left = 0;
1140*4882a593Smuzhiyun 		sel->r.top = 0;
1141*4882a593Smuzhiyun 		sel->r.width = f->f_width;
1142*4882a593Smuzhiyun 		sel->r.height = f->f_height;
1143*4882a593Smuzhiyun 	}
1144*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1145*4882a593Smuzhiyun 
1146*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
1147*4882a593Smuzhiyun 		 __func__, f->rect.left, f->rect.top, f->rect.width,
1148*4882a593Smuzhiyun 		 f->rect.height, f->f_width, f->f_height);
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	return 0;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun 
fimc_lite_subdev_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1153*4882a593Smuzhiyun static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
1154*4882a593Smuzhiyun 					  struct v4l2_subdev_pad_config *cfg,
1155*4882a593Smuzhiyun 					  struct v4l2_subdev_selection *sel)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1158*4882a593Smuzhiyun 	struct flite_frame *f = &fimc->inp_frame;
1159*4882a593Smuzhiyun 	int ret = 0;
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
1162*4882a593Smuzhiyun 		return -EINVAL;
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1165*4882a593Smuzhiyun 	fimc_lite_try_crop(fimc, &sel->r);
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1168*4882a593Smuzhiyun 		*v4l2_subdev_get_try_crop(sd, cfg, sel->pad) = sel->r;
1169*4882a593Smuzhiyun 	} else {
1170*4882a593Smuzhiyun 		unsigned long flags;
1171*4882a593Smuzhiyun 		spin_lock_irqsave(&fimc->slock, flags);
1172*4882a593Smuzhiyun 		f->rect = sel->r;
1173*4882a593Smuzhiyun 		/* Same crop rectangle on the source pad */
1174*4882a593Smuzhiyun 		fimc->out_frame.rect = sel->r;
1175*4882a593Smuzhiyun 		set_bit(ST_FLITE_CONFIG, &fimc->state);
1176*4882a593Smuzhiyun 		spin_unlock_irqrestore(&fimc->slock, flags);
1177*4882a593Smuzhiyun 	}
1178*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
1181*4882a593Smuzhiyun 		 __func__, f->rect.left, f->rect.top, f->rect.width,
1182*4882a593Smuzhiyun 		 f->rect.height, f->f_width, f->f_height);
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	return ret;
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun 
fimc_lite_subdev_s_stream(struct v4l2_subdev * sd,int on)1187*4882a593Smuzhiyun static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
1188*4882a593Smuzhiyun {
1189*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1190*4882a593Smuzhiyun 	unsigned long flags;
1191*4882a593Smuzhiyun 	int ret;
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 	/*
1194*4882a593Smuzhiyun 	 * Find sensor subdev linked to FIMC-LITE directly or through
1195*4882a593Smuzhiyun 	 * MIPI-CSIS. This is required for configuration where FIMC-LITE
1196*4882a593Smuzhiyun 	 * is used as a subdev only and feeds data internally to FIMC-IS.
1197*4882a593Smuzhiyun 	 * The pipeline links are protected through entity.stream_count
1198*4882a593Smuzhiyun 	 * so there is no need to take the media graph mutex here.
1199*4882a593Smuzhiyun 	 */
1200*4882a593Smuzhiyun 	fimc->sensor = fimc_find_remote_sensor(&sd->entity);
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
1203*4882a593Smuzhiyun 		return -ENOIOCTLCMD;
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1206*4882a593Smuzhiyun 	if (on) {
1207*4882a593Smuzhiyun 		flite_hw_reset(fimc);
1208*4882a593Smuzhiyun 		ret = fimc_lite_hw_init(fimc, true);
1209*4882a593Smuzhiyun 		if (!ret) {
1210*4882a593Smuzhiyun 			spin_lock_irqsave(&fimc->slock, flags);
1211*4882a593Smuzhiyun 			flite_hw_capture_start(fimc);
1212*4882a593Smuzhiyun 			spin_unlock_irqrestore(&fimc->slock, flags);
1213*4882a593Smuzhiyun 		}
1214*4882a593Smuzhiyun 	} else {
1215*4882a593Smuzhiyun 		set_bit(ST_FLITE_OFF, &fimc->state);
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 		spin_lock_irqsave(&fimc->slock, flags);
1218*4882a593Smuzhiyun 		flite_hw_capture_stop(fimc);
1219*4882a593Smuzhiyun 		spin_unlock_irqrestore(&fimc->slock, flags);
1220*4882a593Smuzhiyun 
1221*4882a593Smuzhiyun 		ret = wait_event_timeout(fimc->irq_queue,
1222*4882a593Smuzhiyun 				!test_bit(ST_FLITE_OFF, &fimc->state),
1223*4882a593Smuzhiyun 				msecs_to_jiffies(200));
1224*4882a593Smuzhiyun 		if (ret == 0)
1225*4882a593Smuzhiyun 			v4l2_err(sd, "s_stream(0) timeout\n");
1226*4882a593Smuzhiyun 		clear_bit(ST_FLITE_RUN, &fimc->state);
1227*4882a593Smuzhiyun 	}
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1230*4882a593Smuzhiyun 	return ret;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun 
fimc_lite_log_status(struct v4l2_subdev * sd)1233*4882a593Smuzhiyun static int fimc_lite_log_status(struct v4l2_subdev *sd)
1234*4882a593Smuzhiyun {
1235*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	flite_hw_dump_regs(fimc, __func__);
1238*4882a593Smuzhiyun 	return 0;
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun 
fimc_lite_subdev_registered(struct v4l2_subdev * sd)1241*4882a593Smuzhiyun static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
1242*4882a593Smuzhiyun {
1243*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1244*4882a593Smuzhiyun 	struct vb2_queue *q = &fimc->vb_queue;
1245*4882a593Smuzhiyun 	struct video_device *vfd = &fimc->ve.vdev;
1246*4882a593Smuzhiyun 	int ret;
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	memset(vfd, 0, sizeof(*vfd));
1249*4882a593Smuzhiyun 	atomic_set(&fimc->out_path, FIMC_IO_DMA);
1250*4882a593Smuzhiyun 
1251*4882a593Smuzhiyun 	snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
1252*4882a593Smuzhiyun 		 fimc->index);
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 	vfd->fops = &fimc_lite_fops;
1255*4882a593Smuzhiyun 	vfd->ioctl_ops = &fimc_lite_ioctl_ops;
1256*4882a593Smuzhiyun 	vfd->v4l2_dev = sd->v4l2_dev;
1257*4882a593Smuzhiyun 	vfd->minor = -1;
1258*4882a593Smuzhiyun 	vfd->release = video_device_release_empty;
1259*4882a593Smuzhiyun 	vfd->queue = q;
1260*4882a593Smuzhiyun 	vfd->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING;
1261*4882a593Smuzhiyun 	fimc->reqbufs_count = 0;
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	INIT_LIST_HEAD(&fimc->pending_buf_q);
1264*4882a593Smuzhiyun 	INIT_LIST_HEAD(&fimc->active_buf_q);
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun 	memset(q, 0, sizeof(*q));
1267*4882a593Smuzhiyun 	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1268*4882a593Smuzhiyun 	q->io_modes = VB2_MMAP | VB2_USERPTR;
1269*4882a593Smuzhiyun 	q->ops = &fimc_lite_qops;
1270*4882a593Smuzhiyun 	q->mem_ops = &vb2_dma_contig_memops;
1271*4882a593Smuzhiyun 	q->buf_struct_size = sizeof(struct flite_buffer);
1272*4882a593Smuzhiyun 	q->drv_priv = fimc;
1273*4882a593Smuzhiyun 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1274*4882a593Smuzhiyun 	q->lock = &fimc->lock;
1275*4882a593Smuzhiyun 	q->dev = &fimc->pdev->dev;
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	ret = vb2_queue_init(q);
1278*4882a593Smuzhiyun 	if (ret < 0)
1279*4882a593Smuzhiyun 		return ret;
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun 	fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
1282*4882a593Smuzhiyun 	ret = media_entity_pads_init(&vfd->entity, 1, &fimc->vd_pad);
1283*4882a593Smuzhiyun 	if (ret < 0)
1284*4882a593Smuzhiyun 		return ret;
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	video_set_drvdata(vfd, fimc);
1287*4882a593Smuzhiyun 	fimc->ve.pipe = v4l2_get_subdev_hostdata(sd);
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
1290*4882a593Smuzhiyun 	if (ret < 0) {
1291*4882a593Smuzhiyun 		media_entity_cleanup(&vfd->entity);
1292*4882a593Smuzhiyun 		fimc->ve.pipe = NULL;
1293*4882a593Smuzhiyun 		return ret;
1294*4882a593Smuzhiyun 	}
1295*4882a593Smuzhiyun 
1296*4882a593Smuzhiyun 	v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
1297*4882a593Smuzhiyun 		  vfd->name, video_device_node_name(vfd));
1298*4882a593Smuzhiyun 	return 0;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun 
fimc_lite_subdev_unregistered(struct v4l2_subdev * sd)1301*4882a593Smuzhiyun static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
1302*4882a593Smuzhiyun {
1303*4882a593Smuzhiyun 	struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
1304*4882a593Smuzhiyun 
1305*4882a593Smuzhiyun 	if (fimc == NULL)
1306*4882a593Smuzhiyun 		return;
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	mutex_lock(&fimc->lock);
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	if (video_is_registered(&fimc->ve.vdev)) {
1311*4882a593Smuzhiyun 		video_unregister_device(&fimc->ve.vdev);
1312*4882a593Smuzhiyun 		media_entity_cleanup(&fimc->ve.vdev.entity);
1313*4882a593Smuzhiyun 		fimc->ve.pipe = NULL;
1314*4882a593Smuzhiyun 	}
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	mutex_unlock(&fimc->lock);
1317*4882a593Smuzhiyun }
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
1320*4882a593Smuzhiyun 	.registered = fimc_lite_subdev_registered,
1321*4882a593Smuzhiyun 	.unregistered = fimc_lite_subdev_unregistered,
1322*4882a593Smuzhiyun };
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
1325*4882a593Smuzhiyun 	.enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
1326*4882a593Smuzhiyun 	.get_selection = fimc_lite_subdev_get_selection,
1327*4882a593Smuzhiyun 	.set_selection = fimc_lite_subdev_set_selection,
1328*4882a593Smuzhiyun 	.get_fmt = fimc_lite_subdev_get_fmt,
1329*4882a593Smuzhiyun 	.set_fmt = fimc_lite_subdev_set_fmt,
1330*4882a593Smuzhiyun };
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
1333*4882a593Smuzhiyun 	.s_stream = fimc_lite_subdev_s_stream,
1334*4882a593Smuzhiyun };
1335*4882a593Smuzhiyun 
1336*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
1337*4882a593Smuzhiyun 	.log_status = fimc_lite_log_status,
1338*4882a593Smuzhiyun };
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun static const struct v4l2_subdev_ops fimc_lite_subdev_ops = {
1341*4882a593Smuzhiyun 	.core = &fimc_lite_core_ops,
1342*4882a593Smuzhiyun 	.video = &fimc_lite_subdev_video_ops,
1343*4882a593Smuzhiyun 	.pad = &fimc_lite_subdev_pad_ops,
1344*4882a593Smuzhiyun };
1345*4882a593Smuzhiyun 
fimc_lite_s_ctrl(struct v4l2_ctrl * ctrl)1346*4882a593Smuzhiyun static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun 	struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
1349*4882a593Smuzhiyun 					      ctrl_handler);
1350*4882a593Smuzhiyun 	set_bit(ST_FLITE_CONFIG, &fimc->state);
1351*4882a593Smuzhiyun 	return 0;
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
1355*4882a593Smuzhiyun 	.s_ctrl	= fimc_lite_s_ctrl,
1356*4882a593Smuzhiyun };
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun static const struct v4l2_ctrl_config fimc_lite_ctrl = {
1359*4882a593Smuzhiyun 	.ops	= &fimc_lite_ctrl_ops,
1360*4882a593Smuzhiyun 	.id	= V4L2_CTRL_CLASS_USER | 0x1001,
1361*4882a593Smuzhiyun 	.type	= V4L2_CTRL_TYPE_BOOLEAN,
1362*4882a593Smuzhiyun 	.name	= "Test Pattern 640x480",
1363*4882a593Smuzhiyun 	.step	= 1,
1364*4882a593Smuzhiyun };
1365*4882a593Smuzhiyun 
fimc_lite_set_default_config(struct fimc_lite * fimc)1366*4882a593Smuzhiyun static void fimc_lite_set_default_config(struct fimc_lite *fimc)
1367*4882a593Smuzhiyun {
1368*4882a593Smuzhiyun 	struct flite_frame *sink = &fimc->inp_frame;
1369*4882a593Smuzhiyun 	struct flite_frame *source = &fimc->out_frame;
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	sink->fmt = &fimc_lite_formats[0];
1372*4882a593Smuzhiyun 	sink->f_width = FLITE_DEFAULT_WIDTH;
1373*4882a593Smuzhiyun 	sink->f_height = FLITE_DEFAULT_HEIGHT;
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	sink->rect.width = FLITE_DEFAULT_WIDTH;
1376*4882a593Smuzhiyun 	sink->rect.height = FLITE_DEFAULT_HEIGHT;
1377*4882a593Smuzhiyun 	sink->rect.left = 0;
1378*4882a593Smuzhiyun 	sink->rect.top = 0;
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	*source = *sink;
1381*4882a593Smuzhiyun }
1382*4882a593Smuzhiyun 
fimc_lite_create_capture_subdev(struct fimc_lite * fimc)1383*4882a593Smuzhiyun static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
1384*4882a593Smuzhiyun {
1385*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
1386*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &fimc->subdev;
1387*4882a593Smuzhiyun 	int ret;
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
1390*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1391*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
1392*4882a593Smuzhiyun 
1393*4882a593Smuzhiyun 	fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1394*4882a593Smuzhiyun 	fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
1395*4882a593Smuzhiyun 	fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
1396*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, FLITE_SD_PADS_NUM,
1397*4882a593Smuzhiyun 				fimc->subdev_pads);
1398*4882a593Smuzhiyun 	if (ret)
1399*4882a593Smuzhiyun 		return ret;
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(handler, 1);
1402*4882a593Smuzhiyun 	fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
1403*4882a593Smuzhiyun 						  NULL);
1404*4882a593Smuzhiyun 	if (handler->error) {
1405*4882a593Smuzhiyun 		media_entity_cleanup(&sd->entity);
1406*4882a593Smuzhiyun 		return handler->error;
1407*4882a593Smuzhiyun 	}
1408*4882a593Smuzhiyun 
1409*4882a593Smuzhiyun 	sd->ctrl_handler = handler;
1410*4882a593Smuzhiyun 	sd->internal_ops = &fimc_lite_subdev_internal_ops;
1411*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
1412*4882a593Smuzhiyun 	sd->entity.ops = &fimc_lite_subdev_media_ops;
1413*4882a593Smuzhiyun 	sd->owner = THIS_MODULE;
1414*4882a593Smuzhiyun 	v4l2_set_subdevdata(sd, fimc);
1415*4882a593Smuzhiyun 
1416*4882a593Smuzhiyun 	return 0;
1417*4882a593Smuzhiyun }
1418*4882a593Smuzhiyun 
fimc_lite_unregister_capture_subdev(struct fimc_lite * fimc)1419*4882a593Smuzhiyun static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
1420*4882a593Smuzhiyun {
1421*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &fimc->subdev;
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
1424*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1425*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&fimc->ctrl_handler);
1426*4882a593Smuzhiyun 	v4l2_set_subdevdata(sd, NULL);
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun 
fimc_lite_clk_put(struct fimc_lite * fimc)1429*4882a593Smuzhiyun static void fimc_lite_clk_put(struct fimc_lite *fimc)
1430*4882a593Smuzhiyun {
1431*4882a593Smuzhiyun 	if (IS_ERR(fimc->clock))
1432*4882a593Smuzhiyun 		return;
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun 	clk_put(fimc->clock);
1435*4882a593Smuzhiyun 	fimc->clock = ERR_PTR(-EINVAL);
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun 
fimc_lite_clk_get(struct fimc_lite * fimc)1438*4882a593Smuzhiyun static int fimc_lite_clk_get(struct fimc_lite *fimc)
1439*4882a593Smuzhiyun {
1440*4882a593Smuzhiyun 	fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
1441*4882a593Smuzhiyun 	return PTR_ERR_OR_ZERO(fimc->clock);
1442*4882a593Smuzhiyun }
1443*4882a593Smuzhiyun 
1444*4882a593Smuzhiyun static const struct of_device_id flite_of_match[];
1445*4882a593Smuzhiyun 
fimc_lite_probe(struct platform_device * pdev)1446*4882a593Smuzhiyun static int fimc_lite_probe(struct platform_device *pdev)
1447*4882a593Smuzhiyun {
1448*4882a593Smuzhiyun 	struct flite_drvdata *drv_data = NULL;
1449*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
1450*4882a593Smuzhiyun 	const struct of_device_id *of_id;
1451*4882a593Smuzhiyun 	struct fimc_lite *fimc;
1452*4882a593Smuzhiyun 	struct resource *res;
1453*4882a593Smuzhiyun 	int ret;
1454*4882a593Smuzhiyun 
1455*4882a593Smuzhiyun 	if (!dev->of_node)
1456*4882a593Smuzhiyun 		return -ENODEV;
1457*4882a593Smuzhiyun 
1458*4882a593Smuzhiyun 	fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
1459*4882a593Smuzhiyun 	if (!fimc)
1460*4882a593Smuzhiyun 		return -ENOMEM;
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun 	of_id = of_match_node(flite_of_match, dev->of_node);
1463*4882a593Smuzhiyun 	if (of_id)
1464*4882a593Smuzhiyun 		drv_data = (struct flite_drvdata *)of_id->data;
1465*4882a593Smuzhiyun 	fimc->index = of_alias_get_id(dev->of_node, "fimc-lite");
1466*4882a593Smuzhiyun 
1467*4882a593Smuzhiyun 	if (!drv_data || fimc->index >= drv_data->num_instances ||
1468*4882a593Smuzhiyun 						fimc->index < 0) {
1469*4882a593Smuzhiyun 		dev_err(dev, "Wrong %pOF node alias\n", dev->of_node);
1470*4882a593Smuzhiyun 		return -EINVAL;
1471*4882a593Smuzhiyun 	}
1472*4882a593Smuzhiyun 
1473*4882a593Smuzhiyun 	fimc->dd = drv_data;
1474*4882a593Smuzhiyun 	fimc->pdev = pdev;
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	init_waitqueue_head(&fimc->irq_queue);
1477*4882a593Smuzhiyun 	spin_lock_init(&fimc->slock);
1478*4882a593Smuzhiyun 	mutex_init(&fimc->lock);
1479*4882a593Smuzhiyun 
1480*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481*4882a593Smuzhiyun 	fimc->regs = devm_ioremap_resource(dev, res);
1482*4882a593Smuzhiyun 	if (IS_ERR(fimc->regs))
1483*4882a593Smuzhiyun 		return PTR_ERR(fimc->regs);
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1486*4882a593Smuzhiyun 	if (res == NULL) {
1487*4882a593Smuzhiyun 		dev_err(dev, "Failed to get IRQ resource\n");
1488*4882a593Smuzhiyun 		return -ENXIO;
1489*4882a593Smuzhiyun 	}
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun 	ret = fimc_lite_clk_get(fimc);
1492*4882a593Smuzhiyun 	if (ret)
1493*4882a593Smuzhiyun 		return ret;
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	ret = devm_request_irq(dev, res->start, flite_irq_handler,
1496*4882a593Smuzhiyun 			       0, dev_name(dev), fimc);
1497*4882a593Smuzhiyun 	if (ret) {
1498*4882a593Smuzhiyun 		dev_err(dev, "Failed to install irq (%d)\n", ret);
1499*4882a593Smuzhiyun 		goto err_clk_put;
1500*4882a593Smuzhiyun 	}
1501*4882a593Smuzhiyun 
1502*4882a593Smuzhiyun 	/* The video node will be created within the subdev's registered() op */
1503*4882a593Smuzhiyun 	ret = fimc_lite_create_capture_subdev(fimc);
1504*4882a593Smuzhiyun 	if (ret)
1505*4882a593Smuzhiyun 		goto err_clk_put;
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun 	platform_set_drvdata(pdev, fimc);
1508*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 	if (!pm_runtime_enabled(dev)) {
1511*4882a593Smuzhiyun 		ret = clk_prepare_enable(fimc->clock);
1512*4882a593Smuzhiyun 		if (ret < 0)
1513*4882a593Smuzhiyun 			goto err_sd;
1514*4882a593Smuzhiyun 	}
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	fimc_lite_set_default_config(fimc);
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	dev_dbg(dev, "FIMC-LITE.%d registered successfully\n",
1521*4882a593Smuzhiyun 		fimc->index);
1522*4882a593Smuzhiyun 	return 0;
1523*4882a593Smuzhiyun 
1524*4882a593Smuzhiyun err_sd:
1525*4882a593Smuzhiyun 	fimc_lite_unregister_capture_subdev(fimc);
1526*4882a593Smuzhiyun err_clk_put:
1527*4882a593Smuzhiyun 	fimc_lite_clk_put(fimc);
1528*4882a593Smuzhiyun 	return ret;
1529*4882a593Smuzhiyun }
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun #ifdef CONFIG_PM
fimc_lite_runtime_resume(struct device * dev)1532*4882a593Smuzhiyun static int fimc_lite_runtime_resume(struct device *dev)
1533*4882a593Smuzhiyun {
1534*4882a593Smuzhiyun 	struct fimc_lite *fimc = dev_get_drvdata(dev);
1535*4882a593Smuzhiyun 
1536*4882a593Smuzhiyun 	clk_prepare_enable(fimc->clock);
1537*4882a593Smuzhiyun 	return 0;
1538*4882a593Smuzhiyun }
1539*4882a593Smuzhiyun 
fimc_lite_runtime_suspend(struct device * dev)1540*4882a593Smuzhiyun static int fimc_lite_runtime_suspend(struct device *dev)
1541*4882a593Smuzhiyun {
1542*4882a593Smuzhiyun 	struct fimc_lite *fimc = dev_get_drvdata(dev);
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun 	clk_disable_unprepare(fimc->clock);
1545*4882a593Smuzhiyun 	return 0;
1546*4882a593Smuzhiyun }
1547*4882a593Smuzhiyun #endif
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
fimc_lite_resume(struct device * dev)1550*4882a593Smuzhiyun static int fimc_lite_resume(struct device *dev)
1551*4882a593Smuzhiyun {
1552*4882a593Smuzhiyun 	struct fimc_lite *fimc = dev_get_drvdata(dev);
1553*4882a593Smuzhiyun 	struct flite_buffer *buf;
1554*4882a593Smuzhiyun 	unsigned long flags;
1555*4882a593Smuzhiyun 	int i;
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	spin_lock_irqsave(&fimc->slock, flags);
1558*4882a593Smuzhiyun 	if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1559*4882a593Smuzhiyun 	    !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
1560*4882a593Smuzhiyun 		spin_unlock_irqrestore(&fimc->slock, flags);
1561*4882a593Smuzhiyun 		return 0;
1562*4882a593Smuzhiyun 	}
1563*4882a593Smuzhiyun 	flite_hw_reset(fimc);
1564*4882a593Smuzhiyun 	spin_unlock_irqrestore(&fimc->slock, flags);
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun 	if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
1567*4882a593Smuzhiyun 		return 0;
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun 	INIT_LIST_HEAD(&fimc->active_buf_q);
1570*4882a593Smuzhiyun 	fimc_pipeline_call(&fimc->ve, open,
1571*4882a593Smuzhiyun 			   &fimc->ve.vdev.entity, false);
1572*4882a593Smuzhiyun 	fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
1573*4882a593Smuzhiyun 	clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun 	for (i = 0; i < fimc->reqbufs_count; i++) {
1576*4882a593Smuzhiyun 		if (list_empty(&fimc->pending_buf_q))
1577*4882a593Smuzhiyun 			break;
1578*4882a593Smuzhiyun 		buf = fimc_lite_pending_queue_pop(fimc);
1579*4882a593Smuzhiyun 		buffer_queue(&buf->vb.vb2_buf);
1580*4882a593Smuzhiyun 	}
1581*4882a593Smuzhiyun 	return 0;
1582*4882a593Smuzhiyun }
1583*4882a593Smuzhiyun 
fimc_lite_suspend(struct device * dev)1584*4882a593Smuzhiyun static int fimc_lite_suspend(struct device *dev)
1585*4882a593Smuzhiyun {
1586*4882a593Smuzhiyun 	struct fimc_lite *fimc = dev_get_drvdata(dev);
1587*4882a593Smuzhiyun 	bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
1588*4882a593Smuzhiyun 	int ret;
1589*4882a593Smuzhiyun 
1590*4882a593Smuzhiyun 	if (test_and_set_bit(ST_LPM, &fimc->state))
1591*4882a593Smuzhiyun 		return 0;
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 	ret = fimc_lite_stop_capture(fimc, suspend);
1594*4882a593Smuzhiyun 	if (ret < 0 || !fimc_lite_active(fimc))
1595*4882a593Smuzhiyun 		return ret;
1596*4882a593Smuzhiyun 
1597*4882a593Smuzhiyun 	return fimc_pipeline_call(&fimc->ve, close);
1598*4882a593Smuzhiyun }
1599*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1600*4882a593Smuzhiyun 
fimc_lite_remove(struct platform_device * pdev)1601*4882a593Smuzhiyun static int fimc_lite_remove(struct platform_device *pdev)
1602*4882a593Smuzhiyun {
1603*4882a593Smuzhiyun 	struct fimc_lite *fimc = platform_get_drvdata(pdev);
1604*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
1605*4882a593Smuzhiyun 
1606*4882a593Smuzhiyun 	if (!pm_runtime_enabled(dev))
1607*4882a593Smuzhiyun 		clk_disable_unprepare(fimc->clock);
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 	pm_runtime_disable(dev);
1610*4882a593Smuzhiyun 	pm_runtime_set_suspended(dev);
1611*4882a593Smuzhiyun 	fimc_lite_unregister_capture_subdev(fimc);
1612*4882a593Smuzhiyun 	vb2_dma_contig_clear_max_seg_size(dev);
1613*4882a593Smuzhiyun 	fimc_lite_clk_put(fimc);
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	dev_info(dev, "Driver unloaded\n");
1616*4882a593Smuzhiyun 	return 0;
1617*4882a593Smuzhiyun }
1618*4882a593Smuzhiyun 
1619*4882a593Smuzhiyun static const struct dev_pm_ops fimc_lite_pm_ops = {
1620*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
1621*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
1622*4882a593Smuzhiyun 			   NULL)
1623*4882a593Smuzhiyun };
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun /* EXYNOS4412 */
1626*4882a593Smuzhiyun static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
1627*4882a593Smuzhiyun 	.max_width		= 8192,
1628*4882a593Smuzhiyun 	.max_height		= 8192,
1629*4882a593Smuzhiyun 	.out_width_align	= 8,
1630*4882a593Smuzhiyun 	.win_hor_offs_align	= 2,
1631*4882a593Smuzhiyun 	.out_hor_offs_align	= 8,
1632*4882a593Smuzhiyun 	.max_dma_bufs		= 1,
1633*4882a593Smuzhiyun 	.num_instances		= 2,
1634*4882a593Smuzhiyun };
1635*4882a593Smuzhiyun 
1636*4882a593Smuzhiyun /* EXYNOS5250 */
1637*4882a593Smuzhiyun static struct flite_drvdata fimc_lite_drvdata_exynos5 = {
1638*4882a593Smuzhiyun 	.max_width		= 8192,
1639*4882a593Smuzhiyun 	.max_height		= 8192,
1640*4882a593Smuzhiyun 	.out_width_align	= 8,
1641*4882a593Smuzhiyun 	.win_hor_offs_align	= 2,
1642*4882a593Smuzhiyun 	.out_hor_offs_align	= 8,
1643*4882a593Smuzhiyun 	.max_dma_bufs		= 32,
1644*4882a593Smuzhiyun 	.num_instances		= 3,
1645*4882a593Smuzhiyun };
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun static const struct of_device_id flite_of_match[] = {
1648*4882a593Smuzhiyun 	{
1649*4882a593Smuzhiyun 		.compatible = "samsung,exynos4212-fimc-lite",
1650*4882a593Smuzhiyun 		.data = &fimc_lite_drvdata_exynos4,
1651*4882a593Smuzhiyun 	},
1652*4882a593Smuzhiyun 	{
1653*4882a593Smuzhiyun 		.compatible = "samsung,exynos5250-fimc-lite",
1654*4882a593Smuzhiyun 		.data = &fimc_lite_drvdata_exynos5,
1655*4882a593Smuzhiyun 	},
1656*4882a593Smuzhiyun 	{ /* sentinel */ },
1657*4882a593Smuzhiyun };
1658*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, flite_of_match);
1659*4882a593Smuzhiyun 
1660*4882a593Smuzhiyun static struct platform_driver fimc_lite_driver = {
1661*4882a593Smuzhiyun 	.probe		= fimc_lite_probe,
1662*4882a593Smuzhiyun 	.remove		= fimc_lite_remove,
1663*4882a593Smuzhiyun 	.driver = {
1664*4882a593Smuzhiyun 		.of_match_table = flite_of_match,
1665*4882a593Smuzhiyun 		.name		= FIMC_LITE_DRV_NAME,
1666*4882a593Smuzhiyun 		.pm		= &fimc_lite_pm_ops,
1667*4882a593Smuzhiyun 	}
1668*4882a593Smuzhiyun };
1669*4882a593Smuzhiyun module_platform_driver(fimc_lite_driver);
1670*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1671*4882a593Smuzhiyun MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);
1672