1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef FIMC_LITE_REG_H_
7*4882a593Smuzhiyun #define FIMC_LITE_REG_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "fimc-lite.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* Camera Source size */
14*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE 0x00
15*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
16*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
17*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
18*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
19*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
20*4882a593Smuzhiyun #define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Global control */
23*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL 0x04
24*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24)
25*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24)
26*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24)
27*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24)
28*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24)
29*4882a593Smuzhiyun /* User defined formats. x = 0...15 */
30*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
31*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24)
32*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21)
33*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20)
34*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19)
35*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18)
36*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_SWRST BIT(17)
37*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15)
38*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14)
39*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13)
40*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12)
41*4882a593Smuzhiyun /* Interrupts mask bits (1 disables an interrupt) */
42*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8)
43*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7)
44*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6)
45*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5)
46*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5)
47*4882a593Smuzhiyun #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Image Capture Enable */
50*4882a593Smuzhiyun #define FLITE_REG_CIIMGCPT 0x08
51*4882a593Smuzhiyun #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31)
52*4882a593Smuzhiyun #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25)
53*4882a593Smuzhiyun #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18)
54*4882a593Smuzhiyun #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Capture Sequence */
57*4882a593Smuzhiyun #define FLITE_REG_CICPTSEQ 0x0c
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Camera Window Offset */
60*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST 0x10
61*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31)
62*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST_CLROVIY BIT(31)
63*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15)
64*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14)
65*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Camera Window Offset2 */
68*4882a593Smuzhiyun #define FLITE_REG_CIWDOFST2 0x14
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Camera Output DMA Format */
71*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT 0x18
72*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15)
73*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_PACK12 BIT(14)
74*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4)
75*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4)
76*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4)
77*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_CRYCBY (3 << 4)
78*4882a593Smuzhiyun #define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4)
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* Camera Output Canvas */
81*4882a593Smuzhiyun #define FLITE_REG_CIOCAN 0x20
82*4882a593Smuzhiyun #define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff)
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Camera Output DMA Offset */
85*4882a593Smuzhiyun #define FLITE_REG_CIOOFF 0x24
86*4882a593Smuzhiyun #define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff)
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Camera Output DMA Start Address */
89*4882a593Smuzhiyun #define FLITE_REG_CIOSA 0x30
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Camera Status */
92*4882a593Smuzhiyun #define FLITE_REG_CISTATUS 0x40
93*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22)
94*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21)
95*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20)
96*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14)
97*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13)
98*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_OVFIY BIT(10)
99*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_OVFICB BIT(9)
100*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_OVFICR BIT(8)
101*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7)
102*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6)
103*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5)
104*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4)
105*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0)
106*4882a593Smuzhiyun #define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4)
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Camera Status2 */
109*4882a593Smuzhiyun #define FLITE_REG_CISTATUS2 0x44
110*4882a593Smuzhiyun #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1)
111*4882a593Smuzhiyun #define FLITE_REG_CISTATUS2_FRMEND BIT(0)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Qos Threshold */
114*4882a593Smuzhiyun #define FLITE_REG_CITHOLD 0xf0
115*4882a593Smuzhiyun #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30)
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Camera General Purpose */
118*4882a593Smuzhiyun #define FLITE_REG_CIGENERAL 0xfc
119*4882a593Smuzhiyun /* b0: 1 - camera B, 0 - camera A */
120*4882a593Smuzhiyun #define FLITE_REG_CIGENERAL_CAM_B BIT(0)
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #define FLITE_REG_CIFCNTSEQ 0x100
123*4882a593Smuzhiyun #define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x)))
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* ----------------------------------------------------------------------------
126*4882a593Smuzhiyun * Function declarations
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun void flite_hw_reset(struct fimc_lite *dev);
129*4882a593Smuzhiyun void flite_hw_clear_pending_irq(struct fimc_lite *dev);
130*4882a593Smuzhiyun u32 flite_hw_get_interrupt_source(struct fimc_lite *dev);
131*4882a593Smuzhiyun void flite_hw_clear_last_capture_end(struct fimc_lite *dev);
132*4882a593Smuzhiyun void flite_hw_set_interrupt_mask(struct fimc_lite *dev);
133*4882a593Smuzhiyun void flite_hw_capture_start(struct fimc_lite *dev);
134*4882a593Smuzhiyun void flite_hw_capture_stop(struct fimc_lite *dev);
135*4882a593Smuzhiyun void flite_hw_set_camera_bus(struct fimc_lite *dev,
136*4882a593Smuzhiyun struct fimc_source_info *s_info);
137*4882a593Smuzhiyun void flite_hw_set_camera_polarity(struct fimc_lite *dev,
138*4882a593Smuzhiyun struct fimc_source_info *cam);
139*4882a593Smuzhiyun void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f);
140*4882a593Smuzhiyun void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f,
143*4882a593Smuzhiyun bool enable);
144*4882a593Smuzhiyun void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f);
145*4882a593Smuzhiyun void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on);
146*4882a593Smuzhiyun void flite_hw_dump_regs(struct fimc_lite *dev, const char *label);
147*4882a593Smuzhiyun void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf);
148*4882a593Smuzhiyun void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index);
149*4882a593Smuzhiyun
flite_hw_set_dma_buf_mask(struct fimc_lite * dev,u32 mask)150*4882a593Smuzhiyun static inline void flite_hw_set_dma_buf_mask(struct fimc_lite *dev, u32 mask)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #endif /* FIMC_LITE_REG_H */
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