xref: /OK3568_Linux_fs/kernel/drivers/media/platform/exynos4-is/fimc-isp.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
8*4882a593Smuzhiyun  *          Younghwan Joo <yhwan.joo@samsung.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/list.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/printk.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/types.h>
22*4882a593Smuzhiyun #include <media/v4l2-device.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "media-dev.h"
25*4882a593Smuzhiyun #include "fimc-isp-video.h"
26*4882a593Smuzhiyun #include "fimc-is-command.h"
27*4882a593Smuzhiyun #include "fimc-is-param.h"
28*4882a593Smuzhiyun #include "fimc-is-regs.h"
29*4882a593Smuzhiyun #include "fimc-is.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun int fimc_isp_debug;
32*4882a593Smuzhiyun module_param_named(debug_isp, fimc_isp_debug, int, S_IRUGO | S_IWUSR);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
35*4882a593Smuzhiyun 	{
36*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG8,
37*4882a593Smuzhiyun 		.depth		= { 8 },
38*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW8,
39*4882a593Smuzhiyun 		.memplanes	= 1,
40*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
41*4882a593Smuzhiyun 	}, {
42*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG10,
43*4882a593Smuzhiyun 		.depth		= { 10 },
44*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW10,
45*4882a593Smuzhiyun 		.memplanes	= 1,
46*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
47*4882a593Smuzhiyun 	}, {
48*4882a593Smuzhiyun 		.fourcc		= V4L2_PIX_FMT_SGRBG12,
49*4882a593Smuzhiyun 		.depth		= { 12 },
50*4882a593Smuzhiyun 		.color		= FIMC_FMT_RAW12,
51*4882a593Smuzhiyun 		.memplanes	= 1,
52*4882a593Smuzhiyun 		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
53*4882a593Smuzhiyun 	},
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /**
57*4882a593Smuzhiyun  * fimc_isp_find_format - lookup color format by fourcc or media bus code
58*4882a593Smuzhiyun  * @pixelformat: fourcc to match, ignored if null
59*4882a593Smuzhiyun  * @mbus_code: media bus code to match, ignored if null
60*4882a593Smuzhiyun  * @index: index to the fimc_isp_formats array, ignored if negative
61*4882a593Smuzhiyun  */
fimc_isp_find_format(const u32 * pixelformat,const u32 * mbus_code,int index)62*4882a593Smuzhiyun const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
63*4882a593Smuzhiyun 					const u32 *mbus_code, int index)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	const struct fimc_fmt *fmt, *def_fmt = NULL;
66*4882a593Smuzhiyun 	unsigned int i;
67*4882a593Smuzhiyun 	int id = 0;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
70*4882a593Smuzhiyun 		return NULL;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
73*4882a593Smuzhiyun 		fmt = &fimc_isp_formats[i];
74*4882a593Smuzhiyun 		if (pixelformat && fmt->fourcc == *pixelformat)
75*4882a593Smuzhiyun 			return fmt;
76*4882a593Smuzhiyun 		if (mbus_code && fmt->mbus_code == *mbus_code)
77*4882a593Smuzhiyun 			return fmt;
78*4882a593Smuzhiyun 		if (index == id)
79*4882a593Smuzhiyun 			def_fmt = fmt;
80*4882a593Smuzhiyun 		id++;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 	return def_fmt;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
fimc_isp_irq_handler(struct fimc_is * is)85*4882a593Smuzhiyun void fimc_isp_irq_handler(struct fimc_is *is)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
88*4882a593Smuzhiyun 	is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
91*4882a593Smuzhiyun 	fimc_isp_video_irq_handler(is);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	wake_up(&is->irq_queue);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* Capture subdev media entity operations */
fimc_is_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)97*4882a593Smuzhiyun static int fimc_is_link_setup(struct media_entity *entity,
98*4882a593Smuzhiyun 				const struct media_pad *local,
99*4882a593Smuzhiyun 				const struct media_pad *remote, u32 flags)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static const struct media_entity_operations fimc_is_subdev_media_ops = {
105*4882a593Smuzhiyun 	.link_setup = fimc_is_link_setup,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
fimc_is_subdev_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)108*4882a593Smuzhiyun static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
109*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
110*4882a593Smuzhiyun 				struct v4l2_subdev_mbus_code_enum *code)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	const struct fimc_fmt *fmt;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	fmt = fimc_isp_find_format(NULL, NULL, code->index);
115*4882a593Smuzhiyun 	if (!fmt)
116*4882a593Smuzhiyun 		return -EINVAL;
117*4882a593Smuzhiyun 	code->code = fmt->mbus_code;
118*4882a593Smuzhiyun 	return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
fimc_isp_subdev_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)121*4882a593Smuzhiyun static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
122*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
123*4882a593Smuzhiyun 				   struct v4l2_subdev_format *fmt)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
126*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &fmt->format;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
129*4882a593Smuzhiyun 		*mf = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
130*4882a593Smuzhiyun 		return 0;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	mf->colorspace = V4L2_COLORSPACE_SRGB;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	mutex_lock(&isp->subdev_lock);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
138*4882a593Smuzhiyun 		/* ISP OTF input image format */
139*4882a593Smuzhiyun 		*mf = isp->sink_fmt;
140*4882a593Smuzhiyun 	} else {
141*4882a593Smuzhiyun 		/* ISP OTF output image format */
142*4882a593Smuzhiyun 		*mf = isp->src_fmt;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 		if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
145*4882a593Smuzhiyun 			mf->colorspace = V4L2_COLORSPACE_JPEG;
146*4882a593Smuzhiyun 			mf->code = MEDIA_BUS_FMT_YUV10_1X30;
147*4882a593Smuzhiyun 		}
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	mutex_unlock(&isp->subdev_lock);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	isp_dbg(1, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", __func__,
153*4882a593Smuzhiyun 		fmt->pad, mf->code, mf->width, mf->height);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
__isp_subdev_try_format(struct fimc_isp * isp,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)158*4882a593Smuzhiyun static void __isp_subdev_try_format(struct fimc_isp *isp,
159*4882a593Smuzhiyun 				    struct v4l2_subdev_pad_config *cfg,
160*4882a593Smuzhiyun 				    struct v4l2_subdev_format *fmt)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &fmt->format;
163*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *format;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	mf->colorspace = V4L2_COLORSPACE_SRGB;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
168*4882a593Smuzhiyun 		v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
169*4882a593Smuzhiyun 				FIMC_ISP_SINK_WIDTH_MAX, 0,
170*4882a593Smuzhiyun 				&mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
171*4882a593Smuzhiyun 				FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
172*4882a593Smuzhiyun 		mf->code = MEDIA_BUS_FMT_SGRBG10_1X10;
173*4882a593Smuzhiyun 	} else {
174*4882a593Smuzhiyun 		if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
175*4882a593Smuzhiyun 			format = v4l2_subdev_get_try_format(&isp->subdev, cfg,
176*4882a593Smuzhiyun 						FIMC_ISP_SD_PAD_SINK);
177*4882a593Smuzhiyun 		else
178*4882a593Smuzhiyun 			format = &isp->sink_fmt;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 		/* Allow changing format only on sink pad */
181*4882a593Smuzhiyun 		mf->width = format->width - FIMC_ISP_CAC_MARGIN_WIDTH;
182*4882a593Smuzhiyun 		mf->height = format->height - FIMC_ISP_CAC_MARGIN_HEIGHT;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 		if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
185*4882a593Smuzhiyun 			mf->code = MEDIA_BUS_FMT_YUV10_1X30;
186*4882a593Smuzhiyun 			mf->colorspace = V4L2_COLORSPACE_JPEG;
187*4882a593Smuzhiyun 		} else {
188*4882a593Smuzhiyun 			mf->code = format->code;
189*4882a593Smuzhiyun 		}
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
fimc_isp_subdev_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)193*4882a593Smuzhiyun static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
194*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
195*4882a593Smuzhiyun 				   struct v4l2_subdev_format *fmt)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
198*4882a593Smuzhiyun 	struct fimc_is *is = fimc_isp_to_is(isp);
199*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &fmt->format;
200*4882a593Smuzhiyun 	int ret = 0;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	isp_dbg(1, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
203*4882a593Smuzhiyun 		 __func__, fmt->pad, mf->code, mf->width, mf->height);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	mutex_lock(&isp->subdev_lock);
206*4882a593Smuzhiyun 	__isp_subdev_try_format(isp, cfg, fmt);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
209*4882a593Smuzhiyun 		mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
210*4882a593Smuzhiyun 		*mf = fmt->format;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		/* Propagate format to the source pads */
213*4882a593Smuzhiyun 		if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
214*4882a593Smuzhiyun 			struct v4l2_subdev_format format = *fmt;
215*4882a593Smuzhiyun 			unsigned int pad;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 			for (pad = FIMC_ISP_SD_PAD_SRC_FIFO;
218*4882a593Smuzhiyun 					pad < FIMC_ISP_SD_PADS_NUM; pad++) {
219*4882a593Smuzhiyun 				format.pad = pad;
220*4882a593Smuzhiyun 				__isp_subdev_try_format(isp, cfg, &format);
221*4882a593Smuzhiyun 				mf = v4l2_subdev_get_try_format(sd, cfg, pad);
222*4882a593Smuzhiyun 				*mf = format.format;
223*4882a593Smuzhiyun 			}
224*4882a593Smuzhiyun 		}
225*4882a593Smuzhiyun 	} else {
226*4882a593Smuzhiyun 		if (sd->entity.stream_count == 0) {
227*4882a593Smuzhiyun 			if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
228*4882a593Smuzhiyun 				struct v4l2_subdev_format format = *fmt;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 				isp->sink_fmt = *mf;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 				format.pad = FIMC_ISP_SD_PAD_SRC_DMA;
233*4882a593Smuzhiyun 				__isp_subdev_try_format(isp, cfg, &format);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 				isp->src_fmt = format.format;
236*4882a593Smuzhiyun 				__is_set_frame_size(is, &isp->src_fmt);
237*4882a593Smuzhiyun 			} else {
238*4882a593Smuzhiyun 				isp->src_fmt = *mf;
239*4882a593Smuzhiyun 			}
240*4882a593Smuzhiyun 		} else {
241*4882a593Smuzhiyun 			ret = -EBUSY;
242*4882a593Smuzhiyun 		}
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	mutex_unlock(&isp->subdev_lock);
246*4882a593Smuzhiyun 	return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
fimc_isp_subdev_s_stream(struct v4l2_subdev * sd,int on)249*4882a593Smuzhiyun static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
252*4882a593Smuzhiyun 	struct fimc_is *is = fimc_isp_to_is(isp);
253*4882a593Smuzhiyun 	int ret;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	if (!test_bit(IS_ST_INIT_DONE, &is->state))
258*4882a593Smuzhiyun 		return -EBUSY;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	fimc_is_mem_barrier();
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	if (on) {
263*4882a593Smuzhiyun 		if (__get_pending_param_count(is)) {
264*4882a593Smuzhiyun 			ret = fimc_is_itf_s_param(is, true);
265*4882a593Smuzhiyun 			if (ret < 0)
266*4882a593Smuzhiyun 				return ret;
267*4882a593Smuzhiyun 		}
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 		isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 		ret = fimc_is_itf_mode_change(is);
272*4882a593Smuzhiyun 		if (ret)
273*4882a593Smuzhiyun 			return -EINVAL;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 		clear_bit(IS_ST_STREAM_ON, &is->state);
276*4882a593Smuzhiyun 		fimc_is_hw_stream_on(is);
277*4882a593Smuzhiyun 		ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
278*4882a593Smuzhiyun 					 FIMC_IS_CONFIG_TIMEOUT);
279*4882a593Smuzhiyun 		if (ret < 0) {
280*4882a593Smuzhiyun 			v4l2_err(sd, "stream on timeout\n");
281*4882a593Smuzhiyun 			return ret;
282*4882a593Smuzhiyun 		}
283*4882a593Smuzhiyun 	} else {
284*4882a593Smuzhiyun 		clear_bit(IS_ST_STREAM_OFF, &is->state);
285*4882a593Smuzhiyun 		fimc_is_hw_stream_off(is);
286*4882a593Smuzhiyun 		ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
287*4882a593Smuzhiyun 					 FIMC_IS_CONFIG_TIMEOUT);
288*4882a593Smuzhiyun 		if (ret < 0) {
289*4882a593Smuzhiyun 			v4l2_err(sd, "stream off timeout\n");
290*4882a593Smuzhiyun 			return ret;
291*4882a593Smuzhiyun 		}
292*4882a593Smuzhiyun 		is->setfile.sub_index = 0;
293*4882a593Smuzhiyun 	}
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
fimc_isp_subdev_s_power(struct v4l2_subdev * sd,int on)298*4882a593Smuzhiyun static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
301*4882a593Smuzhiyun 	struct fimc_is *is = fimc_isp_to_is(isp);
302*4882a593Smuzhiyun 	int ret = 0;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	pr_debug("on: %d\n", on);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	if (on) {
307*4882a593Smuzhiyun 		ret = pm_runtime_resume_and_get(&is->pdev->dev);
308*4882a593Smuzhiyun 		if (ret < 0)
309*4882a593Smuzhiyun 			return ret;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		set_bit(IS_ST_PWR_ON, &is->state);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 		ret = fimc_is_start_firmware(is);
314*4882a593Smuzhiyun 		if (ret < 0) {
315*4882a593Smuzhiyun 			v4l2_err(sd, "firmware booting failed\n");
316*4882a593Smuzhiyun 			pm_runtime_put(&is->pdev->dev);
317*4882a593Smuzhiyun 			return ret;
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 		set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 		ret = fimc_is_hw_initialize(is);
322*4882a593Smuzhiyun 	} else {
323*4882a593Smuzhiyun 		/* Close sensor */
324*4882a593Smuzhiyun 		if (!test_bit(IS_ST_PWR_ON, &is->state)) {
325*4882a593Smuzhiyun 			fimc_is_hw_close_sensor(is, 0);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 			ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
328*4882a593Smuzhiyun 						 FIMC_IS_CONFIG_TIMEOUT);
329*4882a593Smuzhiyun 			if (ret < 0) {
330*4882a593Smuzhiyun 				v4l2_err(sd, "sensor close timeout\n");
331*4882a593Smuzhiyun 				return ret;
332*4882a593Smuzhiyun 			}
333*4882a593Smuzhiyun 		}
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 		/* SUB IP power off */
336*4882a593Smuzhiyun 		if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
337*4882a593Smuzhiyun 			fimc_is_hw_subip_power_off(is);
338*4882a593Smuzhiyun 			ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
339*4882a593Smuzhiyun 						 FIMC_IS_CONFIG_TIMEOUT);
340*4882a593Smuzhiyun 			if (ret < 0) {
341*4882a593Smuzhiyun 				v4l2_err(sd, "sub-IP power off timeout\n");
342*4882a593Smuzhiyun 				return ret;
343*4882a593Smuzhiyun 			}
344*4882a593Smuzhiyun 		}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 		fimc_is_cpu_set_power(is, 0);
347*4882a593Smuzhiyun 		pm_runtime_put_sync(&is->pdev->dev);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 		clear_bit(IS_ST_PWR_ON, &is->state);
350*4882a593Smuzhiyun 		clear_bit(IS_ST_INIT_DONE, &is->state);
351*4882a593Smuzhiyun 		is->state = 0;
352*4882a593Smuzhiyun 		is->config[is->config_index].p_region_index[0] = 0;
353*4882a593Smuzhiyun 		is->config[is->config_index].p_region_index[1] = 0;
354*4882a593Smuzhiyun 		set_bit(IS_ST_IDLE, &is->state);
355*4882a593Smuzhiyun 		wmb();
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	return ret;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
fimc_isp_subdev_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)361*4882a593Smuzhiyun static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
362*4882a593Smuzhiyun 				struct v4l2_subdev_fh *fh)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *format;
365*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt fmt = {
366*4882a593Smuzhiyun 		.colorspace = V4L2_COLORSPACE_SRGB,
367*4882a593Smuzhiyun 		.code = fimc_isp_formats[0].mbus_code,
368*4882a593Smuzhiyun 		.width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH,
369*4882a593Smuzhiyun 		.height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT,
370*4882a593Smuzhiyun 		.field = V4L2_FIELD_NONE,
371*4882a593Smuzhiyun 	};
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SINK);
374*4882a593Smuzhiyun 	*format = fmt;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_FIFO);
377*4882a593Smuzhiyun 	fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
378*4882a593Smuzhiyun 	fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
379*4882a593Smuzhiyun 	*format = fmt;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_DMA);
382*4882a593Smuzhiyun 	*format = fmt;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	return 0;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun 
fimc_isp_subdev_registered(struct v4l2_subdev * sd)387*4882a593Smuzhiyun static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
390*4882a593Smuzhiyun 	int ret;
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	/* Use pipeline object allocated by the media device. */
393*4882a593Smuzhiyun 	isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
396*4882a593Smuzhiyun 			V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
397*4882a593Smuzhiyun 	if (ret < 0)
398*4882a593Smuzhiyun 		isp->video_capture.ve.pipe = NULL;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	return ret;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
fimc_isp_subdev_unregistered(struct v4l2_subdev * sd)403*4882a593Smuzhiyun static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct fimc_isp *isp = v4l2_get_subdevdata(sd);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	fimc_isp_video_device_unregister(isp,
408*4882a593Smuzhiyun 			V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
412*4882a593Smuzhiyun 	.registered = fimc_isp_subdev_registered,
413*4882a593Smuzhiyun 	.unregistered = fimc_isp_subdev_unregistered,
414*4882a593Smuzhiyun 	.open = fimc_isp_subdev_open,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
418*4882a593Smuzhiyun 	.enum_mbus_code = fimc_is_subdev_enum_mbus_code,
419*4882a593Smuzhiyun 	.get_fmt = fimc_isp_subdev_get_fmt,
420*4882a593Smuzhiyun 	.set_fmt = fimc_isp_subdev_set_fmt,
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
424*4882a593Smuzhiyun 	.s_stream = fimc_isp_subdev_s_stream,
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
428*4882a593Smuzhiyun 	.s_power = fimc_isp_subdev_s_power,
429*4882a593Smuzhiyun };
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
432*4882a593Smuzhiyun 	.core = &fimc_is_core_ops,
433*4882a593Smuzhiyun 	.video = &fimc_is_subdev_video_ops,
434*4882a593Smuzhiyun 	.pad = &fimc_is_subdev_pad_ops,
435*4882a593Smuzhiyun };
436*4882a593Smuzhiyun 
__ctrl_set_white_balance(struct fimc_is * is,int value)437*4882a593Smuzhiyun static int __ctrl_set_white_balance(struct fimc_is *is, int value)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun 	switch (value) {
440*4882a593Smuzhiyun 	case V4L2_WHITE_BALANCE_AUTO:
441*4882a593Smuzhiyun 		__is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
442*4882a593Smuzhiyun 		break;
443*4882a593Smuzhiyun 	case V4L2_WHITE_BALANCE_DAYLIGHT:
444*4882a593Smuzhiyun 		__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
445*4882a593Smuzhiyun 					ISP_AWB_ILLUMINATION_DAYLIGHT);
446*4882a593Smuzhiyun 		break;
447*4882a593Smuzhiyun 	case V4L2_WHITE_BALANCE_CLOUDY:
448*4882a593Smuzhiyun 		__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
449*4882a593Smuzhiyun 					ISP_AWB_ILLUMINATION_CLOUDY);
450*4882a593Smuzhiyun 		break;
451*4882a593Smuzhiyun 	case V4L2_WHITE_BALANCE_INCANDESCENT:
452*4882a593Smuzhiyun 		__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
453*4882a593Smuzhiyun 					ISP_AWB_ILLUMINATION_TUNGSTEN);
454*4882a593Smuzhiyun 		break;
455*4882a593Smuzhiyun 	case V4L2_WHITE_BALANCE_FLUORESCENT:
456*4882a593Smuzhiyun 		__is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
457*4882a593Smuzhiyun 					ISP_AWB_ILLUMINATION_FLUORESCENT);
458*4882a593Smuzhiyun 		break;
459*4882a593Smuzhiyun 	default:
460*4882a593Smuzhiyun 		return -EINVAL;
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	return 0;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
__ctrl_set_aewb_lock(struct fimc_is * is,struct v4l2_ctrl * ctrl)466*4882a593Smuzhiyun static int __ctrl_set_aewb_lock(struct fimc_is *is,
467*4882a593Smuzhiyun 				      struct v4l2_ctrl *ctrl)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
470*4882a593Smuzhiyun 	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
471*4882a593Smuzhiyun 	struct isp_param *isp = &is->is_p_region->parameter.isp;
472*4882a593Smuzhiyun 	int cmd, ret;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
475*4882a593Smuzhiyun 	isp->aa.cmd = cmd;
476*4882a593Smuzhiyun 	isp->aa.target = ISP_AA_TARGET_AE;
477*4882a593Smuzhiyun 	fimc_is_set_param_bit(is, PARAM_ISP_AA);
478*4882a593Smuzhiyun 	is->af.ae_lock_state = ae_lock;
479*4882a593Smuzhiyun 	wmb();
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	ret = fimc_is_itf_s_param(is, false);
482*4882a593Smuzhiyun 	if (ret < 0)
483*4882a593Smuzhiyun 		return ret;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
486*4882a593Smuzhiyun 	isp->aa.cmd = cmd;
487*4882a593Smuzhiyun 	isp->aa.target = ISP_AA_TARGET_AE;
488*4882a593Smuzhiyun 	fimc_is_set_param_bit(is, PARAM_ISP_AA);
489*4882a593Smuzhiyun 	is->af.awb_lock_state = awb_lock;
490*4882a593Smuzhiyun 	wmb();
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	return fimc_is_itf_s_param(is, false);
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /* Supported manual ISO values */
496*4882a593Smuzhiyun static const s64 iso_qmenu[] = {
497*4882a593Smuzhiyun 	50, 100, 200, 400, 800,
498*4882a593Smuzhiyun };
499*4882a593Smuzhiyun 
__ctrl_set_iso(struct fimc_is * is,int value)500*4882a593Smuzhiyun static int __ctrl_set_iso(struct fimc_is *is, int value)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	unsigned int idx, iso;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	if (value == V4L2_ISO_SENSITIVITY_AUTO) {
505*4882a593Smuzhiyun 		__is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
506*4882a593Smuzhiyun 		return 0;
507*4882a593Smuzhiyun 	}
508*4882a593Smuzhiyun 	idx = is->isp.ctrls.iso->val;
509*4882a593Smuzhiyun 	if (idx >= ARRAY_SIZE(iso_qmenu))
510*4882a593Smuzhiyun 		return -EINVAL;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	iso = iso_qmenu[idx];
513*4882a593Smuzhiyun 	__is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
514*4882a593Smuzhiyun 	return 0;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun 
__ctrl_set_metering(struct fimc_is * is,unsigned int value)517*4882a593Smuzhiyun static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	unsigned int val;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	switch (value) {
522*4882a593Smuzhiyun 	case V4L2_EXPOSURE_METERING_AVERAGE:
523*4882a593Smuzhiyun 		val = ISP_METERING_COMMAND_AVERAGE;
524*4882a593Smuzhiyun 		break;
525*4882a593Smuzhiyun 	case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
526*4882a593Smuzhiyun 		val = ISP_METERING_COMMAND_CENTER;
527*4882a593Smuzhiyun 		break;
528*4882a593Smuzhiyun 	case V4L2_EXPOSURE_METERING_SPOT:
529*4882a593Smuzhiyun 		val = ISP_METERING_COMMAND_SPOT;
530*4882a593Smuzhiyun 		break;
531*4882a593Smuzhiyun 	case V4L2_EXPOSURE_METERING_MATRIX:
532*4882a593Smuzhiyun 		val = ISP_METERING_COMMAND_MATRIX;
533*4882a593Smuzhiyun 		break;
534*4882a593Smuzhiyun 	default:
535*4882a593Smuzhiyun 		return -EINVAL;
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	__is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
539*4882a593Smuzhiyun 	return 0;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
__ctrl_set_afc(struct fimc_is * is,int value)542*4882a593Smuzhiyun static int __ctrl_set_afc(struct fimc_is *is, int value)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	switch (value) {
545*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
546*4882a593Smuzhiyun 		__is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
547*4882a593Smuzhiyun 		break;
548*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
549*4882a593Smuzhiyun 		__is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
550*4882a593Smuzhiyun 		break;
551*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
552*4882a593Smuzhiyun 		__is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
553*4882a593Smuzhiyun 		break;
554*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
555*4882a593Smuzhiyun 		__is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
556*4882a593Smuzhiyun 		break;
557*4882a593Smuzhiyun 	default:
558*4882a593Smuzhiyun 		return -EINVAL;
559*4882a593Smuzhiyun 	}
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	return 0;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
__ctrl_set_image_effect(struct fimc_is * is,int value)564*4882a593Smuzhiyun static int __ctrl_set_image_effect(struct fimc_is *is, int value)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	static const u8 effects[][2] = {
567*4882a593Smuzhiyun 		{ V4L2_COLORFX_NONE,	 ISP_IMAGE_EFFECT_DISABLE },
568*4882a593Smuzhiyun 		{ V4L2_COLORFX_BW,	 ISP_IMAGE_EFFECT_MONOCHROME },
569*4882a593Smuzhiyun 		{ V4L2_COLORFX_SEPIA,	 ISP_IMAGE_EFFECT_SEPIA },
570*4882a593Smuzhiyun 		{ V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
571*4882a593Smuzhiyun 		{ 16 /* TODO */,	 ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
572*4882a593Smuzhiyun 	};
573*4882a593Smuzhiyun 	int i;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(effects); i++) {
576*4882a593Smuzhiyun 		if (effects[i][0] != value)
577*4882a593Smuzhiyun 			continue;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 		__is_set_isp_effect(is, effects[i][1]);
580*4882a593Smuzhiyun 		return 0;
581*4882a593Smuzhiyun 	}
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	return -EINVAL;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun 
fimc_is_s_ctrl(struct v4l2_ctrl * ctrl)586*4882a593Smuzhiyun static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun 	struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
589*4882a593Smuzhiyun 	struct fimc_is *is = fimc_isp_to_is(isp);
590*4882a593Smuzhiyun 	bool set_param = true;
591*4882a593Smuzhiyun 	int ret = 0;
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	switch (ctrl->id) {
594*4882a593Smuzhiyun 	case V4L2_CID_CONTRAST:
595*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
596*4882a593Smuzhiyun 				    ctrl->val);
597*4882a593Smuzhiyun 		break;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	case V4L2_CID_SATURATION:
600*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
601*4882a593Smuzhiyun 				    ctrl->val);
602*4882a593Smuzhiyun 		break;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	case V4L2_CID_SHARPNESS:
605*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
606*4882a593Smuzhiyun 				    ctrl->val);
607*4882a593Smuzhiyun 		break;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_ABSOLUTE:
610*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
611*4882a593Smuzhiyun 				    ctrl->val);
612*4882a593Smuzhiyun 		break;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	case V4L2_CID_BRIGHTNESS:
615*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
616*4882a593Smuzhiyun 				    ctrl->val);
617*4882a593Smuzhiyun 		break;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	case V4L2_CID_HUE:
620*4882a593Smuzhiyun 		__is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
621*4882a593Smuzhiyun 				    ctrl->val);
622*4882a593Smuzhiyun 		break;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_METERING:
625*4882a593Smuzhiyun 		ret = __ctrl_set_metering(is, ctrl->val);
626*4882a593Smuzhiyun 		break;
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
629*4882a593Smuzhiyun 		ret = __ctrl_set_white_balance(is, ctrl->val);
630*4882a593Smuzhiyun 		break;
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	case V4L2_CID_3A_LOCK:
633*4882a593Smuzhiyun 		ret = __ctrl_set_aewb_lock(is, ctrl);
634*4882a593Smuzhiyun 		set_param = false;
635*4882a593Smuzhiyun 		break;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	case V4L2_CID_ISO_SENSITIVITY_AUTO:
638*4882a593Smuzhiyun 		ret = __ctrl_set_iso(is, ctrl->val);
639*4882a593Smuzhiyun 		break;
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY:
642*4882a593Smuzhiyun 		ret = __ctrl_set_afc(is, ctrl->val);
643*4882a593Smuzhiyun 		break;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	case V4L2_CID_COLORFX:
646*4882a593Smuzhiyun 		__ctrl_set_image_effect(is, ctrl->val);
647*4882a593Smuzhiyun 		break;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	default:
650*4882a593Smuzhiyun 		ret = -EINVAL;
651*4882a593Smuzhiyun 		break;
652*4882a593Smuzhiyun 	}
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	if (ret < 0) {
655*4882a593Smuzhiyun 		v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
656*4882a593Smuzhiyun 						ctrl->name, ctrl->val);
657*4882a593Smuzhiyun 		return ret;
658*4882a593Smuzhiyun 	}
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
661*4882a593Smuzhiyun 		return fimc_is_itf_s_param(is, true);
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	return 0;
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
667*4882a593Smuzhiyun 	.s_ctrl	= fimc_is_s_ctrl,
668*4882a593Smuzhiyun };
669*4882a593Smuzhiyun 
__isp_subdev_set_default_format(struct fimc_isp * isp)670*4882a593Smuzhiyun static void __isp_subdev_set_default_format(struct fimc_isp *isp)
671*4882a593Smuzhiyun {
672*4882a593Smuzhiyun 	struct fimc_is *is = fimc_isp_to_is(isp);
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	isp->sink_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH +
675*4882a593Smuzhiyun 				FIMC_ISP_CAC_MARGIN_WIDTH;
676*4882a593Smuzhiyun 	isp->sink_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT +
677*4882a593Smuzhiyun 				FIMC_ISP_CAC_MARGIN_HEIGHT;
678*4882a593Smuzhiyun 	isp->sink_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	isp->src_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
681*4882a593Smuzhiyun 	isp->src_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
682*4882a593Smuzhiyun 	isp->src_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
683*4882a593Smuzhiyun 	__is_set_frame_size(is, &isp->src_fmt);
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
fimc_isp_subdev_create(struct fimc_isp * isp)686*4882a593Smuzhiyun int fimc_isp_subdev_create(struct fimc_isp *isp)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun 	const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
689*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
690*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &isp->subdev;
691*4882a593Smuzhiyun 	struct fimc_isp_ctrls *ctrls = &isp->ctrls;
692*4882a593Smuzhiyun 	int ret;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	mutex_init(&isp->subdev_lock);
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	v4l2_subdev_init(sd, &fimc_is_subdev_ops);
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun 	sd->owner = THIS_MODULE;
699*4882a593Smuzhiyun 	sd->grp_id = GRP_ID_FIMC_IS;
700*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
701*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
704*4882a593Smuzhiyun 	isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
705*4882a593Smuzhiyun 	isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
706*4882a593Smuzhiyun 	isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
707*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
708*4882a593Smuzhiyun 				isp->subdev_pads);
709*4882a593Smuzhiyun 	if (ret)
710*4882a593Smuzhiyun 		return ret;
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(handler, 20);
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
715*4882a593Smuzhiyun 						-2, 2, 1, 0);
716*4882a593Smuzhiyun 	ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
717*4882a593Smuzhiyun 						-4, 4, 1, 0);
718*4882a593Smuzhiyun 	ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
719*4882a593Smuzhiyun 						-2, 2, 1, 0);
720*4882a593Smuzhiyun 	ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
721*4882a593Smuzhiyun 						-2, 2, 1, 0);
722*4882a593Smuzhiyun 	ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
723*4882a593Smuzhiyun 						-2, 2, 1, 0);
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
726*4882a593Smuzhiyun 					V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
727*4882a593Smuzhiyun 					8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
730*4882a593Smuzhiyun 					V4L2_CID_EXPOSURE_ABSOLUTE,
731*4882a593Smuzhiyun 					-4, 4, 1, 0);
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
734*4882a593Smuzhiyun 					V4L2_CID_EXPOSURE_METERING, 3,
735*4882a593Smuzhiyun 					~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
738*4882a593Smuzhiyun 					V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
739*4882a593Smuzhiyun 					V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
740*4882a593Smuzhiyun 	/* ISO sensitivity */
741*4882a593Smuzhiyun 	ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
742*4882a593Smuzhiyun 			V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
743*4882a593Smuzhiyun 			V4L2_ISO_SENSITIVITY_AUTO);
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
746*4882a593Smuzhiyun 			V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
747*4882a593Smuzhiyun 			ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
750*4882a593Smuzhiyun 					V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	/* TODO: Add support for NEGATIVE_COLOR option */
753*4882a593Smuzhiyun 	ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
754*4882a593Smuzhiyun 			V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 	if (handler->error) {
757*4882a593Smuzhiyun 		media_entity_cleanup(&sd->entity);
758*4882a593Smuzhiyun 		return handler->error;
759*4882a593Smuzhiyun 	}
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
762*4882a593Smuzhiyun 			V4L2_ISO_SENSITIVITY_MANUAL, false);
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun 	sd->ctrl_handler = handler;
765*4882a593Smuzhiyun 	sd->internal_ops = &fimc_is_subdev_internal_ops;
766*4882a593Smuzhiyun 	sd->entity.ops = &fimc_is_subdev_media_ops;
767*4882a593Smuzhiyun 	v4l2_set_subdevdata(sd, isp);
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	__isp_subdev_set_default_format(isp);
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 	return 0;
772*4882a593Smuzhiyun }
773*4882a593Smuzhiyun 
fimc_isp_subdev_destroy(struct fimc_isp * isp)774*4882a593Smuzhiyun void fimc_isp_subdev_destroy(struct fimc_isp *isp)
775*4882a593Smuzhiyun {
776*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &isp->subdev;
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
779*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
780*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&isp->ctrls.handler);
781*4882a593Smuzhiyun 	v4l2_set_subdevdata(sd, NULL);
782*4882a593Smuzhiyun }
783