1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Samsung Exynos4x12 FIMC-IS (Imaging Subsystem) driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * FIMC-IS command set definitions 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2013 Samsung Electronics Co., Ltd. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Authors: Younghwan Joo <yhwan.joo@samsung.com> 10*4882a593Smuzhiyun * Sylwester Nawrocki <s.nawrocki@samsung.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef FIMC_IS_CMD_H_ 14*4882a593Smuzhiyun #define FIMC_IS_CMD_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define FIMC_IS_COMMAND_VER 110 /* FIMC-IS command set version 1.10 */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Enumeration of commands between the FIMC-IS and the host processor. */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* HOST to FIMC-IS */ 21*4882a593Smuzhiyun #define HIC_PREVIEW_STILL 0x0001 22*4882a593Smuzhiyun #define HIC_PREVIEW_VIDEO 0x0002 23*4882a593Smuzhiyun #define HIC_CAPTURE_STILL 0x0003 24*4882a593Smuzhiyun #define HIC_CAPTURE_VIDEO 0x0004 25*4882a593Smuzhiyun #define HIC_STREAM_ON 0x0005 26*4882a593Smuzhiyun #define HIC_STREAM_OFF 0x0006 27*4882a593Smuzhiyun #define HIC_SET_PARAMETER 0x0007 28*4882a593Smuzhiyun #define HIC_GET_PARAMETER 0x0008 29*4882a593Smuzhiyun #define HIC_SET_TUNE 0x0009 30*4882a593Smuzhiyun #define HIC_GET_STATUS 0x000b 31*4882a593Smuzhiyun /* Sensor part */ 32*4882a593Smuzhiyun #define HIC_OPEN_SENSOR 0x000c 33*4882a593Smuzhiyun #define HIC_CLOSE_SENSOR 0x000d 34*4882a593Smuzhiyun #define HIC_SIMMIAN_INIT 0x000e 35*4882a593Smuzhiyun #define HIC_SIMMIAN_WRITE 0x000f 36*4882a593Smuzhiyun #define HIC_SIMMIAN_READ 0x0010 37*4882a593Smuzhiyun #define HIC_POWER_DOWN 0x0011 38*4882a593Smuzhiyun #define HIC_GET_SET_FILE_ADDR 0x0012 39*4882a593Smuzhiyun #define HIC_LOAD_SET_FILE 0x0013 40*4882a593Smuzhiyun #define HIC_MSG_CONFIG 0x0014 41*4882a593Smuzhiyun #define HIC_MSG_TEST 0x0015 42*4882a593Smuzhiyun /* FIMC-IS to HOST */ 43*4882a593Smuzhiyun #define IHC_GET_SENSOR_NUM 0x1000 44*4882a593Smuzhiyun #define IHC_SET_SHOT_MARK 0x1001 45*4882a593Smuzhiyun /* parameter1: frame number */ 46*4882a593Smuzhiyun /* parameter2: confidence level (smile 0~100) */ 47*4882a593Smuzhiyun /* parameter3: confidence level (blink 0~100) */ 48*4882a593Smuzhiyun #define IHC_SET_FACE_MARK 0x1002 49*4882a593Smuzhiyun /* parameter1: coordinate count */ 50*4882a593Smuzhiyun /* parameter2: coordinate buffer address */ 51*4882a593Smuzhiyun #define IHC_FRAME_DONE 0x1003 52*4882a593Smuzhiyun /* parameter1: frame start number */ 53*4882a593Smuzhiyun /* parameter2: frame count */ 54*4882a593Smuzhiyun #define IHC_AA_DONE 0x1004 55*4882a593Smuzhiyun #define IHC_NOT_READY 0x1005 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define IH_REPLY_DONE 0x2000 58*4882a593Smuzhiyun #define IH_REPLY_NOT_DONE 0x2001 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun enum fimc_is_scenario { 61*4882a593Smuzhiyun IS_SC_PREVIEW_STILL, 62*4882a593Smuzhiyun IS_SC_PREVIEW_VIDEO, 63*4882a593Smuzhiyun IS_SC_CAPTURE_STILL, 64*4882a593Smuzhiyun IS_SC_CAPTURE_VIDEO, 65*4882a593Smuzhiyun IS_SC_MAX 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun enum fimc_is_sub_scenario { 69*4882a593Smuzhiyun IS_SC_SUB_DEFAULT, 70*4882a593Smuzhiyun IS_SC_SUB_PS_VTCALL, 71*4882a593Smuzhiyun IS_SC_SUB_CS_VTCALL, 72*4882a593Smuzhiyun IS_SC_SUB_PV_VTCALL, 73*4882a593Smuzhiyun IS_SC_SUB_CV_VTCALL, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct is_common_regs { 77*4882a593Smuzhiyun u32 hicmd; 78*4882a593Smuzhiyun u32 hic_sensorid; 79*4882a593Smuzhiyun u32 hic_param[4]; 80*4882a593Smuzhiyun u32 reserved1[4]; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun u32 ihcmd; 83*4882a593Smuzhiyun u32 ihc_sensorid; 84*4882a593Smuzhiyun u32 ihc_param[4]; 85*4882a593Smuzhiyun u32 reserved2[4]; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun u32 isp_sensor_id; 88*4882a593Smuzhiyun u32 isp_param[2]; 89*4882a593Smuzhiyun u32 reserved3[1]; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun u32 scc_sensor_id; 92*4882a593Smuzhiyun u32 scc_param[2]; 93*4882a593Smuzhiyun u32 reserved4[1]; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun u32 dnr_sensor_id; 96*4882a593Smuzhiyun u32 dnr_param[2]; 97*4882a593Smuzhiyun u32 reserved5[1]; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun u32 scp_sensor_id; 100*4882a593Smuzhiyun u32 scp_param[2]; 101*4882a593Smuzhiyun u32 reserved6[29]; 102*4882a593Smuzhiyun } __packed; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct is_mcuctl_reg { 105*4882a593Smuzhiyun u32 mcuctl; 106*4882a593Smuzhiyun u32 bboar; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun u32 intgr0; 109*4882a593Smuzhiyun u32 intcr0; 110*4882a593Smuzhiyun u32 intmr0; 111*4882a593Smuzhiyun u32 intsr0; 112*4882a593Smuzhiyun u32 intmsr0; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 intgr1; 115*4882a593Smuzhiyun u32 intcr1; 116*4882a593Smuzhiyun u32 intmr1; 117*4882a593Smuzhiyun u32 intsr1; 118*4882a593Smuzhiyun u32 intmsr1; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun u32 intcr2; 121*4882a593Smuzhiyun u32 intmr2; 122*4882a593Smuzhiyun u32 intsr2; 123*4882a593Smuzhiyun u32 intmsr2; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun u32 gpoctrl; 126*4882a593Smuzhiyun u32 cpoenctlr; 127*4882a593Smuzhiyun u32 gpictlr; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun u32 reserved[0xd]; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun struct is_common_regs common; 132*4882a593Smuzhiyun } __packed; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* FIMC_IS_CMD_H_ */ 135