1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments Inc
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/ctype.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/videodev2.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/platform_data/i2c-davinci.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <media/davinci/vpbe_types.h>
22*4882a593Smuzhiyun #include <media/davinci/vpbe_venc.h>
23*4882a593Smuzhiyun #include <media/davinci/vpss.h>
24*4882a593Smuzhiyun #include <media/v4l2-device.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "vpbe_venc_regs.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MODULE_NAME "davinci-vpbe-venc"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static const struct platform_device_id vpbe_venc_devtype[] = {
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun .name = DM644X_VPBE_VENC_SUBDEV_NAME,
33*4882a593Smuzhiyun .driver_data = VPBE_VERSION_1,
34*4882a593Smuzhiyun }, {
35*4882a593Smuzhiyun .name = DM365_VPBE_VENC_SUBDEV_NAME,
36*4882a593Smuzhiyun .driver_data = VPBE_VERSION_2,
37*4882a593Smuzhiyun }, {
38*4882a593Smuzhiyun .name = DM355_VPBE_VENC_SUBDEV_NAME,
39*4882a593Smuzhiyun .driver_data = VPBE_VERSION_3,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun /* sentinel */
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, vpbe_venc_devtype);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static int debug = 2;
49*4882a593Smuzhiyun module_param(debug, int, 0644);
50*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level 0-2");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct venc_state {
53*4882a593Smuzhiyun struct v4l2_subdev sd;
54*4882a593Smuzhiyun struct venc_callback *callback;
55*4882a593Smuzhiyun struct venc_platform_data *pdata;
56*4882a593Smuzhiyun struct device *pdev;
57*4882a593Smuzhiyun u32 output;
58*4882a593Smuzhiyun v4l2_std_id std;
59*4882a593Smuzhiyun spinlock_t lock;
60*4882a593Smuzhiyun void __iomem *venc_base;
61*4882a593Smuzhiyun void __iomem *vdaccfg_reg;
62*4882a593Smuzhiyun enum vpbe_version venc_type;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
to_state(struct v4l2_subdev * sd)65*4882a593Smuzhiyun static inline struct venc_state *to_state(struct v4l2_subdev *sd)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return container_of(sd, struct venc_state, sd);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
venc_read(struct v4l2_subdev * sd,u32 offset)70*4882a593Smuzhiyun static inline u32 venc_read(struct v4l2_subdev *sd, u32 offset)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return readl(venc->venc_base + offset);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
venc_write(struct v4l2_subdev * sd,u32 offset,u32 val)77*4882a593Smuzhiyun static inline u32 venc_write(struct v4l2_subdev *sd, u32 offset, u32 val)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun writel(val, (venc->venc_base + offset));
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return val;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
venc_modify(struct v4l2_subdev * sd,u32 offset,u32 val,u32 mask)86*4882a593Smuzhiyun static inline u32 venc_modify(struct v4l2_subdev *sd, u32 offset,
87*4882a593Smuzhiyun u32 val, u32 mask)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun u32 new_val = (venc_read(sd, offset) & ~mask) | (val & mask);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun venc_write(sd, offset, new_val);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return new_val;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
vdaccfg_write(struct v4l2_subdev * sd,u32 val)96*4882a593Smuzhiyun static inline u32 vdaccfg_write(struct v4l2_subdev *sd, u32 val)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun writel(val, venc->vdaccfg_reg);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun val = readl(venc->vdaccfg_reg);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return val;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define VDAC_COMPONENT 0x543
108*4882a593Smuzhiyun #define VDAC_S_VIDEO 0x210
109*4882a593Smuzhiyun /* This function sets the dac of the VPBE for various outputs
110*4882a593Smuzhiyun */
venc_set_dac(struct v4l2_subdev * sd,u32 out_index)111*4882a593Smuzhiyun static int venc_set_dac(struct v4l2_subdev *sd, u32 out_index)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun switch (out_index) {
114*4882a593Smuzhiyun case 0:
115*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "Setting output to Composite\n");
116*4882a593Smuzhiyun venc_write(sd, VENC_DACSEL, 0);
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun case 1:
119*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "Setting output to Component\n");
120*4882a593Smuzhiyun venc_write(sd, VENC_DACSEL, VDAC_COMPONENT);
121*4882a593Smuzhiyun break;
122*4882a593Smuzhiyun case 2:
123*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "Setting output to S-video\n");
124*4882a593Smuzhiyun venc_write(sd, VENC_DACSEL, VDAC_S_VIDEO);
125*4882a593Smuzhiyun break;
126*4882a593Smuzhiyun default:
127*4882a593Smuzhiyun return -EINVAL;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
venc_enabledigitaloutput(struct v4l2_subdev * sd,int benable)133*4882a593Smuzhiyun static void venc_enabledigitaloutput(struct v4l2_subdev *sd, int benable)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun v4l2_dbg(debug, 2, sd, "venc_enabledigitaloutput\n");
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (benable) {
140*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
141*4882a593Smuzhiyun venc_write(sd, VENC_CVBS, 0);
142*4882a593Smuzhiyun venc_write(sd, VENC_LCDOUT, 0);
143*4882a593Smuzhiyun venc_write(sd, VENC_HSPLS, 0);
144*4882a593Smuzhiyun venc_write(sd, VENC_HSTART, 0);
145*4882a593Smuzhiyun venc_write(sd, VENC_HVALID, 0);
146*4882a593Smuzhiyun venc_write(sd, VENC_HINT, 0);
147*4882a593Smuzhiyun venc_write(sd, VENC_VSPLS, 0);
148*4882a593Smuzhiyun venc_write(sd, VENC_VSTART, 0);
149*4882a593Smuzhiyun venc_write(sd, VENC_VVALID, 0);
150*4882a593Smuzhiyun venc_write(sd, VENC_VINT, 0);
151*4882a593Smuzhiyun venc_write(sd, VENC_YCCCTL, 0);
152*4882a593Smuzhiyun venc_write(sd, VENC_DACSEL, 0);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun } else {
155*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
156*4882a593Smuzhiyun /* disable VCLK output pin enable */
157*4882a593Smuzhiyun venc_write(sd, VENC_VIDCTL, 0x141);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* Disable output sync pins */
160*4882a593Smuzhiyun venc_write(sd, VENC_SYNCCTL, 0);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Disable DCLOCK */
163*4882a593Smuzhiyun venc_write(sd, VENC_DCLKCTL, 0);
164*4882a593Smuzhiyun venc_write(sd, VENC_DRGBX1, 0x0000057C);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /* Disable LCD output control (accepting default polarity) */
167*4882a593Smuzhiyun venc_write(sd, VENC_LCDOUT, 0);
168*4882a593Smuzhiyun if (venc->venc_type != VPBE_VERSION_3)
169*4882a593Smuzhiyun venc_write(sd, VENC_CMPNT, 0x100);
170*4882a593Smuzhiyun venc_write(sd, VENC_HSPLS, 0);
171*4882a593Smuzhiyun venc_write(sd, VENC_HINT, 0);
172*4882a593Smuzhiyun venc_write(sd, VENC_HSTART, 0);
173*4882a593Smuzhiyun venc_write(sd, VENC_HVALID, 0);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun venc_write(sd, VENC_VSPLS, 0);
176*4882a593Smuzhiyun venc_write(sd, VENC_VINT, 0);
177*4882a593Smuzhiyun venc_write(sd, VENC_VSTART, 0);
178*4882a593Smuzhiyun venc_write(sd, VENC_VVALID, 0);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun venc_write(sd, VENC_HSDLY, 0);
181*4882a593Smuzhiyun venc_write(sd, VENC_VSDLY, 0);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun venc_write(sd, VENC_YCCCTL, 0);
184*4882a593Smuzhiyun venc_write(sd, VENC_VSTARTA, 0);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Set OSD clock and OSD Sync Adavance registers */
187*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK0, 1);
188*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK1, 2);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static void
venc_enable_vpss_clock(int venc_type,enum vpbe_enc_timings_type type,unsigned int pclock)193*4882a593Smuzhiyun venc_enable_vpss_clock(int venc_type,
194*4882a593Smuzhiyun enum vpbe_enc_timings_type type,
195*4882a593Smuzhiyun unsigned int pclock)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun if (venc_type == VPBE_VERSION_1)
198*4882a593Smuzhiyun return;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (venc_type == VPBE_VERSION_2 && (type == VPBE_ENC_STD || (type ==
201*4882a593Smuzhiyun VPBE_ENC_DV_TIMINGS && pclock <= 27000000))) {
202*4882a593Smuzhiyun vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
203*4882a593Smuzhiyun vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
204*4882a593Smuzhiyun return;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun if (venc_type == VPBE_VERSION_3 && type == VPBE_ENC_STD)
208*4882a593Smuzhiyun vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 0);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #define VDAC_CONFIG_SD_V3 0x0E21A6B6
212*4882a593Smuzhiyun #define VDAC_CONFIG_SD_V2 0x081141CF
213*4882a593Smuzhiyun /*
214*4882a593Smuzhiyun * setting NTSC mode
215*4882a593Smuzhiyun */
venc_set_ntsc(struct v4l2_subdev * sd)216*4882a593Smuzhiyun static int venc_set_ntsc(struct v4l2_subdev *sd)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
219*4882a593Smuzhiyun struct venc_platform_data *pdata = venc->pdata;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun v4l2_dbg(debug, 2, sd, "venc_set_ntsc\n");
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Setup clock at VPSS & VENC for SD */
224*4882a593Smuzhiyun vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
225*4882a593Smuzhiyun if (pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_525_60) < 0)
226*4882a593Smuzhiyun return -EINVAL;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_525_60);
229*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_3) {
232*4882a593Smuzhiyun venc_write(sd, VENC_CLKCTL, 0x01);
233*4882a593Smuzhiyun venc_write(sd, VENC_VIDCTL, 0);
234*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
235*4882a593Smuzhiyun } else if (venc->venc_type == VPBE_VERSION_2) {
236*4882a593Smuzhiyun venc_write(sd, VENC_CLKCTL, 0x01);
237*4882a593Smuzhiyun venc_write(sd, VENC_VIDCTL, 0);
238*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
239*4882a593Smuzhiyun } else {
240*4882a593Smuzhiyun /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
241*4882a593Smuzhiyun venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
242*4882a593Smuzhiyun /* Set REC656 Mode */
243*4882a593Smuzhiyun venc_write(sd, VENC_YCCCTL, 0x1);
244*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAFRQ);
245*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, 0, VENC_VDPRO_DAUPS);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
249*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
250*4882a593Smuzhiyun VENC_VMOD_VIE);
251*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
252*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (0 << VENC_VMOD_TVTYP_SHIFT),
253*4882a593Smuzhiyun VENC_VMOD_TVTYP);
254*4882a593Smuzhiyun venc_write(sd, VENC_DACTST, 0x0);
255*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun return 0;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun /*
261*4882a593Smuzhiyun * setting PAL mode
262*4882a593Smuzhiyun */
venc_set_pal(struct v4l2_subdev * sd)263*4882a593Smuzhiyun static int venc_set_pal(struct v4l2_subdev *sd)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun v4l2_dbg(debug, 2, sd, "venc_set_pal\n");
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Setup clock at VPSS & VENC for SD */
270*4882a593Smuzhiyun vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
271*4882a593Smuzhiyun if (venc->pdata->setup_clock(VPBE_ENC_STD, V4L2_STD_625_50) < 0)
272*4882a593Smuzhiyun return -EINVAL;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_STD, V4L2_STD_625_50);
275*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_3) {
278*4882a593Smuzhiyun venc_write(sd, VENC_CLKCTL, 0x1);
279*4882a593Smuzhiyun venc_write(sd, VENC_VIDCTL, 0);
280*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_SD_V3);
281*4882a593Smuzhiyun } else if (venc->venc_type == VPBE_VERSION_2) {
282*4882a593Smuzhiyun venc_write(sd, VENC_CLKCTL, 0x1);
283*4882a593Smuzhiyun venc_write(sd, VENC_VIDCTL, 0);
284*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_SD_V2);
285*4882a593Smuzhiyun } else {
286*4882a593Smuzhiyun /* to set VENC CLK DIV to 1 - final clock is 54 MHz */
287*4882a593Smuzhiyun venc_modify(sd, VENC_VIDCTL, 0, 1 << 1);
288*4882a593Smuzhiyun /* Set REC656 Mode */
289*4882a593Smuzhiyun venc_write(sd, VENC_YCCCTL, 0x1);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun venc_modify(sd, VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
293*4882a593Smuzhiyun VENC_SYNCCTL_OVD);
294*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
295*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD,
296*4882a593Smuzhiyun (1 << VENC_VMOD_VIE_SHIFT),
297*4882a593Smuzhiyun VENC_VMOD_VIE);
298*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD,
299*4882a593Smuzhiyun (0 << VENC_VMOD_VMD), VENC_VMOD_VMD);
300*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD,
301*4882a593Smuzhiyun (1 << VENC_VMOD_TVTYP_SHIFT),
302*4882a593Smuzhiyun VENC_VMOD_TVTYP);
303*4882a593Smuzhiyun venc_write(sd, VENC_DACTST, 0x0);
304*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun #define VDAC_CONFIG_HD_V2 0x081141EF
310*4882a593Smuzhiyun /*
311*4882a593Smuzhiyun * venc_set_480p59_94
312*4882a593Smuzhiyun *
313*4882a593Smuzhiyun * This function configures the video encoder to EDTV(525p) component setting.
314*4882a593Smuzhiyun */
venc_set_480p59_94(struct v4l2_subdev * sd)315*4882a593Smuzhiyun static int venc_set_480p59_94(struct v4l2_subdev *sd)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
318*4882a593Smuzhiyun struct venc_platform_data *pdata = venc->pdata;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun v4l2_dbg(debug, 2, sd, "venc_set_480p59_94\n");
321*4882a593Smuzhiyun if (venc->venc_type != VPBE_VERSION_1 &&
322*4882a593Smuzhiyun venc->venc_type != VPBE_VERSION_2)
323*4882a593Smuzhiyun return -EINVAL;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Setup clock at VPSS & VENC for SD */
326*4882a593Smuzhiyun if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
327*4882a593Smuzhiyun return -EINVAL;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
330*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_2)
333*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
334*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK0, 0);
335*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK1, 1);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_1) {
338*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
339*4882a593Smuzhiyun VENC_VDPRO_DAFRQ);
340*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
341*4882a593Smuzhiyun VENC_VDPRO_DAUPS);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
345*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
346*4882a593Smuzhiyun VENC_VMOD_VIE);
347*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
348*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (HDTV_525P << VENC_VMOD_TVTYP_SHIFT),
349*4882a593Smuzhiyun VENC_VMOD_TVTYP);
350*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
351*4882a593Smuzhiyun VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * venc_set_625p
360*4882a593Smuzhiyun *
361*4882a593Smuzhiyun * This function configures the video encoder to HDTV(625p) component setting
362*4882a593Smuzhiyun */
venc_set_576p50(struct v4l2_subdev * sd)363*4882a593Smuzhiyun static int venc_set_576p50(struct v4l2_subdev *sd)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
366*4882a593Smuzhiyun struct venc_platform_data *pdata = venc->pdata;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun v4l2_dbg(debug, 2, sd, "venc_set_576p50\n");
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (venc->venc_type != VPBE_VERSION_1 &&
371*4882a593Smuzhiyun venc->venc_type != VPBE_VERSION_2)
372*4882a593Smuzhiyun return -EINVAL;
373*4882a593Smuzhiyun /* Setup clock at VPSS & VENC for SD */
374*4882a593Smuzhiyun if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 27000000) < 0)
375*4882a593Smuzhiyun return -EINVAL;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 27000000);
378*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_2)
381*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK0, 0);
384*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK1, 1);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun if (venc->venc_type == VPBE_VERSION_1) {
387*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAFRQ,
388*4882a593Smuzhiyun VENC_VDPRO_DAFRQ);
389*4882a593Smuzhiyun venc_modify(sd, VENC_VDPRO, VENC_VDPRO_DAUPS,
390*4882a593Smuzhiyun VENC_VDPRO_DAUPS);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
394*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
395*4882a593Smuzhiyun VENC_VMOD_VIE);
396*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
397*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (HDTV_625P << VENC_VMOD_TVTYP_SHIFT),
398*4882a593Smuzhiyun VENC_VMOD_TVTYP);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VDMD_YCBCR8 <<
401*4882a593Smuzhiyun VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
402*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun return 0;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /*
408*4882a593Smuzhiyun * venc_set_720p60_internal - Setup 720p60 in venc for dm365 only
409*4882a593Smuzhiyun */
venc_set_720p60_internal(struct v4l2_subdev * sd)410*4882a593Smuzhiyun static int venc_set_720p60_internal(struct v4l2_subdev *sd)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
413*4882a593Smuzhiyun struct venc_platform_data *pdata = venc->pdata;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
416*4882a593Smuzhiyun return -EINVAL;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
419*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK0, 0);
422*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK1, 1);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
425*4882a593Smuzhiyun /* DM365 component HD mode */
426*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
427*4882a593Smuzhiyun VENC_VMOD_VIE);
428*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
429*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (HDTV_720P << VENC_VMOD_TVTYP_SHIFT),
430*4882a593Smuzhiyun VENC_VMOD_TVTYP);
431*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
432*4882a593Smuzhiyun venc_write(sd, VENC_XHINTVL, 0);
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /*
437*4882a593Smuzhiyun * venc_set_1080i30_internal - Setup 1080i30 in venc for dm365 only
438*4882a593Smuzhiyun */
venc_set_1080i30_internal(struct v4l2_subdev * sd)439*4882a593Smuzhiyun static int venc_set_1080i30_internal(struct v4l2_subdev *sd)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
442*4882a593Smuzhiyun struct venc_platform_data *pdata = venc->pdata;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun if (pdata->setup_clock(VPBE_ENC_DV_TIMINGS, 74250000) < 0)
445*4882a593Smuzhiyun return -EINVAL;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun venc_enable_vpss_clock(venc->venc_type, VPBE_ENC_DV_TIMINGS, 74250000);
448*4882a593Smuzhiyun venc_enabledigitaloutput(sd, 0);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK0, 0);
451*4882a593Smuzhiyun venc_write(sd, VENC_OSDCLK1, 1);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun venc_write(sd, VENC_VMOD, 0);
455*4882a593Smuzhiyun /* DM365 component HD mode */
456*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (1 << VENC_VMOD_VIE_SHIFT),
457*4882a593Smuzhiyun VENC_VMOD_VIE);
458*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
459*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, (HDTV_1080I << VENC_VMOD_TVTYP_SHIFT),
460*4882a593Smuzhiyun VENC_VMOD_TVTYP);
461*4882a593Smuzhiyun venc_modify(sd, VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
462*4882a593Smuzhiyun venc_write(sd, VENC_XHINTVL, 0);
463*4882a593Smuzhiyun return 0;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
venc_s_std_output(struct v4l2_subdev * sd,v4l2_std_id norm)466*4882a593Smuzhiyun static int venc_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "venc_s_std_output\n");
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (norm & V4L2_STD_525_60)
471*4882a593Smuzhiyun return venc_set_ntsc(sd);
472*4882a593Smuzhiyun else if (norm & V4L2_STD_625_50)
473*4882a593Smuzhiyun return venc_set_pal(sd);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun return -EINVAL;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
venc_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * dv_timings)478*4882a593Smuzhiyun static int venc_s_dv_timings(struct v4l2_subdev *sd,
479*4882a593Smuzhiyun struct v4l2_dv_timings *dv_timings)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
482*4882a593Smuzhiyun u32 height = dv_timings->bt.height;
483*4882a593Smuzhiyun int ret;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "venc_s_dv_timings\n");
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun if (height == 576)
488*4882a593Smuzhiyun return venc_set_576p50(sd);
489*4882a593Smuzhiyun else if (height == 480)
490*4882a593Smuzhiyun return venc_set_480p59_94(sd);
491*4882a593Smuzhiyun else if ((height == 720) &&
492*4882a593Smuzhiyun (venc->venc_type == VPBE_VERSION_2)) {
493*4882a593Smuzhiyun /* TBD setup internal 720p mode here */
494*4882a593Smuzhiyun ret = venc_set_720p60_internal(sd);
495*4882a593Smuzhiyun /* for DM365 VPBE, there is DAC inside */
496*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
497*4882a593Smuzhiyun return ret;
498*4882a593Smuzhiyun } else if ((height == 1080) &&
499*4882a593Smuzhiyun (venc->venc_type == VPBE_VERSION_2)) {
500*4882a593Smuzhiyun /* TBD setup internal 1080i mode here */
501*4882a593Smuzhiyun ret = venc_set_1080i30_internal(sd);
502*4882a593Smuzhiyun /* for DM365 VPBE, there is DAC inside */
503*4882a593Smuzhiyun vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
504*4882a593Smuzhiyun return ret;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun return -EINVAL;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
venc_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)509*4882a593Smuzhiyun static int venc_s_routing(struct v4l2_subdev *sd, u32 input, u32 output,
510*4882a593Smuzhiyun u32 config)
511*4882a593Smuzhiyun {
512*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
513*4882a593Smuzhiyun int ret;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun v4l2_dbg(debug, 1, sd, "venc_s_routing\n");
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun ret = venc_set_dac(sd, output);
518*4882a593Smuzhiyun if (!ret)
519*4882a593Smuzhiyun venc->output = output;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun return ret;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
venc_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)524*4882a593Smuzhiyun static long venc_ioctl(struct v4l2_subdev *sd,
525*4882a593Smuzhiyun unsigned int cmd,
526*4882a593Smuzhiyun void *arg)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun u32 val;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun switch (cmd) {
531*4882a593Smuzhiyun case VENC_GET_FLD:
532*4882a593Smuzhiyun val = venc_read(sd, VENC_VSTAT);
533*4882a593Smuzhiyun *((int *)arg) = ((val & VENC_VSTAT_FIDST) ==
534*4882a593Smuzhiyun VENC_VSTAT_FIDST);
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun default:
537*4882a593Smuzhiyun v4l2_err(sd, "Wrong IOCTL cmd\n");
538*4882a593Smuzhiyun break;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops venc_core_ops = {
545*4882a593Smuzhiyun .ioctl = venc_ioctl,
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops venc_video_ops = {
549*4882a593Smuzhiyun .s_routing = venc_s_routing,
550*4882a593Smuzhiyun .s_std_output = venc_s_std_output,
551*4882a593Smuzhiyun .s_dv_timings = venc_s_dv_timings,
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun static const struct v4l2_subdev_ops venc_ops = {
555*4882a593Smuzhiyun .core = &venc_core_ops,
556*4882a593Smuzhiyun .video = &venc_video_ops,
557*4882a593Smuzhiyun };
558*4882a593Smuzhiyun
venc_initialize(struct v4l2_subdev * sd)559*4882a593Smuzhiyun static int venc_initialize(struct v4l2_subdev *sd)
560*4882a593Smuzhiyun {
561*4882a593Smuzhiyun struct venc_state *venc = to_state(sd);
562*4882a593Smuzhiyun int ret;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /* Set default to output to composite and std to NTSC */
565*4882a593Smuzhiyun venc->output = 0;
566*4882a593Smuzhiyun venc->std = V4L2_STD_525_60;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = venc_s_routing(sd, 0, venc->output, 0);
569*4882a593Smuzhiyun if (ret < 0) {
570*4882a593Smuzhiyun v4l2_err(sd, "Error setting output during init\n");
571*4882a593Smuzhiyun return -EINVAL;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun ret = venc_s_std_output(sd, venc->std);
575*4882a593Smuzhiyun if (ret < 0) {
576*4882a593Smuzhiyun v4l2_err(sd, "Error setting std during init\n");
577*4882a593Smuzhiyun return -EINVAL;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun return ret;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
venc_device_get(struct device * dev,void * data)583*4882a593Smuzhiyun static int venc_device_get(struct device *dev, void *data)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(dev);
586*4882a593Smuzhiyun struct venc_state **venc = data;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun if (strstr(pdev->name, "vpbe-venc") != NULL)
589*4882a593Smuzhiyun *venc = platform_get_drvdata(pdev);
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun return 0;
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun
venc_sub_dev_init(struct v4l2_device * v4l2_dev,const char * venc_name)594*4882a593Smuzhiyun struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
595*4882a593Smuzhiyun const char *venc_name)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun struct venc_state *venc = NULL;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun bus_for_each_dev(&platform_bus_type, NULL, &venc,
600*4882a593Smuzhiyun venc_device_get);
601*4882a593Smuzhiyun if (venc == NULL)
602*4882a593Smuzhiyun return NULL;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun v4l2_subdev_init(&venc->sd, &venc_ops);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun strscpy(venc->sd.name, venc_name, sizeof(venc->sd.name));
607*4882a593Smuzhiyun if (v4l2_device_register_subdev(v4l2_dev, &venc->sd) < 0) {
608*4882a593Smuzhiyun v4l2_err(v4l2_dev,
609*4882a593Smuzhiyun "vpbe unable to register venc sub device\n");
610*4882a593Smuzhiyun return NULL;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun if (venc_initialize(&venc->sd)) {
613*4882a593Smuzhiyun v4l2_err(v4l2_dev,
614*4882a593Smuzhiyun "vpbe venc initialization failed\n");
615*4882a593Smuzhiyun return NULL;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun return &venc->sd;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun EXPORT_SYMBOL(venc_sub_dev_init);
621*4882a593Smuzhiyun
venc_probe(struct platform_device * pdev)622*4882a593Smuzhiyun static int venc_probe(struct platform_device *pdev)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun const struct platform_device_id *pdev_id;
625*4882a593Smuzhiyun struct venc_state *venc;
626*4882a593Smuzhiyun struct resource *res;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun if (!pdev->dev.platform_data) {
629*4882a593Smuzhiyun dev_err(&pdev->dev, "No platform data for VENC sub device");
630*4882a593Smuzhiyun return -EINVAL;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun pdev_id = platform_get_device_id(pdev);
634*4882a593Smuzhiyun if (!pdev_id)
635*4882a593Smuzhiyun return -EINVAL;
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun venc = devm_kzalloc(&pdev->dev, sizeof(struct venc_state), GFP_KERNEL);
638*4882a593Smuzhiyun if (venc == NULL)
639*4882a593Smuzhiyun return -ENOMEM;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun venc->venc_type = pdev_id->driver_data;
642*4882a593Smuzhiyun venc->pdev = &pdev->dev;
643*4882a593Smuzhiyun venc->pdata = pdev->dev.platform_data;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun venc->venc_base = devm_ioremap_resource(&pdev->dev, res);
648*4882a593Smuzhiyun if (IS_ERR(venc->venc_base))
649*4882a593Smuzhiyun return PTR_ERR(venc->venc_base);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun if (venc->venc_type != VPBE_VERSION_1) {
652*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun venc->vdaccfg_reg = devm_ioremap_resource(&pdev->dev, res);
655*4882a593Smuzhiyun if (IS_ERR(venc->vdaccfg_reg))
656*4882a593Smuzhiyun return PTR_ERR(venc->vdaccfg_reg);
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun spin_lock_init(&venc->lock);
659*4882a593Smuzhiyun platform_set_drvdata(pdev, venc);
660*4882a593Smuzhiyun dev_notice(venc->pdev, "VENC sub device probe success\n");
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun return 0;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
venc_remove(struct platform_device * pdev)665*4882a593Smuzhiyun static int venc_remove(struct platform_device *pdev)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun return 0;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun static struct platform_driver venc_driver = {
671*4882a593Smuzhiyun .probe = venc_probe,
672*4882a593Smuzhiyun .remove = venc_remove,
673*4882a593Smuzhiyun .driver = {
674*4882a593Smuzhiyun .name = MODULE_NAME,
675*4882a593Smuzhiyun },
676*4882a593Smuzhiyun .id_table = vpbe_venc_devtype
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun module_platform_driver(venc_driver);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun MODULE_LICENSE("GPL");
682*4882a593Smuzhiyun MODULE_DESCRIPTION("VPBE VENC Driver");
683*4882a593Smuzhiyun MODULE_AUTHOR("Texas Instruments");
684