1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * i.MX6 Video Data Order Adapter (VDOA)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Philipp Zabel
6*4882a593Smuzhiyun * Copyright (C) 2016 Pengutronix, Michael Tretter <kernel@pengutronix.de>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/videodev2.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "imx-vdoa.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define VDOA_NAME "imx-vdoa"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define VDOAC 0x00
24*4882a593Smuzhiyun #define VDOASRR 0x04
25*4882a593Smuzhiyun #define VDOAIE 0x08
26*4882a593Smuzhiyun #define VDOAIST 0x0c
27*4882a593Smuzhiyun #define VDOAFP 0x10
28*4882a593Smuzhiyun #define VDOAIEBA00 0x14
29*4882a593Smuzhiyun #define VDOAIEBA01 0x18
30*4882a593Smuzhiyun #define VDOAIEBA02 0x1c
31*4882a593Smuzhiyun #define VDOAIEBA10 0x20
32*4882a593Smuzhiyun #define VDOAIEBA11 0x24
33*4882a593Smuzhiyun #define VDOAIEBA12 0x28
34*4882a593Smuzhiyun #define VDOASL 0x2c
35*4882a593Smuzhiyun #define VDOAIUBO 0x30
36*4882a593Smuzhiyun #define VDOAVEBA0 0x34
37*4882a593Smuzhiyun #define VDOAVEBA1 0x38
38*4882a593Smuzhiyun #define VDOAVEBA2 0x3c
39*4882a593Smuzhiyun #define VDOAVUBO 0x40
40*4882a593Smuzhiyun #define VDOASR 0x44
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define VDOAC_ISEL BIT(6)
43*4882a593Smuzhiyun #define VDOAC_PFS BIT(5)
44*4882a593Smuzhiyun #define VDOAC_SO BIT(4)
45*4882a593Smuzhiyun #define VDOAC_SYNC BIT(3)
46*4882a593Smuzhiyun #define VDOAC_NF BIT(2)
47*4882a593Smuzhiyun #define VDOAC_BNDM_MASK 0x3
48*4882a593Smuzhiyun #define VDOAC_BAND_HEIGHT_8 0x0
49*4882a593Smuzhiyun #define VDOAC_BAND_HEIGHT_16 0x1
50*4882a593Smuzhiyun #define VDOAC_BAND_HEIGHT_32 0x2
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define VDOASRR_START BIT(1)
53*4882a593Smuzhiyun #define VDOASRR_SWRST BIT(0)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define VDOAIE_EITERR BIT(1)
56*4882a593Smuzhiyun #define VDOAIE_EIEOT BIT(0)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define VDOAIST_TERR BIT(1)
59*4882a593Smuzhiyun #define VDOAIST_EOT BIT(0)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define VDOAFP_FH_MASK (0x1fff << 16)
62*4882a593Smuzhiyun #define VDOAFP_FW_MASK (0x3fff)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define VDOASL_VSLY_MASK (0x3fff << 16)
65*4882a593Smuzhiyun #define VDOASL_ISLY_MASK (0x7fff)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define VDOASR_ERRW BIT(4)
68*4882a593Smuzhiyun #define VDOASR_EOB BIT(3)
69*4882a593Smuzhiyun #define VDOASR_CURRENT_FRAME (0x3 << 1)
70*4882a593Smuzhiyun #define VDOASR_CURRENT_BUFFER BIT(1)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun enum {
73*4882a593Smuzhiyun V4L2_M2M_SRC = 0,
74*4882a593Smuzhiyun V4L2_M2M_DST = 1,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct vdoa_data {
78*4882a593Smuzhiyun struct vdoa_ctx *curr_ctx;
79*4882a593Smuzhiyun struct device *dev;
80*4882a593Smuzhiyun struct clk *vdoa_clk;
81*4882a593Smuzhiyun void __iomem *regs;
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun struct vdoa_q_data {
85*4882a593Smuzhiyun unsigned int width;
86*4882a593Smuzhiyun unsigned int height;
87*4882a593Smuzhiyun unsigned int bytesperline;
88*4882a593Smuzhiyun unsigned int sizeimage;
89*4882a593Smuzhiyun u32 pixelformat;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct vdoa_ctx {
93*4882a593Smuzhiyun struct vdoa_data *vdoa;
94*4882a593Smuzhiyun struct completion completion;
95*4882a593Smuzhiyun struct vdoa_q_data q_data[2];
96*4882a593Smuzhiyun unsigned int submitted_job;
97*4882a593Smuzhiyun unsigned int completed_job;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
vdoa_irq_handler(int irq,void * data)100*4882a593Smuzhiyun static irqreturn_t vdoa_irq_handler(int irq, void *data)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct vdoa_data *vdoa = data;
103*4882a593Smuzhiyun struct vdoa_ctx *curr_ctx;
104*4882a593Smuzhiyun u32 val;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Disable interrupts */
107*4882a593Smuzhiyun writel(0, vdoa->regs + VDOAIE);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun curr_ctx = vdoa->curr_ctx;
110*4882a593Smuzhiyun if (!curr_ctx) {
111*4882a593Smuzhiyun dev_warn(vdoa->dev,
112*4882a593Smuzhiyun "Instance released before the end of transaction\n");
113*4882a593Smuzhiyun return IRQ_HANDLED;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun val = readl(vdoa->regs + VDOAIST);
117*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAIST);
118*4882a593Smuzhiyun if (val & VDOAIST_TERR) {
119*4882a593Smuzhiyun val = readl(vdoa->regs + VDOASR) & VDOASR_ERRW;
120*4882a593Smuzhiyun dev_err(vdoa->dev, "AXI %s error\n", val ? "write" : "read");
121*4882a593Smuzhiyun } else if (!(val & VDOAIST_EOT)) {
122*4882a593Smuzhiyun dev_warn(vdoa->dev, "Spurious interrupt\n");
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun curr_ctx->completed_job++;
125*4882a593Smuzhiyun complete(&curr_ctx->completion);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return IRQ_HANDLED;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
vdoa_wait_for_completion(struct vdoa_ctx * ctx)130*4882a593Smuzhiyun int vdoa_wait_for_completion(struct vdoa_ctx *ctx)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct vdoa_data *vdoa = ctx->vdoa;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (ctx->submitted_job == ctx->completed_job)
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (!wait_for_completion_timeout(&ctx->completion,
138*4882a593Smuzhiyun msecs_to_jiffies(300))) {
139*4882a593Smuzhiyun dev_err(vdoa->dev,
140*4882a593Smuzhiyun "Timeout waiting for transfer result\n");
141*4882a593Smuzhiyun return -ETIMEDOUT;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun EXPORT_SYMBOL(vdoa_wait_for_completion);
147*4882a593Smuzhiyun
vdoa_device_run(struct vdoa_ctx * ctx,dma_addr_t dst,dma_addr_t src)148*4882a593Smuzhiyun void vdoa_device_run(struct vdoa_ctx *ctx, dma_addr_t dst, dma_addr_t src)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct vdoa_q_data *src_q_data, *dst_q_data;
151*4882a593Smuzhiyun struct vdoa_data *vdoa = ctx->vdoa;
152*4882a593Smuzhiyun u32 val;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (vdoa->curr_ctx)
155*4882a593Smuzhiyun vdoa_wait_for_completion(vdoa->curr_ctx);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun vdoa->curr_ctx = ctx;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun reinit_completion(&ctx->completion);
160*4882a593Smuzhiyun ctx->submitted_job++;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun src_q_data = &ctx->q_data[V4L2_M2M_SRC];
163*4882a593Smuzhiyun dst_q_data = &ctx->q_data[V4L2_M2M_DST];
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Progressive, no sync, 1 frame per run */
166*4882a593Smuzhiyun if (dst_q_data->pixelformat == V4L2_PIX_FMT_YUYV)
167*4882a593Smuzhiyun val = VDOAC_PFS;
168*4882a593Smuzhiyun else
169*4882a593Smuzhiyun val = 0;
170*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAC);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun writel(dst_q_data->height << 16 | dst_q_data->width,
173*4882a593Smuzhiyun vdoa->regs + VDOAFP);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun val = dst;
176*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAIEBA00);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun writel(src_q_data->bytesperline << 16 | dst_q_data->bytesperline,
179*4882a593Smuzhiyun vdoa->regs + VDOASL);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (dst_q_data->pixelformat == V4L2_PIX_FMT_NV12 ||
182*4882a593Smuzhiyun dst_q_data->pixelformat == V4L2_PIX_FMT_NV21)
183*4882a593Smuzhiyun val = dst_q_data->bytesperline * dst_q_data->height;
184*4882a593Smuzhiyun else
185*4882a593Smuzhiyun val = 0;
186*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAIUBO);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun val = src;
189*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAVEBA0);
190*4882a593Smuzhiyun val = round_up(src_q_data->bytesperline * src_q_data->height, 4096);
191*4882a593Smuzhiyun writel(val, vdoa->regs + VDOAVUBO);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* Enable interrupts and start transfer */
194*4882a593Smuzhiyun writel(VDOAIE_EITERR | VDOAIE_EIEOT, vdoa->regs + VDOAIE);
195*4882a593Smuzhiyun writel(VDOASRR_START, vdoa->regs + VDOASRR);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun EXPORT_SYMBOL(vdoa_device_run);
198*4882a593Smuzhiyun
vdoa_context_create(struct vdoa_data * vdoa)199*4882a593Smuzhiyun struct vdoa_ctx *vdoa_context_create(struct vdoa_data *vdoa)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct vdoa_ctx *ctx;
202*4882a593Smuzhiyun int err;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
205*4882a593Smuzhiyun if (!ctx)
206*4882a593Smuzhiyun return NULL;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun err = clk_prepare_enable(vdoa->vdoa_clk);
209*4882a593Smuzhiyun if (err) {
210*4882a593Smuzhiyun kfree(ctx);
211*4882a593Smuzhiyun return NULL;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun init_completion(&ctx->completion);
215*4882a593Smuzhiyun ctx->vdoa = vdoa;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return ctx;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun EXPORT_SYMBOL(vdoa_context_create);
220*4882a593Smuzhiyun
vdoa_context_destroy(struct vdoa_ctx * ctx)221*4882a593Smuzhiyun void vdoa_context_destroy(struct vdoa_ctx *ctx)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun struct vdoa_data *vdoa = ctx->vdoa;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (vdoa->curr_ctx == ctx) {
226*4882a593Smuzhiyun vdoa_wait_for_completion(vdoa->curr_ctx);
227*4882a593Smuzhiyun vdoa->curr_ctx = NULL;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun clk_disable_unprepare(vdoa->vdoa_clk);
231*4882a593Smuzhiyun kfree(ctx);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun EXPORT_SYMBOL(vdoa_context_destroy);
234*4882a593Smuzhiyun
vdoa_context_configure(struct vdoa_ctx * ctx,unsigned int width,unsigned int height,u32 pixelformat)235*4882a593Smuzhiyun int vdoa_context_configure(struct vdoa_ctx *ctx,
236*4882a593Smuzhiyun unsigned int width, unsigned int height,
237*4882a593Smuzhiyun u32 pixelformat)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct vdoa_q_data *src_q_data;
240*4882a593Smuzhiyun struct vdoa_q_data *dst_q_data;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (width < 16 || width > 8192 || width % 16 != 0 ||
243*4882a593Smuzhiyun height < 16 || height > 4096 || height % 16 != 0)
244*4882a593Smuzhiyun return -EINVAL;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (pixelformat != V4L2_PIX_FMT_YUYV &&
247*4882a593Smuzhiyun pixelformat != V4L2_PIX_FMT_NV12)
248*4882a593Smuzhiyun return -EINVAL;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* If no context is passed, only check if the format is valid */
251*4882a593Smuzhiyun if (!ctx)
252*4882a593Smuzhiyun return 0;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun src_q_data = &ctx->q_data[V4L2_M2M_SRC];
255*4882a593Smuzhiyun dst_q_data = &ctx->q_data[V4L2_M2M_DST];
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun src_q_data->width = width;
258*4882a593Smuzhiyun src_q_data->height = height;
259*4882a593Smuzhiyun src_q_data->bytesperline = width;
260*4882a593Smuzhiyun src_q_data->sizeimage =
261*4882a593Smuzhiyun round_up(src_q_data->bytesperline * height, 4096) +
262*4882a593Smuzhiyun src_q_data->bytesperline * height / 2;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun dst_q_data->width = width;
265*4882a593Smuzhiyun dst_q_data->height = height;
266*4882a593Smuzhiyun dst_q_data->pixelformat = pixelformat;
267*4882a593Smuzhiyun switch (pixelformat) {
268*4882a593Smuzhiyun case V4L2_PIX_FMT_YUYV:
269*4882a593Smuzhiyun dst_q_data->bytesperline = width * 2;
270*4882a593Smuzhiyun dst_q_data->sizeimage = dst_q_data->bytesperline * height;
271*4882a593Smuzhiyun break;
272*4882a593Smuzhiyun case V4L2_PIX_FMT_NV12:
273*4882a593Smuzhiyun default:
274*4882a593Smuzhiyun dst_q_data->bytesperline = width;
275*4882a593Smuzhiyun dst_q_data->sizeimage =
276*4882a593Smuzhiyun dst_q_data->bytesperline * height * 3 / 2;
277*4882a593Smuzhiyun break;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun EXPORT_SYMBOL(vdoa_context_configure);
283*4882a593Smuzhiyun
vdoa_probe(struct platform_device * pdev)284*4882a593Smuzhiyun static int vdoa_probe(struct platform_device *pdev)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun struct vdoa_data *vdoa;
287*4882a593Smuzhiyun struct resource *res;
288*4882a593Smuzhiyun int ret;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
291*4882a593Smuzhiyun if (ret) {
292*4882a593Smuzhiyun dev_err(&pdev->dev, "DMA enable failed\n");
293*4882a593Smuzhiyun return ret;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun vdoa = devm_kzalloc(&pdev->dev, sizeof(*vdoa), GFP_KERNEL);
297*4882a593Smuzhiyun if (!vdoa)
298*4882a593Smuzhiyun return -ENOMEM;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun vdoa->dev = &pdev->dev;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun vdoa->vdoa_clk = devm_clk_get(vdoa->dev, NULL);
303*4882a593Smuzhiyun if (IS_ERR(vdoa->vdoa_clk)) {
304*4882a593Smuzhiyun dev_err(vdoa->dev, "Failed to get clock\n");
305*4882a593Smuzhiyun return PTR_ERR(vdoa->vdoa_clk);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
309*4882a593Smuzhiyun vdoa->regs = devm_ioremap_resource(vdoa->dev, res);
310*4882a593Smuzhiyun if (IS_ERR(vdoa->regs))
311*4882a593Smuzhiyun return PTR_ERR(vdoa->regs);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
314*4882a593Smuzhiyun if (!res)
315*4882a593Smuzhiyun return -EINVAL;
316*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, res->start, NULL,
317*4882a593Smuzhiyun vdoa_irq_handler, IRQF_ONESHOT,
318*4882a593Smuzhiyun "vdoa", vdoa);
319*4882a593Smuzhiyun if (ret < 0) {
320*4882a593Smuzhiyun dev_err(vdoa->dev, "Failed to get irq\n");
321*4882a593Smuzhiyun return ret;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun platform_set_drvdata(pdev, vdoa);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return 0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
vdoa_remove(struct platform_device * pdev)329*4882a593Smuzhiyun static int vdoa_remove(struct platform_device *pdev)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun static const struct of_device_id vdoa_dt_ids[] = {
335*4882a593Smuzhiyun { .compatible = "fsl,imx6q-vdoa" },
336*4882a593Smuzhiyun {}
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, vdoa_dt_ids);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static struct platform_driver vdoa_driver = {
341*4882a593Smuzhiyun .probe = vdoa_probe,
342*4882a593Smuzhiyun .remove = vdoa_remove,
343*4882a593Smuzhiyun .driver = {
344*4882a593Smuzhiyun .name = VDOA_NAME,
345*4882a593Smuzhiyun .of_match_table = vdoa_dt_ids,
346*4882a593Smuzhiyun },
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun module_platform_driver(vdoa_driver);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun MODULE_DESCRIPTION("Video Data Order Adapter");
352*4882a593Smuzhiyun MODULE_AUTHOR("Philipp Zabel <philipp.zabel@gmail.com>");
353*4882a593Smuzhiyun MODULE_ALIAS("platform:imx-vdoa");
354*4882a593Smuzhiyun MODULE_LICENSE("GPL");
355