1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register definitions for the Atmel Image Sensor Interface. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Atmel Corporation 6*4882a593Smuzhiyun * Josh Wu, <josh.wu@atmel.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on previous work by Lars Haring, <lars.haring@atmel.com> 9*4882a593Smuzhiyun * and Sedji Gaouaou 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ATMEL_ISI_H__ 12*4882a593Smuzhiyun #define __ATMEL_ISI_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* ISI_V2 register offsets */ 17*4882a593Smuzhiyun #define ISI_CFG1 0x0000 18*4882a593Smuzhiyun #define ISI_CFG2 0x0004 19*4882a593Smuzhiyun #define ISI_PSIZE 0x0008 20*4882a593Smuzhiyun #define ISI_PDECF 0x000c 21*4882a593Smuzhiyun #define ISI_Y2R_SET0 0x0010 22*4882a593Smuzhiyun #define ISI_Y2R_SET1 0x0014 23*4882a593Smuzhiyun #define ISI_R2Y_SET0 0x0018 24*4882a593Smuzhiyun #define ISI_R2Y_SET1 0x001C 25*4882a593Smuzhiyun #define ISI_R2Y_SET2 0x0020 26*4882a593Smuzhiyun #define ISI_CTRL 0x0024 27*4882a593Smuzhiyun #define ISI_STATUS 0x0028 28*4882a593Smuzhiyun #define ISI_INTEN 0x002C 29*4882a593Smuzhiyun #define ISI_INTDIS 0x0030 30*4882a593Smuzhiyun #define ISI_INTMASK 0x0034 31*4882a593Smuzhiyun #define ISI_DMA_CHER 0x0038 32*4882a593Smuzhiyun #define ISI_DMA_CHDR 0x003C 33*4882a593Smuzhiyun #define ISI_DMA_CHSR 0x0040 34*4882a593Smuzhiyun #define ISI_DMA_P_ADDR 0x0044 35*4882a593Smuzhiyun #define ISI_DMA_P_CTRL 0x0048 36*4882a593Smuzhiyun #define ISI_DMA_P_DSCR 0x004C 37*4882a593Smuzhiyun #define ISI_DMA_C_ADDR 0x0050 38*4882a593Smuzhiyun #define ISI_DMA_C_CTRL 0x0054 39*4882a593Smuzhiyun #define ISI_DMA_C_DSCR 0x0058 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Bitfields in CFG1 */ 42*4882a593Smuzhiyun #define ISI_CFG1_HSYNC_POL_ACTIVE_LOW (1 << 2) 43*4882a593Smuzhiyun #define ISI_CFG1_VSYNC_POL_ACTIVE_LOW (1 << 3) 44*4882a593Smuzhiyun #define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING (1 << 4) 45*4882a593Smuzhiyun #define ISI_CFG1_EMB_SYNC (1 << 6) 46*4882a593Smuzhiyun #define ISI_CFG1_CRC_SYNC (1 << 7) 47*4882a593Smuzhiyun /* Constants for FRATE(ISI_V2) */ 48*4882a593Smuzhiyun #define ISI_CFG1_FRATE_CAPTURE_ALL (0 << 8) 49*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_2 (1 << 8) 50*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_3 (2 << 8) 51*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_4 (3 << 8) 52*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_5 (4 << 8) 53*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_6 (5 << 8) 54*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_7 (6 << 8) 55*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_8 (7 << 8) 56*4882a593Smuzhiyun #define ISI_CFG1_FRATE_DIV_MASK (7 << 8) 57*4882a593Smuzhiyun #define ISI_CFG1_DISCR (1 << 11) 58*4882a593Smuzhiyun #define ISI_CFG1_FULL_MODE (1 << 12) 59*4882a593Smuzhiyun /* Definition for THMASK(ISI_V2) */ 60*4882a593Smuzhiyun #define ISI_CFG1_THMASK_BEATS_4 (0 << 13) 61*4882a593Smuzhiyun #define ISI_CFG1_THMASK_BEATS_8 (1 << 13) 62*4882a593Smuzhiyun #define ISI_CFG1_THMASK_BEATS_16 (2 << 13) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Bitfields in CFG2 */ 65*4882a593Smuzhiyun #define ISI_CFG2_GS_MODE_2_PIXEL (0 << 11) 66*4882a593Smuzhiyun #define ISI_CFG2_GS_MODE_1_PIXEL (1 << 11) 67*4882a593Smuzhiyun #define ISI_CFG2_GRAYSCALE (1 << 13) 68*4882a593Smuzhiyun #define ISI_CFG2_COL_SPACE_YCbCr (0 << 15) 69*4882a593Smuzhiyun #define ISI_CFG2_COL_SPACE_RGB (1 << 15) 70*4882a593Smuzhiyun /* Constants for YCC_SWAP(ISI_V2) */ 71*4882a593Smuzhiyun #define ISI_CFG2_YCC_SWAP_DEFAULT (0 << 28) 72*4882a593Smuzhiyun #define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28) 73*4882a593Smuzhiyun #define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28) 74*4882a593Smuzhiyun #define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28) 75*4882a593Smuzhiyun #define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28) 76*4882a593Smuzhiyun #define ISI_CFG2_IM_VSIZE_OFFSET 0 77*4882a593Smuzhiyun #define ISI_CFG2_IM_HSIZE_OFFSET 16 78*4882a593Smuzhiyun #define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET) 79*4882a593Smuzhiyun #define ISI_CFG2_IM_HSIZE_MASK (0x7FF << ISI_CFG2_IM_HSIZE_OFFSET) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Bitfields in PSIZE */ 82*4882a593Smuzhiyun #define ISI_PSIZE_PREV_VSIZE_OFFSET 0 83*4882a593Smuzhiyun #define ISI_PSIZE_PREV_HSIZE_OFFSET 16 84*4882a593Smuzhiyun #define ISI_PSIZE_PREV_VSIZE_MASK (0x3FF << ISI_PSIZE_PREV_VSIZE_OFFSET) 85*4882a593Smuzhiyun #define ISI_PSIZE_PREV_HSIZE_MASK (0x3FF << ISI_PSIZE_PREV_HSIZE_OFFSET) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Bitfields in PDECF */ 88*4882a593Smuzhiyun #define ISI_PDECF_DEC_FACTOR_MASK (0xFF << 0) 89*4882a593Smuzhiyun #define ISI_PDECF_NO_SAMPLING (16) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Bitfields in CTRL */ 92*4882a593Smuzhiyun /* Also using in SR(ISI_V2) */ 93*4882a593Smuzhiyun #define ISI_CTRL_EN (1 << 0) 94*4882a593Smuzhiyun #define ISI_CTRL_CDC (1 << 8) 95*4882a593Smuzhiyun /* Also using in SR/IER/IDR/IMR(ISI_V2) */ 96*4882a593Smuzhiyun #define ISI_CTRL_DIS (1 << 1) 97*4882a593Smuzhiyun #define ISI_CTRL_SRST (1 << 2) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* Bitfields in SR */ 100*4882a593Smuzhiyun #define ISI_SR_SIP (1 << 19) 101*4882a593Smuzhiyun /* Also using in SR/IER/IDR/IMR */ 102*4882a593Smuzhiyun #define ISI_SR_VSYNC (1 << 10) 103*4882a593Smuzhiyun #define ISI_SR_PXFR_DONE (1 << 16) 104*4882a593Smuzhiyun #define ISI_SR_CXFR_DONE (1 << 17) 105*4882a593Smuzhiyun #define ISI_SR_P_OVR (1 << 24) 106*4882a593Smuzhiyun #define ISI_SR_C_OVR (1 << 25) 107*4882a593Smuzhiyun #define ISI_SR_CRC_ERR (1 << 26) 108*4882a593Smuzhiyun #define ISI_SR_FR_OVR (1 << 27) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */ 111*4882a593Smuzhiyun #define ISI_DMA_CTRL_FETCH (1 << 0) 112*4882a593Smuzhiyun #define ISI_DMA_CTRL_WB (1 << 1) 113*4882a593Smuzhiyun #define ISI_DMA_CTRL_IEN (1 << 2) 114*4882a593Smuzhiyun #define ISI_DMA_CTRL_DONE (1 << 3) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Bitfields in DMA_CHSR/CHER/CHDR */ 117*4882a593Smuzhiyun #define ISI_DMA_CHSR_P_CH (1 << 0) 118*4882a593Smuzhiyun #define ISI_DMA_CHSR_C_CH (1 << 1) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Definition for isi_platform_data */ 121*4882a593Smuzhiyun #define ISI_DATAWIDTH_8 0x01 122*4882a593Smuzhiyun #define ISI_DATAWIDTH_10 0x02 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun struct v4l2_async_subdev; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct isi_platform_data { 127*4882a593Smuzhiyun u8 has_emb_sync; 128*4882a593Smuzhiyun u8 hsync_act_low; 129*4882a593Smuzhiyun u8 vsync_act_low; 130*4882a593Smuzhiyun u8 pclk_act_falling; 131*4882a593Smuzhiyun u8 full_mode; 132*4882a593Smuzhiyun u32 data_width_flags; 133*4882a593Smuzhiyun /* Using for ISI_CFG1 */ 134*4882a593Smuzhiyun u32 frate; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif /* __ATMEL_ISI_H__ */ 138