1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Microchip Image Sensor Controller (ISC) driver header file 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2019 Microchip Technology, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Songjun Wu 8*4882a593Smuzhiyun * Author: Eugen Hristev <eugen.hristev@microchip.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef _ATMEL_ISC_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define ISC_MAX_SUPPORT_WIDTH 2592 14*4882a593Smuzhiyun #define ISC_MAX_SUPPORT_HEIGHT 1944 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define ISC_CLK_MAX_DIV 255 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum isc_clk_id { 19*4882a593Smuzhiyun ISC_ISPCK = 0, 20*4882a593Smuzhiyun ISC_MCK = 1, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct isc_clk { 24*4882a593Smuzhiyun struct clk_hw hw; 25*4882a593Smuzhiyun struct clk *clk; 26*4882a593Smuzhiyun struct regmap *regmap; 27*4882a593Smuzhiyun spinlock_t lock; /* serialize access to clock registers */ 28*4882a593Smuzhiyun u8 id; 29*4882a593Smuzhiyun u8 parent_id; 30*4882a593Smuzhiyun u32 div; 31*4882a593Smuzhiyun struct device *dev; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define to_isc_clk(v) container_of(v, struct isc_clk, hw) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct isc_buffer { 37*4882a593Smuzhiyun struct vb2_v4l2_buffer vb; 38*4882a593Smuzhiyun struct list_head list; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct isc_subdev_entity { 42*4882a593Smuzhiyun struct v4l2_subdev *sd; 43*4882a593Smuzhiyun struct v4l2_async_subdev *asd; 44*4882a593Smuzhiyun struct v4l2_async_notifier notifier; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun u32 pfe_cfg0; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct list_head list; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * struct isc_format - ISC media bus format information 53*4882a593Smuzhiyun This structure represents the interface between the ISC 54*4882a593Smuzhiyun and the sensor. It's the input format received by 55*4882a593Smuzhiyun the ISC. 56*4882a593Smuzhiyun * @fourcc: Fourcc code for this format 57*4882a593Smuzhiyun * @mbus_code: V4L2 media bus format code. 58*4882a593Smuzhiyun * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer. 59*4882a593Smuzhiyun this is either BGBG, RGRG, etc. 60*4882a593Smuzhiyun * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct isc_format { 64*4882a593Smuzhiyun u32 fourcc; 65*4882a593Smuzhiyun u32 mbus_code; 66*4882a593Smuzhiyun u32 cfa_baycfg; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun bool sd_support; 69*4882a593Smuzhiyun u32 pfe_cfg0_bps; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Pipeline bitmap */ 73*4882a593Smuzhiyun #define WB_ENABLE BIT(0) 74*4882a593Smuzhiyun #define CFA_ENABLE BIT(1) 75*4882a593Smuzhiyun #define CC_ENABLE BIT(2) 76*4882a593Smuzhiyun #define GAM_ENABLE BIT(3) 77*4882a593Smuzhiyun #define GAM_BENABLE BIT(4) 78*4882a593Smuzhiyun #define GAM_GENABLE BIT(5) 79*4882a593Smuzhiyun #define GAM_RENABLE BIT(6) 80*4882a593Smuzhiyun #define CSC_ENABLE BIT(7) 81*4882a593Smuzhiyun #define CBC_ENABLE BIT(8) 82*4882a593Smuzhiyun #define SUB422_ENABLE BIT(9) 83*4882a593Smuzhiyun #define SUB420_ENABLE BIT(10) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * struct fmt_config - ISC format configuration and internal pipeline 89*4882a593Smuzhiyun This structure represents the internal configuration 90*4882a593Smuzhiyun of the ISC. 91*4882a593Smuzhiyun It also holds the format that ISC will present to v4l2. 92*4882a593Smuzhiyun * @sd_format: Pointer to an isc_format struct that holds the sensor 93*4882a593Smuzhiyun configuration. 94*4882a593Smuzhiyun * @fourcc: Fourcc code for this format. 95*4882a593Smuzhiyun * @bpp: Bytes per pixel in the current format. 96*4882a593Smuzhiyun * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging) 97*4882a593Smuzhiyun * @dcfg_imode: Configuration of the input of the DMA module 98*4882a593Smuzhiyun * @dctrl_dview: Configuration of the output of the DMA module 99*4882a593Smuzhiyun * @bits_pipeline: Configuration of the pipeline, which modules are enabled 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun struct fmt_config { 102*4882a593Smuzhiyun struct isc_format *sd_format; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun u32 fourcc; 105*4882a593Smuzhiyun u8 bpp; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun u32 rlp_cfg_mode; 108*4882a593Smuzhiyun u32 dcfg_imode; 109*4882a593Smuzhiyun u32 dctrl_dview; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun u32 bits_pipeline; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define HIST_ENTRIES 512 115*4882a593Smuzhiyun #define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun enum{ 118*4882a593Smuzhiyun HIST_INIT = 0, 119*4882a593Smuzhiyun HIST_ENABLED, 120*4882a593Smuzhiyun HIST_DISABLED, 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct isc_ctrls { 124*4882a593Smuzhiyun struct v4l2_ctrl_handler handler; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun u32 brightness; 127*4882a593Smuzhiyun u32 contrast; 128*4882a593Smuzhiyun u8 gamma_index; 129*4882a593Smuzhiyun #define ISC_WB_NONE 0 130*4882a593Smuzhiyun #define ISC_WB_AUTO 1 131*4882a593Smuzhiyun #define ISC_WB_ONETIME 2 132*4882a593Smuzhiyun u8 awb; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* one for each component : GR, R, GB, B */ 135*4882a593Smuzhiyun u32 gain[HIST_BAYER]; 136*4882a593Smuzhiyun s32 offset[HIST_BAYER]; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun u32 hist_entry[HIST_ENTRIES]; 139*4882a593Smuzhiyun u32 hist_count[HIST_BAYER]; 140*4882a593Smuzhiyun u8 hist_id; 141*4882a593Smuzhiyun u8 hist_stat; 142*4882a593Smuzhiyun #define HIST_MIN_INDEX 0 143*4882a593Smuzhiyun #define HIST_MAX_INDEX 1 144*4882a593Smuzhiyun u32 hist_minmax[HIST_BAYER][2]; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define ISC_PIPE_LINE_NODE_NUM 11 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * struct isc_device - ISC device driver data/config struct 151*4882a593Smuzhiyun * @regmap: Register map 152*4882a593Smuzhiyun * @hclock: Hclock clock input (refer datasheet) 153*4882a593Smuzhiyun * @ispck: iscpck clock (refer datasheet) 154*4882a593Smuzhiyun * @isc_clks: ISC clocks 155*4882a593Smuzhiyun * 156*4882a593Smuzhiyun * @dev: Registered device driver 157*4882a593Smuzhiyun * @v4l2_dev: v4l2 registered device 158*4882a593Smuzhiyun * @video_dev: registered video device 159*4882a593Smuzhiyun * 160*4882a593Smuzhiyun * @vb2_vidq: video buffer 2 video queue 161*4882a593Smuzhiyun * @dma_queue_lock: lock to serialize the dma buffer queue 162*4882a593Smuzhiyun * @dma_queue: the queue for dma buffers 163*4882a593Smuzhiyun * @cur_frm: current isc frame/buffer 164*4882a593Smuzhiyun * @sequence: current frame number 165*4882a593Smuzhiyun * @stop: true if isc is not streaming, false if streaming 166*4882a593Smuzhiyun * @comp: completion reference that signals frame completion 167*4882a593Smuzhiyun * 168*4882a593Smuzhiyun * @fmt: current v42l format 169*4882a593Smuzhiyun * @user_formats: list of formats that are supported and agreed with sd 170*4882a593Smuzhiyun * @num_user_formats: how many formats are in user_formats 171*4882a593Smuzhiyun * 172*4882a593Smuzhiyun * @config: current ISC format configuration 173*4882a593Smuzhiyun * @try_config: the current ISC try format , not yet activated 174*4882a593Smuzhiyun * 175*4882a593Smuzhiyun * @ctrls: holds information about ISC controls 176*4882a593Smuzhiyun * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button 177*4882a593Smuzhiyun * @awb_work: workqueue reference for autowhitebalance histogram 178*4882a593Smuzhiyun * analysis 179*4882a593Smuzhiyun * 180*4882a593Smuzhiyun * @lock: lock for serializing userspace file operations 181*4882a593Smuzhiyun * with ISC operations 182*4882a593Smuzhiyun * @awb_lock: lock for serializing awb work queue operations 183*4882a593Smuzhiyun * with DMA/buffer operations 184*4882a593Smuzhiyun * 185*4882a593Smuzhiyun * @pipeline: configuration of the ISC pipeline 186*4882a593Smuzhiyun * 187*4882a593Smuzhiyun * @current_subdev: current subdevice: the sensor 188*4882a593Smuzhiyun * @subdev_entities: list of subdevice entitites 189*4882a593Smuzhiyun */ 190*4882a593Smuzhiyun struct isc_device { 191*4882a593Smuzhiyun struct regmap *regmap; 192*4882a593Smuzhiyun struct clk *hclock; 193*4882a593Smuzhiyun struct clk *ispck; 194*4882a593Smuzhiyun struct isc_clk isc_clks[2]; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun struct device *dev; 197*4882a593Smuzhiyun struct v4l2_device v4l2_dev; 198*4882a593Smuzhiyun struct video_device video_dev; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun struct vb2_queue vb2_vidq; 201*4882a593Smuzhiyun spinlock_t dma_queue_lock; /* serialize access to dma queue */ 202*4882a593Smuzhiyun struct list_head dma_queue; 203*4882a593Smuzhiyun struct isc_buffer *cur_frm; 204*4882a593Smuzhiyun unsigned int sequence; 205*4882a593Smuzhiyun bool stop; 206*4882a593Smuzhiyun struct completion comp; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun struct v4l2_format fmt; 209*4882a593Smuzhiyun struct isc_format **user_formats; 210*4882a593Smuzhiyun unsigned int num_user_formats; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun struct fmt_config config; 213*4882a593Smuzhiyun struct fmt_config try_config; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun struct isc_ctrls ctrls; 216*4882a593Smuzhiyun struct work_struct awb_work; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun struct mutex lock; /* serialize access to file operations */ 219*4882a593Smuzhiyun spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun struct isc_subdev_entity *current_subdev; 224*4882a593Smuzhiyun struct list_head subdev_entities; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun struct { 227*4882a593Smuzhiyun #define ISC_CTRL_DO_WB 1 228*4882a593Smuzhiyun #define ISC_CTRL_R_GAIN 2 229*4882a593Smuzhiyun #define ISC_CTRL_B_GAIN 3 230*4882a593Smuzhiyun #define ISC_CTRL_GR_GAIN 4 231*4882a593Smuzhiyun #define ISC_CTRL_GB_GAIN 5 232*4882a593Smuzhiyun #define ISC_CTRL_R_OFF 6 233*4882a593Smuzhiyun #define ISC_CTRL_B_OFF 7 234*4882a593Smuzhiyun #define ISC_CTRL_GR_OFF 8 235*4882a593Smuzhiyun #define ISC_CTRL_GB_OFF 9 236*4882a593Smuzhiyun struct v4l2_ctrl *awb_ctrl; 237*4882a593Smuzhiyun struct v4l2_ctrl *do_wb_ctrl; 238*4882a593Smuzhiyun struct v4l2_ctrl *r_gain_ctrl; 239*4882a593Smuzhiyun struct v4l2_ctrl *b_gain_ctrl; 240*4882a593Smuzhiyun struct v4l2_ctrl *gr_gain_ctrl; 241*4882a593Smuzhiyun struct v4l2_ctrl *gb_gain_ctrl; 242*4882a593Smuzhiyun struct v4l2_ctrl *r_off_ctrl; 243*4882a593Smuzhiyun struct v4l2_ctrl *b_off_ctrl; 244*4882a593Smuzhiyun struct v4l2_ctrl *gr_off_ctrl; 245*4882a593Smuzhiyun struct v4l2_ctrl *gb_off_ctrl; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define GAMMA_MAX 2 250*4882a593Smuzhiyun #define GAMMA_ENTRIES 64 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define ATMEL_ISC_NAME "atmel-isc" 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun extern struct isc_format formats_list[]; 255*4882a593Smuzhiyun extern const struct isc_format controller_formats[]; 256*4882a593Smuzhiyun extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES]; 257*4882a593Smuzhiyun extern const struct regmap_config isc_regmap_config; 258*4882a593Smuzhiyun extern const struct v4l2_async_notifier_operations isc_async_ops; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun irqreturn_t isc_interrupt(int irq, void *dev_id); 261*4882a593Smuzhiyun int isc_pipeline_init(struct isc_device *isc); 262*4882a593Smuzhiyun int isc_clk_init(struct isc_device *isc); 263*4882a593Smuzhiyun void isc_subdev_cleanup(struct isc_device *isc); 264*4882a593Smuzhiyun void isc_clk_cleanup(struct isc_device *isc); 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #endif 267