1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI AM437x Image Sensor Interface Registers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 - 2014 Texas Instruments, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Benoit Parrot <bparrot@ti.com> 8*4882a593Smuzhiyun * Lad, Prabhakar <prabhakar.csengg@gmail.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef AM437X_VPFE_REGS_H 12*4882a593Smuzhiyun #define AM437X_VPFE_REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* VPFE module register offset */ 15*4882a593Smuzhiyun #define VPFE_REVISION 0x0 16*4882a593Smuzhiyun #define VPFE_PCR 0x4 17*4882a593Smuzhiyun #define VPFE_SYNMODE 0x8 18*4882a593Smuzhiyun #define VPFE_HD_VD_WID 0xc 19*4882a593Smuzhiyun #define VPFE_PIX_LINES 0x10 20*4882a593Smuzhiyun #define VPFE_HORZ_INFO 0x14 21*4882a593Smuzhiyun #define VPFE_VERT_START 0x18 22*4882a593Smuzhiyun #define VPFE_VERT_LINES 0x1c 23*4882a593Smuzhiyun #define VPFE_CULLING 0x20 24*4882a593Smuzhiyun #define VPFE_HSIZE_OFF 0x24 25*4882a593Smuzhiyun #define VPFE_SDOFST 0x28 26*4882a593Smuzhiyun #define VPFE_SDR_ADDR 0x2c 27*4882a593Smuzhiyun #define VPFE_CLAMP 0x30 28*4882a593Smuzhiyun #define VPFE_DCSUB 0x34 29*4882a593Smuzhiyun #define VPFE_COLPTN 0x38 30*4882a593Smuzhiyun #define VPFE_BLKCMP 0x3c 31*4882a593Smuzhiyun #define VPFE_VDINT 0x48 32*4882a593Smuzhiyun #define VPFE_ALAW 0x4c 33*4882a593Smuzhiyun #define VPFE_REC656IF 0x50 34*4882a593Smuzhiyun #define VPFE_CCDCFG 0x54 35*4882a593Smuzhiyun #define VPFE_DMA_CNTL 0x98 36*4882a593Smuzhiyun #define VPFE_SYSCONFIG 0x104 37*4882a593Smuzhiyun #define VPFE_CONFIG 0x108 38*4882a593Smuzhiyun #define VPFE_IRQ_EOI 0x110 39*4882a593Smuzhiyun #define VPFE_IRQ_STS_RAW 0x114 40*4882a593Smuzhiyun #define VPFE_IRQ_STS 0x118 41*4882a593Smuzhiyun #define VPFE_IRQ_EN_SET 0x11c 42*4882a593Smuzhiyun #define VPFE_IRQ_EN_CLR 0x120 43*4882a593Smuzhiyun #define VPFE_REG_END 0x124 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Define bit fields within selected registers */ 46*4882a593Smuzhiyun #define VPFE_FID_POL_MASK 1 47*4882a593Smuzhiyun #define VPFE_FID_POL_SHIFT 4 48*4882a593Smuzhiyun #define VPFE_HD_POL_MASK 1 49*4882a593Smuzhiyun #define VPFE_HD_POL_SHIFT 3 50*4882a593Smuzhiyun #define VPFE_VD_POL_MASK 1 51*4882a593Smuzhiyun #define VPFE_VD_POL_SHIFT 2 52*4882a593Smuzhiyun #define VPFE_HSIZE_OFF_MASK 0xffffffe0 53*4882a593Smuzhiyun #define VPFE_32BYTE_ALIGN_VAL 31 54*4882a593Smuzhiyun #define VPFE_FRM_FMT_MASK 0x1 55*4882a593Smuzhiyun #define VPFE_FRM_FMT_SHIFT 7 56*4882a593Smuzhiyun #define VPFE_DATA_SZ_MASK 7 57*4882a593Smuzhiyun #define VPFE_DATA_SZ_SHIFT 8 58*4882a593Smuzhiyun #define VPFE_PIX_FMT_MASK 3 59*4882a593Smuzhiyun #define VPFE_PIX_FMT_SHIFT 12 60*4882a593Smuzhiyun #define VPFE_VP2SDR_DISABLE 0xfffbffff 61*4882a593Smuzhiyun #define VPFE_WEN_ENABLE BIT(17) 62*4882a593Smuzhiyun #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff 63*4882a593Smuzhiyun #define VPFE_VDHDEN_ENABLE BIT(16) 64*4882a593Smuzhiyun #define VPFE_LPF_ENABLE BIT(14) 65*4882a593Smuzhiyun #define VPFE_ALAW_ENABLE BIT(3) 66*4882a593Smuzhiyun #define VPFE_ALAW_GAMMA_WD_MASK 7 67*4882a593Smuzhiyun #define VPFE_BLK_CLAMP_ENABLE BIT(31) 68*4882a593Smuzhiyun #define VPFE_BLK_SGAIN_MASK 0x1f 69*4882a593Smuzhiyun #define VPFE_BLK_ST_PXL_MASK 0x7fff 70*4882a593Smuzhiyun #define VPFE_BLK_ST_PXL_SHIFT 10 71*4882a593Smuzhiyun #define VPFE_BLK_SAMPLE_LN_MASK 7 72*4882a593Smuzhiyun #define VPFE_BLK_SAMPLE_LN_SHIFT 28 73*4882a593Smuzhiyun #define VPFE_BLK_SAMPLE_LINE_MASK 7 74*4882a593Smuzhiyun #define VPFE_BLK_SAMPLE_LINE_SHIFT 25 75*4882a593Smuzhiyun #define VPFE_BLK_DC_SUB_MASK 0x03fff 76*4882a593Smuzhiyun #define VPFE_BLK_COMP_MASK 0xff 77*4882a593Smuzhiyun #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 78*4882a593Smuzhiyun #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 79*4882a593Smuzhiyun #define VPFE_BLK_COMP_R_COMP_SHIFT 24 80*4882a593Smuzhiyun #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15) 81*4882a593Smuzhiyun #define VPFE_DATA_PACK_ENABLE BIT(11) 82*4882a593Smuzhiyun #define VPFE_HORZ_INFO_SPH_SHIFT 16 83*4882a593Smuzhiyun #define VPFE_VERT_START_SLV0_SHIFT 16 84*4882a593Smuzhiyun #define VPFE_VDINT_VDINT0_SHIFT 16 85*4882a593Smuzhiyun #define VPFE_VDINT_VDINT1_MASK 0xffff 86*4882a593Smuzhiyun #define VPFE_PPC_RAW 1 87*4882a593Smuzhiyun #define VPFE_DCSUB_DEFAULT_VAL 0 88*4882a593Smuzhiyun #define VPFE_CLAMP_DEFAULT_VAL 0 89*4882a593Smuzhiyun #define VPFE_COLPTN_VAL 0xbb11bb11 90*4882a593Smuzhiyun #define VPFE_TWO_BYTES_PER_PIXEL 2 91*4882a593Smuzhiyun #define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d 92*4882a593Smuzhiyun #define VPFE_INTERLACED_NO_IMAGE_INVERT 0x0249 93*4882a593Smuzhiyun #define VPFE_PROGRESSIVE_IMAGE_INVERT 0x4000 94*4882a593Smuzhiyun #define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 0 95*4882a593Smuzhiyun #define VPFE_INTERLACED_HEIGHT_SHIFT 1 96*4882a593Smuzhiyun #define VPFE_SYN_MODE_INPMOD_SHIFT 12 97*4882a593Smuzhiyun #define VPFE_SYN_MODE_INPMOD_MASK 3 98*4882a593Smuzhiyun #define VPFE_SYN_MODE_8BITS (7 << 8) 99*4882a593Smuzhiyun #define VPFE_SYN_MODE_10BITS (6 << 8) 100*4882a593Smuzhiyun #define VPFE_SYN_MODE_11BITS (5 << 8) 101*4882a593Smuzhiyun #define VPFE_SYN_MODE_12BITS (4 << 8) 102*4882a593Smuzhiyun #define VPFE_SYN_MODE_13BITS (3 << 8) 103*4882a593Smuzhiyun #define VPFE_SYN_MODE_14BITS (2 << 8) 104*4882a593Smuzhiyun #define VPFE_SYN_MODE_15BITS (1 << 8) 105*4882a593Smuzhiyun #define VPFE_SYN_MODE_16BITS (0 << 8) 106*4882a593Smuzhiyun #define VPFE_SYN_FLDMODE_MASK 1 107*4882a593Smuzhiyun #define VPFE_SYN_FLDMODE_SHIFT 7 108*4882a593Smuzhiyun #define VPFE_REC656IF_BT656_EN 3 109*4882a593Smuzhiyun #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2) 110*4882a593Smuzhiyun #define VPFE_CCDCFG_Y8POS_SHIFT 11 111*4882a593Smuzhiyun #define VPFE_CCDCFG_BW656_10BIT BIT(5) 112*4882a593Smuzhiyun #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 113*4882a593Smuzhiyun #define VPFE_NO_CULLING 0xffff00ff 114*4882a593Smuzhiyun #define VPFE_VDINT0 BIT(0) 115*4882a593Smuzhiyun #define VPFE_VDINT1 BIT(1) 116*4882a593Smuzhiyun #define VPFE_VDINT2 BIT(2) 117*4882a593Smuzhiyun #define VPFE_DMA_CNTL_OVERFLOW BIT(31) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define VPFE_CONFIG_PCLK_INV_SHIFT 0 120*4882a593Smuzhiyun #define VPFE_CONFIG_PCLK_INV_MASK 1 121*4882a593Smuzhiyun #define VPFE_CONFIG_PCLK_INV_NOT_INV 0 122*4882a593Smuzhiyun #define VPFE_CONFIG_PCLK_INV_INV 1 123*4882a593Smuzhiyun #define VPFE_CONFIG_EN_SHIFT 1 124*4882a593Smuzhiyun #define VPFE_CONFIG_EN_MASK 2 125*4882a593Smuzhiyun #define VPFE_CONFIG_EN_DISABLE 0 126*4882a593Smuzhiyun #define VPFE_CONFIG_EN_ENABLE 1 127*4882a593Smuzhiyun #define VPFE_CONFIG_ST_SHIFT 2 128*4882a593Smuzhiyun #define VPFE_CONFIG_ST_MASK 4 129*4882a593Smuzhiyun #define VPFE_CONFIG_ST_OCP_ACTIVE 0 130*4882a593Smuzhiyun #define VPFE_CONFIG_ST_OCP_STANDBY 1 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif /* AM437X_VPFE_REGS_H */ 133