1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 - 2014 Texas Instruments, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Benoit Parrot <bparrot@ti.com>
6*4882a593Smuzhiyun * Lad, Prabhakar <prabhakar.csengg@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef AM437X_VPFE_H
10*4882a593Smuzhiyun #define AM437X_VPFE_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/am437x-vpfe.h>
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/completion.h>
15*4882a593Smuzhiyun #include <linux/device.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/videodev2.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <media/v4l2-dev.h>
21*4882a593Smuzhiyun #include <media/v4l2-device.h>
22*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
23*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
24*4882a593Smuzhiyun #include <media/videobuf2-dma-contig.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "am437x-vpfe_regs.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun enum vpfe_pin_pol {
29*4882a593Smuzhiyun VPFE_PINPOL_POSITIVE = 0,
30*4882a593Smuzhiyun VPFE_PINPOL_NEGATIVE,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun enum vpfe_hw_if_type {
34*4882a593Smuzhiyun /* Raw Bayer */
35*4882a593Smuzhiyun VPFE_RAW_BAYER = 0,
36*4882a593Smuzhiyun /* BT656 - 8 bit */
37*4882a593Smuzhiyun VPFE_BT656,
38*4882a593Smuzhiyun /* BT656 - 10 bit */
39*4882a593Smuzhiyun VPFE_BT656_10BIT,
40*4882a593Smuzhiyun /* YCbCr - 8 bit with external sync */
41*4882a593Smuzhiyun VPFE_YCBCR_SYNC_8,
42*4882a593Smuzhiyun /* YCbCr - 16 bit with external sync */
43*4882a593Smuzhiyun VPFE_YCBCR_SYNC_16,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* interface description */
47*4882a593Smuzhiyun struct vpfe_hw_if_param {
48*4882a593Smuzhiyun enum vpfe_hw_if_type if_type;
49*4882a593Smuzhiyun enum vpfe_pin_pol hdpol;
50*4882a593Smuzhiyun enum vpfe_pin_pol vdpol;
51*4882a593Smuzhiyun unsigned int bus_width;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define VPFE_MAX_SUBDEV 1
55*4882a593Smuzhiyun #define VPFE_MAX_INPUTS 1
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct vpfe_std_info {
58*4882a593Smuzhiyun int active_pixels;
59*4882a593Smuzhiyun int active_lines;
60*4882a593Smuzhiyun /* current frame format */
61*4882a593Smuzhiyun int frame_format;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct vpfe_route {
65*4882a593Smuzhiyun u32 input;
66*4882a593Smuzhiyun u32 output;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun struct vpfe_subdev_info {
70*4882a593Smuzhiyun /* Sub device group id */
71*4882a593Smuzhiyun int grp_id;
72*4882a593Smuzhiyun /* inputs available at the sub device */
73*4882a593Smuzhiyun struct v4l2_input inputs[VPFE_MAX_INPUTS];
74*4882a593Smuzhiyun /* Sub dev routing information for each input */
75*4882a593Smuzhiyun struct vpfe_route *routes;
76*4882a593Smuzhiyun /* check if sub dev supports routing */
77*4882a593Smuzhiyun int can_route;
78*4882a593Smuzhiyun /* ccdc bus/interface configuration */
79*4882a593Smuzhiyun struct vpfe_hw_if_param vpfe_param;
80*4882a593Smuzhiyun struct v4l2_subdev *sd;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct vpfe_config {
84*4882a593Smuzhiyun /* information about each subdev */
85*4882a593Smuzhiyun struct vpfe_subdev_info sub_devs[VPFE_MAX_SUBDEV];
86*4882a593Smuzhiyun /* Flat array, arranged in groups */
87*4882a593Smuzhiyun struct v4l2_async_subdev *asd[VPFE_MAX_SUBDEV];
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct vpfe_cap_buffer {
91*4882a593Smuzhiyun struct vb2_v4l2_buffer vb;
92*4882a593Smuzhiyun struct list_head list;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun enum ccdc_pixfmt {
96*4882a593Smuzhiyun CCDC_PIXFMT_RAW = 0,
97*4882a593Smuzhiyun CCDC_PIXFMT_YCBCR_16BIT,
98*4882a593Smuzhiyun CCDC_PIXFMT_YCBCR_8BIT,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun enum ccdc_frmfmt {
102*4882a593Smuzhiyun CCDC_FRMFMT_PROGRESSIVE = 0,
103*4882a593Smuzhiyun CCDC_FRMFMT_INTERLACED,
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* PIXEL ORDER IN MEMORY from LSB to MSB */
107*4882a593Smuzhiyun /* only applicable for 8-bit input mode */
108*4882a593Smuzhiyun enum ccdc_pixorder {
109*4882a593Smuzhiyun CCDC_PIXORDER_YCBYCR,
110*4882a593Smuzhiyun CCDC_PIXORDER_CBYCRY,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun enum ccdc_buftype {
114*4882a593Smuzhiyun CCDC_BUFTYPE_FLD_INTERLEAVED,
115*4882a593Smuzhiyun CCDC_BUFTYPE_FLD_SEPARATED
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* returns the highest bit used for the gamma */
ccdc_gamma_width_max_bit(enum vpfe_ccdc_gamma_width width)120*4882a593Smuzhiyun static inline u8 ccdc_gamma_width_max_bit(enum vpfe_ccdc_gamma_width width)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun return 15 - width;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* returns the highest bit used for this data size */
ccdc_data_size_max_bit(enum vpfe_ccdc_data_size sz)126*4882a593Smuzhiyun static inline u8 ccdc_data_size_max_bit(enum vpfe_ccdc_data_size sz)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun return sz == VPFE_CCDC_DATA_8BITS ? 7 : 15 - sz;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Structure for CCDC configuration parameters for raw capture mode */
132*4882a593Smuzhiyun struct ccdc_params_raw {
133*4882a593Smuzhiyun /* pixel format */
134*4882a593Smuzhiyun enum ccdc_pixfmt pix_fmt;
135*4882a593Smuzhiyun /* progressive or interlaced frame */
136*4882a593Smuzhiyun enum ccdc_frmfmt frm_fmt;
137*4882a593Smuzhiyun struct v4l2_rect win;
138*4882a593Smuzhiyun /* Current Format Bytes Per Pixels */
139*4882a593Smuzhiyun unsigned int bytesperpixel;
140*4882a593Smuzhiyun /* Current Format Bytes per Lines
141*4882a593Smuzhiyun * (Aligned to 32 bytes) used for HORZ_INFO
142*4882a593Smuzhiyun */
143*4882a593Smuzhiyun unsigned int bytesperline;
144*4882a593Smuzhiyun /* field id polarity */
145*4882a593Smuzhiyun enum vpfe_pin_pol fid_pol;
146*4882a593Smuzhiyun /* vertical sync polarity */
147*4882a593Smuzhiyun enum vpfe_pin_pol vd_pol;
148*4882a593Smuzhiyun /* horizontal sync polarity */
149*4882a593Smuzhiyun enum vpfe_pin_pol hd_pol;
150*4882a593Smuzhiyun /* interleaved or separated fields */
151*4882a593Smuzhiyun enum ccdc_buftype buf_type;
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun * enable to store the image in inverse
154*4882a593Smuzhiyun * order in memory(bottom to top)
155*4882a593Smuzhiyun */
156*4882a593Smuzhiyun unsigned char image_invert_enable;
157*4882a593Smuzhiyun /* configurable parameters */
158*4882a593Smuzhiyun struct vpfe_ccdc_config_params_raw config_params;
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun struct ccdc_params_ycbcr {
162*4882a593Smuzhiyun /* pixel format */
163*4882a593Smuzhiyun enum ccdc_pixfmt pix_fmt;
164*4882a593Smuzhiyun /* progressive or interlaced frame */
165*4882a593Smuzhiyun enum ccdc_frmfmt frm_fmt;
166*4882a593Smuzhiyun struct v4l2_rect win;
167*4882a593Smuzhiyun /* Current Format Bytes Per Pixels */
168*4882a593Smuzhiyun unsigned int bytesperpixel;
169*4882a593Smuzhiyun /* Current Format Bytes per Lines
170*4882a593Smuzhiyun * (Aligned to 32 bytes) used for HORZ_INFO
171*4882a593Smuzhiyun */
172*4882a593Smuzhiyun unsigned int bytesperline;
173*4882a593Smuzhiyun /* field id polarity */
174*4882a593Smuzhiyun enum vpfe_pin_pol fid_pol;
175*4882a593Smuzhiyun /* vertical sync polarity */
176*4882a593Smuzhiyun enum vpfe_pin_pol vd_pol;
177*4882a593Smuzhiyun /* horizontal sync polarity */
178*4882a593Smuzhiyun enum vpfe_pin_pol hd_pol;
179*4882a593Smuzhiyun /* enable BT.656 embedded sync mode */
180*4882a593Smuzhiyun int bt656_enable;
181*4882a593Smuzhiyun /* cb:y:cr:y or y:cb:y:cr in memory */
182*4882a593Smuzhiyun enum ccdc_pixorder pix_order;
183*4882a593Smuzhiyun /* interleaved or separated fields */
184*4882a593Smuzhiyun enum ccdc_buftype buf_type;
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /*
188*4882a593Smuzhiyun * CCDC operational configuration
189*4882a593Smuzhiyun */
190*4882a593Smuzhiyun struct ccdc_config {
191*4882a593Smuzhiyun /* CCDC interface type */
192*4882a593Smuzhiyun enum vpfe_hw_if_type if_type;
193*4882a593Smuzhiyun /* Raw Bayer configuration */
194*4882a593Smuzhiyun struct ccdc_params_raw bayer;
195*4882a593Smuzhiyun /* YCbCr configuration */
196*4882a593Smuzhiyun struct ccdc_params_ycbcr ycbcr;
197*4882a593Smuzhiyun /* ccdc base address */
198*4882a593Smuzhiyun void __iomem *base_addr;
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun struct vpfe_ccdc {
202*4882a593Smuzhiyun struct ccdc_config ccdc_cfg;
203*4882a593Smuzhiyun u32 ccdc_ctx[VPFE_REG_END / sizeof(u32)];
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /*
207*4882a593Smuzhiyun * struct vpfe_fmt - VPFE media bus format information
208*4882a593Smuzhiyun * fourcc: V4L2 pixel format code
209*4882a593Smuzhiyun * code: V4L2 media bus format code
210*4882a593Smuzhiyun * bitsperpixel: Bits per pixel over the bus
211*4882a593Smuzhiyun */
212*4882a593Smuzhiyun struct vpfe_fmt {
213*4882a593Smuzhiyun u32 fourcc;
214*4882a593Smuzhiyun u32 code;
215*4882a593Smuzhiyun u32 bitsperpixel;
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /*
219*4882a593Smuzhiyun * When formats[] is modified make sure to adjust this value also.
220*4882a593Smuzhiyun * Expect compile time warnings if VPFE_NUM_FORMATS is smaller then
221*4882a593Smuzhiyun * the number of elements in formats[].
222*4882a593Smuzhiyun */
223*4882a593Smuzhiyun #define VPFE_NUM_FORMATS 10
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun struct vpfe_device {
226*4882a593Smuzhiyun /* V4l2 specific parameters */
227*4882a593Smuzhiyun /* Identifies video device for this channel */
228*4882a593Smuzhiyun struct video_device video_dev;
229*4882a593Smuzhiyun /* sub devices */
230*4882a593Smuzhiyun struct v4l2_subdev **sd;
231*4882a593Smuzhiyun /* vpfe cfg */
232*4882a593Smuzhiyun struct vpfe_config *cfg;
233*4882a593Smuzhiyun /* V4l2 device */
234*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
235*4882a593Smuzhiyun /* parent device */
236*4882a593Smuzhiyun struct device *pdev;
237*4882a593Smuzhiyun /* subdevice async Notifier */
238*4882a593Smuzhiyun struct v4l2_async_notifier notifier;
239*4882a593Smuzhiyun /* Indicates id of the field which is being displayed */
240*4882a593Smuzhiyun unsigned field;
241*4882a593Smuzhiyun unsigned sequence;
242*4882a593Smuzhiyun /* current interface type */
243*4882a593Smuzhiyun struct vpfe_hw_if_param vpfe_if_params;
244*4882a593Smuzhiyun /* ptr to currently selected sub device */
245*4882a593Smuzhiyun struct vpfe_subdev_info *current_subdev;
246*4882a593Smuzhiyun /* current input at the sub device */
247*4882a593Smuzhiyun int current_input;
248*4882a593Smuzhiyun /* Keeps track of the information about the standard */
249*4882a593Smuzhiyun struct vpfe_std_info std_info;
250*4882a593Smuzhiyun /* std index into std table */
251*4882a593Smuzhiyun int std_index;
252*4882a593Smuzhiyun /* IRQs used when CCDC output to SDRAM */
253*4882a593Smuzhiyun unsigned int irq;
254*4882a593Smuzhiyun /* Pointer pointing to current v4l2_buffer */
255*4882a593Smuzhiyun struct vpfe_cap_buffer *cur_frm;
256*4882a593Smuzhiyun /* Pointer pointing to next v4l2_buffer */
257*4882a593Smuzhiyun struct vpfe_cap_buffer *next_frm;
258*4882a593Smuzhiyun /* Used to store pixel format */
259*4882a593Smuzhiyun struct v4l2_format fmt;
260*4882a593Smuzhiyun /* Used to keep a reference to the current vpfe_fmt */
261*4882a593Smuzhiyun struct vpfe_fmt *current_vpfe_fmt;
262*4882a593Smuzhiyun struct vpfe_fmt *active_fmt[VPFE_NUM_FORMATS];
263*4882a593Smuzhiyun unsigned int num_active_fmt;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /*
266*4882a593Smuzhiyun * used when IMP is chained to store the crop window which
267*4882a593Smuzhiyun * is different from the image window
268*4882a593Smuzhiyun */
269*4882a593Smuzhiyun struct v4l2_rect crop;
270*4882a593Smuzhiyun /* Buffer queue used in video-buf */
271*4882a593Smuzhiyun struct vb2_queue buffer_queue;
272*4882a593Smuzhiyun /* Queue of filled frames */
273*4882a593Smuzhiyun struct list_head dma_queue;
274*4882a593Smuzhiyun /* IRQ lock for DMA queue */
275*4882a593Smuzhiyun spinlock_t dma_queue_lock;
276*4882a593Smuzhiyun /* lock used to access this structure */
277*4882a593Smuzhiyun struct mutex lock;
278*4882a593Smuzhiyun /*
279*4882a593Smuzhiyun * offset where second field starts from the starting of the
280*4882a593Smuzhiyun * buffer for field separated YCbCr formats
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun u32 field_off;
283*4882a593Smuzhiyun struct vpfe_ccdc ccdc;
284*4882a593Smuzhiyun int stopping;
285*4882a593Smuzhiyun struct completion capture_stop;
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun #endif /* AM437X_VPFE_H */
289