1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* DMA controller registers */ 3*4882a593Smuzhiyun #define REG8_1(a0) ((const u16[8]) { a0, a0 + 1, a0 + 2, a0 + 3, \ 4*4882a593Smuzhiyun a0 + 4, a0 + 5, a0 + 6, a0 + 7}) 5*4882a593Smuzhiyun #define REG8_2(a0) ((const u16[8]) { a0, a0 + 2, a0 + 4, a0 + 6, \ 6*4882a593Smuzhiyun a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe}) 7*4882a593Smuzhiyun #define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \ 8*4882a593Smuzhiyun a0 + 0x20, a0 + 0x28, a0 + 0x30, \ 9*4882a593Smuzhiyun a0 + 0x38}) 10*4882a593Smuzhiyun #define INT_STATUS 0x00 11*4882a593Smuzhiyun #define PB_STATUS 0x01 12*4882a593Smuzhiyun #define DMA_CMD 0x02 13*4882a593Smuzhiyun #define VIDEO_FIFO_STATUS 0x03 14*4882a593Smuzhiyun #define VIDEO_CHANNEL_ID 0x04 15*4882a593Smuzhiyun #define VIDEO_PARSER_STATUS 0x05 16*4882a593Smuzhiyun #define SYS_SOFT_RST 0x06 17*4882a593Smuzhiyun #define DMA_PAGE_TABLE0_ADDR ((const u16[8]) { 0x08, 0xd0, 0xd2, 0xd4, \ 18*4882a593Smuzhiyun 0xd6, 0xd8, 0xda, 0xdc }) 19*4882a593Smuzhiyun #define DMA_PAGE_TABLE1_ADDR ((const u16[8]) { 0x09, 0xd1, 0xd3, 0xd5, \ 20*4882a593Smuzhiyun 0xd7, 0xd9, 0xdb, 0xdd }) 21*4882a593Smuzhiyun #define DMA_CHANNEL_ENABLE 0x0a 22*4882a593Smuzhiyun #define DMA_CONFIG 0x0b 23*4882a593Smuzhiyun #define DMA_TIMER_INTERVAL 0x0c 24*4882a593Smuzhiyun #define DMA_CHANNEL_TIMEOUT 0x0d 25*4882a593Smuzhiyun #define VDMA_CHANNEL_CONFIG REG8_1(0x10) 26*4882a593Smuzhiyun #define ADMA_P_ADDR REG8_2(0x18) 27*4882a593Smuzhiyun #define ADMA_B_ADDR REG8_2(0x19) 28*4882a593Smuzhiyun #define DMA10_P_ADDR 0x28 29*4882a593Smuzhiyun #define DMA10_B_ADDR 0x29 30*4882a593Smuzhiyun #define VIDEO_CONTROL1 0x2a 31*4882a593Smuzhiyun #define VIDEO_CONTROL2 0x2b 32*4882a593Smuzhiyun #define AUDIO_CONTROL1 0x2c 33*4882a593Smuzhiyun #define AUDIO_CONTROL2 0x2d 34*4882a593Smuzhiyun #define PHASE_REF 0x2e 35*4882a593Smuzhiyun #define GPIO_REG 0x2f 36*4882a593Smuzhiyun #define INTL_HBAR_CTRL REG8_1(0x30) 37*4882a593Smuzhiyun #define AUDIO_CONTROL3 0x38 38*4882a593Smuzhiyun #define VIDEO_FIELD_CTRL REG8_1(0x39) 39*4882a593Smuzhiyun #define HSCALER_CTRL REG8_1(0x42) 40*4882a593Smuzhiyun #define VIDEO_SIZE REG8_1(0x4A) 41*4882a593Smuzhiyun #define VIDEO_SIZE_F2 REG8_1(0x52) 42*4882a593Smuzhiyun #define MD_CONF REG8_1(0x60) 43*4882a593Smuzhiyun #define MD_INIT REG8_1(0x68) 44*4882a593Smuzhiyun #define MD_MAP0 REG8_1(0x70) 45*4882a593Smuzhiyun #define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */ 46*4882a593Smuzhiyun #define VDMA_WHP REG8_8(0x81) 47*4882a593Smuzhiyun #define VDMA_B_ADDR REG8_8(0x82) 48*4882a593Smuzhiyun #define VDMA_F2_P_ADDR REG8_8(0x84) 49*4882a593Smuzhiyun #define VDMA_F2_WHP REG8_8(0x85) 50*4882a593Smuzhiyun #define VDMA_F2_B_ADDR REG8_8(0x86) 51*4882a593Smuzhiyun #define EP_REG_ADDR 0xfe 52*4882a593Smuzhiyun #define EP_REG_DATA 0xff 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Video decoder registers */ 55*4882a593Smuzhiyun #define VDREG8(a0) ((const u16[8]) { \ 56*4882a593Smuzhiyun a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \ 57*4882a593Smuzhiyun a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130}) 58*4882a593Smuzhiyun #define VIDSTAT VDREG8(0x100) 59*4882a593Smuzhiyun #define BRIGHT VDREG8(0x101) 60*4882a593Smuzhiyun #define CONTRAST VDREG8(0x102) 61*4882a593Smuzhiyun #define SHARPNESS VDREG8(0x103) 62*4882a593Smuzhiyun #define SAT_U VDREG8(0x104) 63*4882a593Smuzhiyun #define SAT_V VDREG8(0x105) 64*4882a593Smuzhiyun #define HUE VDREG8(0x106) 65*4882a593Smuzhiyun #define CROP_HI VDREG8(0x107) 66*4882a593Smuzhiyun #define VDELAY_LO VDREG8(0x108) 67*4882a593Smuzhiyun #define VACTIVE_LO VDREG8(0x109) 68*4882a593Smuzhiyun #define HDELAY_LO VDREG8(0x10a) 69*4882a593Smuzhiyun #define HACTIVE_LO VDREG8(0x10b) 70*4882a593Smuzhiyun #define MVSN VDREG8(0x10c) 71*4882a593Smuzhiyun #define STATUS2 VDREG8(0x10d) 72*4882a593Smuzhiyun #define SDT VDREG8(0x10e) 73*4882a593Smuzhiyun #define SDT_EN VDREG8(0x10f) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define VSCALE_LO VDREG8(0x144) 76*4882a593Smuzhiyun #define SCALE_HI VDREG8(0x145) 77*4882a593Smuzhiyun #define HSCALE_LO VDREG8(0x146) 78*4882a593Smuzhiyun #define F2CROP_HI VDREG8(0x147) 79*4882a593Smuzhiyun #define F2VDELAY_LO VDREG8(0x148) 80*4882a593Smuzhiyun #define F2VACTIVE_LO VDREG8(0x149) 81*4882a593Smuzhiyun #define F2HDELAY_LO VDREG8(0x14a) 82*4882a593Smuzhiyun #define F2HACTIVE_LO VDREG8(0x14b) 83*4882a593Smuzhiyun #define F2VSCALE_LO VDREG8(0x14c) 84*4882a593Smuzhiyun #define F2SCALE_HI VDREG8(0x14d) 85*4882a593Smuzhiyun #define F2HSCALE_LO VDREG8(0x14e) 86*4882a593Smuzhiyun #define F2CNT VDREG8(0x14f) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define VDREG2(a0) ((const u16[2]) { a0, a0 + 0x100 }) 89*4882a593Smuzhiyun #define SRST VDREG2(0x180) 90*4882a593Smuzhiyun #define ACNTL VDREG2(0x181) 91*4882a593Smuzhiyun #define ACNTL2 VDREG2(0x182) 92*4882a593Smuzhiyun #define CNTRL1 VDREG2(0x183) 93*4882a593Smuzhiyun #define CKHY VDREG2(0x184) 94*4882a593Smuzhiyun #define SHCOR VDREG2(0x185) 95*4882a593Smuzhiyun #define CORING VDREG2(0x186) 96*4882a593Smuzhiyun #define CLMPG VDREG2(0x187) 97*4882a593Smuzhiyun #define IAGC VDREG2(0x188) 98*4882a593Smuzhiyun #define VCTRL1 VDREG2(0x18f) 99*4882a593Smuzhiyun #define MISC1 VDREG2(0x194) 100*4882a593Smuzhiyun #define LOOP VDREG2(0x195) 101*4882a593Smuzhiyun #define MISC2 VDREG2(0x196) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CLMD VDREG2(0x197) 104*4882a593Smuzhiyun #define ANPWRDOWN VDREG2(0x1ce) 105*4882a593Smuzhiyun #define AIGAIN ((const u16[8]) { 0x1d0, 0x1d1, 0x1d2, 0x1d3, \ 106*4882a593Smuzhiyun 0x2d0, 0x2d1, 0x2d2, 0x2d3 }) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define SYS_MODE_DMA_SHIFT 13 109*4882a593Smuzhiyun #define AUDIO_DMA_SIZE_SHIFT 19 110*4882a593Smuzhiyun #define AUDIO_DMA_SIZE_MIN SZ_512 111*4882a593Smuzhiyun #define AUDIO_DMA_SIZE_MAX SZ_4K 112*4882a593Smuzhiyun #define AUDIO_DMA_SIZE_MASK (SZ_8K - 1) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define DMA_CMD_ENABLE BIT(31) 115*4882a593Smuzhiyun #define INT_STATUS_DMA_TOUT BIT(17) 116*4882a593Smuzhiyun #define TW686X_VIDSTAT_HLOCK BIT(6) 117*4882a593Smuzhiyun #define TW686X_VIDSTAT_VDLOSS BIT(7) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define TW686X_STD_NTSC_M 0 120*4882a593Smuzhiyun #define TW686X_STD_PAL 1 121*4882a593Smuzhiyun #define TW686X_STD_SECAM 2 122*4882a593Smuzhiyun #define TW686X_STD_NTSC_443 3 123*4882a593Smuzhiyun #define TW686X_STD_PAL_M 4 124*4882a593Smuzhiyun #define TW686X_STD_PAL_CN 5 125*4882a593Smuzhiyun #define TW686X_STD_PAL_60 6 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define TW686X_FIELD_MODE 0x3 128*4882a593Smuzhiyun #define TW686X_FRAME_MODE 0x2 129*4882a593Smuzhiyun /* 0x1 is reserved */ 130*4882a593Smuzhiyun #define TW686X_SG_MODE 0x0 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define TW686X_FIFO_ERROR(x) (x & ~(0xff)) 133