xref: /OK3568_Linux_fs/kernel/drivers/media/pci/tw68/tw68.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  tw68 driver common header file
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Much of this code is derived from the cx88 and sa7134 drivers, which
6*4882a593Smuzhiyun  *  were in turn derived from the bt87x driver.  The original work was by
7*4882a593Smuzhiyun  *  Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
8*4882a593Smuzhiyun  *  Hans Verkuil, Andy Walls and many others.  Their work is gratefully
9*4882a593Smuzhiyun  *  acknowledged.  Full credit goes to them - any problems within this code
10*4882a593Smuzhiyun  *  are mine.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *  Copyright (C) 2009  William M. Brack
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *  Refactored and updated to the latest v4l core frameworks:
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  *  Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/pci.h>
20*4882a593Smuzhiyun #include <linux/videodev2.h>
21*4882a593Smuzhiyun #include <linux/notifier.h>
22*4882a593Smuzhiyun #include <linux/delay.h>
23*4882a593Smuzhiyun #include <linux/mutex.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <media/v4l2-common.h>
27*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
28*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
29*4882a593Smuzhiyun #include <media/v4l2-device.h>
30*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
31*4882a593Smuzhiyun #include <media/videobuf2-dma-sg.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "tw68-reg.h"
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define	UNSET	(-1U)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define TW68_NORMS ( \
38*4882a593Smuzhiyun 	V4L2_STD_NTSC    | V4L2_STD_PAL       | V4L2_STD_SECAM    | \
39*4882a593Smuzhiyun 	V4L2_STD_PAL_M   | V4L2_STD_PAL_Nc    | V4L2_STD_PAL_60)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define	TW68_VID_INTS	(TW68_FFERR | TW68_PABORT | TW68_DMAPERR | \
42*4882a593Smuzhiyun 			 TW68_FFOF   | TW68_DMAPI)
43*4882a593Smuzhiyun /* TW6800 chips have trouble with these, so we don't set them for that chip */
44*4882a593Smuzhiyun #define	TW68_VID_INTSX	(TW68_FDMIS | TW68_HLOCK | TW68_VLOCK)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define	TW68_I2C_INTS	(TW68_SBERR | TW68_SBDONE | TW68_SBERR2  | \
47*4882a593Smuzhiyun 			 TW68_SBDONE2)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun enum tw68_decoder_type {
50*4882a593Smuzhiyun 	TW6800,
51*4882a593Smuzhiyun 	TW6801,
52*4882a593Smuzhiyun 	TW6804,
53*4882a593Smuzhiyun 	TWXXXX,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* ----------------------------------------------------------- */
57*4882a593Smuzhiyun /* static data                                                 */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct tw68_tvnorm {
60*4882a593Smuzhiyun 	char		*name;
61*4882a593Smuzhiyun 	v4l2_std_id	id;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	/* video decoder */
64*4882a593Smuzhiyun 	u32	sync_control;
65*4882a593Smuzhiyun 	u32	luma_control;
66*4882a593Smuzhiyun 	u32	chroma_ctrl1;
67*4882a593Smuzhiyun 	u32	chroma_gain;
68*4882a593Smuzhiyun 	u32	chroma_ctrl2;
69*4882a593Smuzhiyun 	u32	vgate_misc;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* video scaler */
72*4882a593Smuzhiyun 	u32	h_delay;
73*4882a593Smuzhiyun 	u32	h_delay0;	/* for TW6800 */
74*4882a593Smuzhiyun 	u32	h_start;
75*4882a593Smuzhiyun 	u32	h_stop;
76*4882a593Smuzhiyun 	u32	v_delay;
77*4882a593Smuzhiyun 	u32	video_v_start;
78*4882a593Smuzhiyun 	u32	video_v_stop;
79*4882a593Smuzhiyun 	u32	vbi_v_start_0;
80*4882a593Smuzhiyun 	u32	vbi_v_stop_0;
81*4882a593Smuzhiyun 	u32	vbi_v_start_1;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/* Techwell specific */
84*4882a593Smuzhiyun 	u32	format;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun struct tw68_format {
88*4882a593Smuzhiyun 	u32	fourcc;
89*4882a593Smuzhiyun 	u32	depth;
90*4882a593Smuzhiyun 	u32	twformat;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /* ----------------------------------------------------------- */
94*4882a593Smuzhiyun /* card configuration					  */
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define TW68_BOARD_NOAUTO		UNSET
97*4882a593Smuzhiyun #define TW68_BOARD_UNKNOWN		0
98*4882a593Smuzhiyun #define	TW68_BOARD_GENERIC_6802		1
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define	TW68_MAXBOARDS			16
101*4882a593Smuzhiyun #define	TW68_INPUT_MAX			4
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* ----------------------------------------------------------- */
104*4882a593Smuzhiyun /* device / file handle status                                 */
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define	BUFFER_TIMEOUT	msecs_to_jiffies(500)	/* 0.5 seconds */
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun struct tw68_dev;	/* forward delclaration */
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* buffer for one video/vbi/ts frame */
111*4882a593Smuzhiyun struct tw68_buf {
112*4882a593Smuzhiyun 	struct vb2_v4l2_buffer vb;
113*4882a593Smuzhiyun 	struct list_head list;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	unsigned int   size;
116*4882a593Smuzhiyun 	__le32         *cpu;
117*4882a593Smuzhiyun 	__le32         *jmp;
118*4882a593Smuzhiyun 	dma_addr_t     dma;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun struct tw68_fmt {
122*4882a593Smuzhiyun 	char			*name;
123*4882a593Smuzhiyun 	u32			fourcc;	/* v4l2 format id */
124*4882a593Smuzhiyun 	int			depth;
125*4882a593Smuzhiyun 	int			flags;
126*4882a593Smuzhiyun 	u32			twformat;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* global device status */
130*4882a593Smuzhiyun struct tw68_dev {
131*4882a593Smuzhiyun 	struct mutex		lock;
132*4882a593Smuzhiyun 	spinlock_t		slock;
133*4882a593Smuzhiyun 	u16			instance;
134*4882a593Smuzhiyun 	struct v4l2_device	v4l2_dev;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* various device info */
137*4882a593Smuzhiyun 	enum tw68_decoder_type	vdecoder;
138*4882a593Smuzhiyun 	struct video_device	vdev;
139*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* pci i/o */
142*4882a593Smuzhiyun 	char			*name;
143*4882a593Smuzhiyun 	struct pci_dev		*pci;
144*4882a593Smuzhiyun 	unsigned char		pci_rev, pci_lat;
145*4882a593Smuzhiyun 	u32			__iomem *lmmio;
146*4882a593Smuzhiyun 	u8			__iomem *bmmio;
147*4882a593Smuzhiyun 	u32			pci_irqmask;
148*4882a593Smuzhiyun 	/* The irq mask to be used will depend upon the chip type */
149*4882a593Smuzhiyun 	u32			board_virqmask;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* video capture */
152*4882a593Smuzhiyun 	const struct tw68_format *fmt;
153*4882a593Smuzhiyun 	unsigned		width, height;
154*4882a593Smuzhiyun 	unsigned		seqnr;
155*4882a593Smuzhiyun 	unsigned		field;
156*4882a593Smuzhiyun 	struct vb2_queue	vidq;
157*4882a593Smuzhiyun 	struct list_head	active;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/* various v4l controls */
160*4882a593Smuzhiyun 	const struct tw68_tvnorm *tvnorm;	/* video */
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	int			input;
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /* ----------------------------------------------------------- */
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define tw_readl(reg)		readl(dev->lmmio + ((reg) >> 2))
168*4882a593Smuzhiyun #define	tw_readb(reg)		readb(dev->bmmio + (reg))
169*4882a593Smuzhiyun #define tw_writel(reg, value)	writel((value), dev->lmmio + ((reg) >> 2))
170*4882a593Smuzhiyun #define	tw_writeb(reg, value)	writeb((value), dev->bmmio + (reg))
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun #define tw_andorl(reg, mask, value) \
173*4882a593Smuzhiyun 		writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
174*4882a593Smuzhiyun 		((value) & (mask)), dev->lmmio+((reg)>>2))
175*4882a593Smuzhiyun #define	tw_andorb(reg, mask, value) \
176*4882a593Smuzhiyun 		writeb((readb(dev->bmmio + (reg)) & ~(mask)) |\
177*4882a593Smuzhiyun 		((value) & (mask)), dev->bmmio+(reg))
178*4882a593Smuzhiyun #define tw_setl(reg, bit)	tw_andorl((reg), (bit), (bit))
179*4882a593Smuzhiyun #define	tw_setb(reg, bit)	tw_andorb((reg), (bit), (bit))
180*4882a593Smuzhiyun #define	tw_clearl(reg, bit)	\
181*4882a593Smuzhiyun 		writel((readl(dev->lmmio + ((reg) >> 2)) & ~(bit)), \
182*4882a593Smuzhiyun 		dev->lmmio + ((reg) >> 2))
183*4882a593Smuzhiyun #define	tw_clearb(reg, bit)	\
184*4882a593Smuzhiyun 		writeb((readb(dev->bmmio+(reg)) & ~(bit)), \
185*4882a593Smuzhiyun 		dev->bmmio + (reg))
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun #define tw_wait(us) { udelay(us); }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* ----------------------------------------------------------- */
190*4882a593Smuzhiyun /* tw68-video.c                                                */
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun void tw68_set_tvnorm_hw(struct tw68_dev *dev);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun int tw68_video_init1(struct tw68_dev *dev);
195*4882a593Smuzhiyun int tw68_video_init2(struct tw68_dev *dev, int video_nr);
196*4882a593Smuzhiyun void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status);
197*4882a593Smuzhiyun int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /* ----------------------------------------------------------- */
200*4882a593Smuzhiyun /* tw68-risc.c                                                 */
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun int tw68_risc_buffer(struct pci_dev *pci, struct tw68_buf *buf,
203*4882a593Smuzhiyun 	struct scatterlist *sglist, unsigned int top_offset,
204*4882a593Smuzhiyun 	unsigned int bottom_offset, unsigned int bpl,
205*4882a593Smuzhiyun 	unsigned int padding, unsigned int lines);
206