1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tw68-reg.h - TW68xx register offsets 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Much of this code is derived from the cx88 and sa7134 drivers, which 6*4882a593Smuzhiyun * were in turn derived from the bt87x driver. The original work was by 7*4882a593Smuzhiyun * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, 8*4882a593Smuzhiyun * Hans Verkuil, Andy Walls and many others. Their work is gratefully 9*4882a593Smuzhiyun * acknowledged. Full credit goes to them - any problems within this code 10*4882a593Smuzhiyun * are mine. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Copyright (C) William M. Brack 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Refactored and updated to the latest v4l core frameworks: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef _TW68_REG_H_ 20*4882a593Smuzhiyun #define _TW68_REG_H_ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* ---------------------------------------------------------------------- */ 23*4882a593Smuzhiyun #define TW68_DMAC 0x000 24*4882a593Smuzhiyun #define TW68_DMAP_SA 0x004 25*4882a593Smuzhiyun #define TW68_DMAP_EXE 0x008 26*4882a593Smuzhiyun #define TW68_DMAP_PP 0x00c 27*4882a593Smuzhiyun #define TW68_VBIC 0x010 28*4882a593Smuzhiyun #define TW68_SBUSC 0x014 29*4882a593Smuzhiyun #define TW68_SBUSSD 0x018 30*4882a593Smuzhiyun #define TW68_INTSTAT 0x01C 31*4882a593Smuzhiyun #define TW68_INTMASK 0x020 32*4882a593Smuzhiyun #define TW68_GPIOC 0x024 33*4882a593Smuzhiyun #define TW68_GPOE 0x028 34*4882a593Smuzhiyun #define TW68_TESTREG 0x02C 35*4882a593Smuzhiyun #define TW68_SBUSRD 0x030 36*4882a593Smuzhiyun #define TW68_SBUS_TRIG 0x034 37*4882a593Smuzhiyun #define TW68_CAP_CTL 0x040 38*4882a593Smuzhiyun #define TW68_SUBSYS 0x054 39*4882a593Smuzhiyun #define TW68_I2C_RST 0x064 40*4882a593Smuzhiyun #define TW68_VBIINST 0x06C 41*4882a593Smuzhiyun /* define bits in FIFO and DMAP Control reg */ 42*4882a593Smuzhiyun #define TW68_DMAP_EN (1 << 0) 43*4882a593Smuzhiyun #define TW68_FIFO_EN (1 << 1) 44*4882a593Smuzhiyun /* define the Interrupt Status Register bits */ 45*4882a593Smuzhiyun #define TW68_SBDONE (1 << 0) 46*4882a593Smuzhiyun #define TW68_DMAPI (1 << 1) 47*4882a593Smuzhiyun #define TW68_GPINT (1 << 2) 48*4882a593Smuzhiyun #define TW68_FFOF (1 << 3) 49*4882a593Smuzhiyun #define TW68_FDMIS (1 << 4) 50*4882a593Smuzhiyun #define TW68_DMAPERR (1 << 5) 51*4882a593Smuzhiyun #define TW68_PABORT (1 << 6) 52*4882a593Smuzhiyun #define TW68_SBDONE2 (1 << 12) 53*4882a593Smuzhiyun #define TW68_SBERR2 (1 << 13) 54*4882a593Smuzhiyun #define TW68_PPERR (1 << 14) 55*4882a593Smuzhiyun #define TW68_FFERR (1 << 15) 56*4882a593Smuzhiyun #define TW68_DET50 (1 << 16) 57*4882a593Smuzhiyun #define TW68_FLOCK (1 << 17) 58*4882a593Smuzhiyun #define TW68_CCVALID (1 << 18) 59*4882a593Smuzhiyun #define TW68_VLOCK (1 << 19) 60*4882a593Smuzhiyun #define TW68_FIELD (1 << 20) 61*4882a593Smuzhiyun #define TW68_SLOCK (1 << 21) 62*4882a593Smuzhiyun #define TW68_HLOCK (1 << 22) 63*4882a593Smuzhiyun #define TW68_VDLOSS (1 << 23) 64*4882a593Smuzhiyun #define TW68_SBERR (1 << 24) 65*4882a593Smuzhiyun /* define the i2c control register bits */ 66*4882a593Smuzhiyun #define TW68_SBMODE (0) 67*4882a593Smuzhiyun #define TW68_WREN (1) 68*4882a593Smuzhiyun #define TW68_SSCLK (6) 69*4882a593Smuzhiyun #define TW68_SSDAT (7) 70*4882a593Smuzhiyun #define TW68_SBCLK (8) 71*4882a593Smuzhiyun #define TW68_WDLEN (16) 72*4882a593Smuzhiyun #define TW68_RDLEN (20) 73*4882a593Smuzhiyun #define TW68_SBRW (24) 74*4882a593Smuzhiyun #define TW68_SBDEV (25) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define TW68_SBMODE_B (1 << TW68_SBMODE) 77*4882a593Smuzhiyun #define TW68_WREN_B (1 << TW68_WREN) 78*4882a593Smuzhiyun #define TW68_SSCLK_B (1 << TW68_SSCLK) 79*4882a593Smuzhiyun #define TW68_SSDAT_B (1 << TW68_SSDAT) 80*4882a593Smuzhiyun #define TW68_SBRW_B (1 << TW68_SBRW) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define TW68_GPDATA 0x100 83*4882a593Smuzhiyun #define TW68_STATUS1 0x204 84*4882a593Smuzhiyun #define TW68_INFORM 0x208 85*4882a593Smuzhiyun #define TW68_OPFORM 0x20C 86*4882a593Smuzhiyun #define TW68_HSYNC 0x210 87*4882a593Smuzhiyun #define TW68_ACNTL 0x218 88*4882a593Smuzhiyun #define TW68_CROP_HI 0x21C 89*4882a593Smuzhiyun #define TW68_VDELAY_LO 0x220 90*4882a593Smuzhiyun #define TW68_VACTIVE_LO 0x224 91*4882a593Smuzhiyun #define TW68_HDELAY_LO 0x228 92*4882a593Smuzhiyun #define TW68_HACTIVE_LO 0x22C 93*4882a593Smuzhiyun #define TW68_CNTRL1 0x230 94*4882a593Smuzhiyun #define TW68_VSCALE_LO 0x234 95*4882a593Smuzhiyun #define TW68_SCALE_HI 0x238 96*4882a593Smuzhiyun #define TW68_HSCALE_LO 0x23C 97*4882a593Smuzhiyun #define TW68_BRIGHT 0x240 98*4882a593Smuzhiyun #define TW68_CONTRAST 0x244 99*4882a593Smuzhiyun #define TW68_SHARPNESS 0x248 100*4882a593Smuzhiyun #define TW68_SAT_U 0x24C 101*4882a593Smuzhiyun #define TW68_SAT_V 0x250 102*4882a593Smuzhiyun #define TW68_HUE 0x254 103*4882a593Smuzhiyun #define TW68_SHARP2 0x258 104*4882a593Smuzhiyun #define TW68_VSHARP 0x25C 105*4882a593Smuzhiyun #define TW68_CORING 0x260 106*4882a593Smuzhiyun #define TW68_VBICNTL 0x264 107*4882a593Smuzhiyun #define TW68_CNTRL2 0x268 108*4882a593Smuzhiyun #define TW68_CC_DATA 0x26C 109*4882a593Smuzhiyun #define TW68_SDT 0x270 110*4882a593Smuzhiyun #define TW68_SDTR 0x274 111*4882a593Smuzhiyun #define TW68_RESERV2 0x278 112*4882a593Smuzhiyun #define TW68_RESERV3 0x27C 113*4882a593Smuzhiyun #define TW68_CLMPG 0x280 114*4882a593Smuzhiyun #define TW68_IAGC 0x284 115*4882a593Smuzhiyun #define TW68_AGCGAIN 0x288 116*4882a593Smuzhiyun #define TW68_PEAKWT 0x28C 117*4882a593Smuzhiyun #define TW68_CLMPL 0x290 118*4882a593Smuzhiyun #define TW68_SYNCT 0x294 119*4882a593Smuzhiyun #define TW68_MISSCNT 0x298 120*4882a593Smuzhiyun #define TW68_PCLAMP 0x29C 121*4882a593Smuzhiyun #define TW68_VCNTL1 0x2A0 122*4882a593Smuzhiyun #define TW68_VCNTL2 0x2A4 123*4882a593Smuzhiyun #define TW68_CKILL 0x2A8 124*4882a593Smuzhiyun #define TW68_COMB 0x2AC 125*4882a593Smuzhiyun #define TW68_LDLY 0x2B0 126*4882a593Smuzhiyun #define TW68_MISC1 0x2B4 127*4882a593Smuzhiyun #define TW68_LOOP 0x2B8 128*4882a593Smuzhiyun #define TW68_MISC2 0x2BC 129*4882a593Smuzhiyun #define TW68_MVSN 0x2C0 130*4882a593Smuzhiyun #define TW68_STATUS2 0x2C4 131*4882a593Smuzhiyun #define TW68_HFREF 0x2C8 132*4882a593Smuzhiyun #define TW68_CLMD 0x2CC 133*4882a593Smuzhiyun #define TW68_IDCNTL 0x2D0 134*4882a593Smuzhiyun #define TW68_CLCNTL1 0x2D4 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Audio */ 137*4882a593Smuzhiyun #define TW68_ACKI1 0x300 138*4882a593Smuzhiyun #define TW68_ACKI2 0x304 139*4882a593Smuzhiyun #define TW68_ACKI3 0x308 140*4882a593Smuzhiyun #define TW68_ACKN1 0x30C 141*4882a593Smuzhiyun #define TW68_ACKN2 0x310 142*4882a593Smuzhiyun #define TW68_ACKN3 0x314 143*4882a593Smuzhiyun #define TW68_SDIV 0x318 144*4882a593Smuzhiyun #define TW68_LRDIV 0x31C 145*4882a593Smuzhiyun #define TW68_ACCNTL 0x320 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define TW68_VSCTL 0x3B8 148*4882a593Smuzhiyun #define TW68_CHROMAGVAL 0x3BC 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define TW68_F2CROP_HI 0x3DC 151*4882a593Smuzhiyun #define TW68_F2VDELAY_LO 0x3E0 152*4882a593Smuzhiyun #define TW68_F2VACTIVE_LO 0x3E4 153*4882a593Smuzhiyun #define TW68_F2HDELAY_LO 0x3E8 154*4882a593Smuzhiyun #define TW68_F2HACTIVE_LO 0x3EC 155*4882a593Smuzhiyun #define TW68_F2CNT 0x3F0 156*4882a593Smuzhiyun #define TW68_F2VSCALE_LO 0x3F4 157*4882a593Smuzhiyun #define TW68_F2SCALE_HI 0x3F8 158*4882a593Smuzhiyun #define TW68_F2HSCALE_LO 0x3FC 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define RISC_INT_BIT 0x08000000 161*4882a593Smuzhiyun #define RISC_SYNCO 0xC0000000 162*4882a593Smuzhiyun #define RISC_SYNCE 0xD0000000 163*4882a593Smuzhiyun #define RISC_JUMP 0xB0000000 164*4882a593Smuzhiyun #define RISC_LINESTART 0x90000000 165*4882a593Smuzhiyun #define RISC_INLINE 0xA0000000 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define VideoFormatNTSC 0 168*4882a593Smuzhiyun #define VideoFormatNTSCJapan 0 169*4882a593Smuzhiyun #define VideoFormatPALBDGHI 1 170*4882a593Smuzhiyun #define VideoFormatSECAM 2 171*4882a593Smuzhiyun #define VideoFormatNTSC443 3 172*4882a593Smuzhiyun #define VideoFormatPALM 4 173*4882a593Smuzhiyun #define VideoFormatPALN 5 174*4882a593Smuzhiyun #define VideoFormatPALNC 5 175*4882a593Smuzhiyun #define VideoFormatPAL60 6 176*4882a593Smuzhiyun #define VideoFormatAuto 7 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define ColorFormatRGB32 0x00 179*4882a593Smuzhiyun #define ColorFormatRGB24 0x10 180*4882a593Smuzhiyun #define ColorFormatRGB16 0x20 181*4882a593Smuzhiyun #define ColorFormatRGB15 0x30 182*4882a593Smuzhiyun #define ColorFormatYUY2 0x40 183*4882a593Smuzhiyun #define ColorFormatBSWAP 0x04 184*4882a593Smuzhiyun #define ColorFormatWSWAP 0x08 185*4882a593Smuzhiyun #define ColorFormatGamma 0x80 186*4882a593Smuzhiyun #endif 187