xref: /OK3568_Linux_fs/kernel/drivers/media/pci/ttpci/budget-patch.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * budget-patch.c: driver for Budget Patch,
4*4882a593Smuzhiyun  * hardware modification of DVB-S cards enabling full TS
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Written by Emard <emard@softhome.net>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Original idea by Roberto Deza <rdeza@unav.es>
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Special thanks to Holger Waechtler, Michael Hunold, Marian Durkovic
11*4882a593Smuzhiyun  * and Metzlerbros
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * the project's page is at https://linuxtv.org
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "av7110.h"
17*4882a593Smuzhiyun #include "av7110_hw.h"
18*4882a593Smuzhiyun #include "budget.h"
19*4882a593Smuzhiyun #include "stv0299.h"
20*4882a593Smuzhiyun #include "ves1x93.h"
21*4882a593Smuzhiyun #include "tda8083.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "bsru6.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define budget_patch budget
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static struct saa7146_extension budget_extension;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun MAKE_BUDGET_INFO(ttbp, "TT-Budget/Patch DVB-S 1.x PCI", BUDGET_PATCH);
32*4882a593Smuzhiyun //MAKE_BUDGET_INFO(satel,"TT-Budget/Patch SATELCO PCI", BUDGET_TT_HW_DISEQC);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static const struct pci_device_id pci_tbl[] = {
35*4882a593Smuzhiyun 	MAKE_EXTENSION_PCI(ttbp,0x13c2, 0x0000),
36*4882a593Smuzhiyun //        MAKE_EXTENSION_PCI(satel, 0x13c2, 0x1013),
37*4882a593Smuzhiyun 	{
38*4882a593Smuzhiyun 		.vendor    = 0,
39*4882a593Smuzhiyun 	}
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* those lines are for budget-patch to be tried
43*4882a593Smuzhiyun ** on a true budget card and observe the
44*4882a593Smuzhiyun ** behaviour of VSYNC generated by rps1.
45*4882a593Smuzhiyun ** this code was shamelessly copy/pasted from budget.c
46*4882a593Smuzhiyun */
gpio_Set22K(struct budget * budget,int state)47*4882a593Smuzhiyun static void gpio_Set22K (struct budget *budget, int state)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun 	struct saa7146_dev *dev=budget->dev;
50*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
51*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, (state ? SAA7146_GPIO_OUTHI : SAA7146_GPIO_OUTLO));
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* Diseqc functions only for TT Budget card */
55*4882a593Smuzhiyun /* taken from the Skyvision DVB driver by
56*4882a593Smuzhiyun    Ralph Metzler <rjkm@metzlerbros.de> */
57*4882a593Smuzhiyun 
DiseqcSendBit(struct budget * budget,int data)58*4882a593Smuzhiyun static void DiseqcSendBit (struct budget *budget, int data)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	struct saa7146_dev *dev=budget->dev;
61*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
64*4882a593Smuzhiyun 	udelay(data ? 500 : 1000);
65*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
66*4882a593Smuzhiyun 	udelay(data ? 1000 : 500);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
DiseqcSendByte(struct budget * budget,int data)69*4882a593Smuzhiyun static void DiseqcSendByte (struct budget *budget, int data)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	int i, par=1, d;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	for (i=7; i>=0; i--) {
76*4882a593Smuzhiyun 		d = (data>>i)&1;
77*4882a593Smuzhiyun 		par ^= d;
78*4882a593Smuzhiyun 		DiseqcSendBit(budget, d);
79*4882a593Smuzhiyun 	}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	DiseqcSendBit(budget, par);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
SendDiSEqCMsg(struct budget * budget,int len,u8 * msg,unsigned long burst)84*4882a593Smuzhiyun static int SendDiSEqCMsg (struct budget *budget, int len, u8 *msg, unsigned long burst)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	struct saa7146_dev *dev=budget->dev;
87*4882a593Smuzhiyun 	int i;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
92*4882a593Smuzhiyun 	mdelay(16);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	for (i=0; i<len; i++)
95*4882a593Smuzhiyun 		DiseqcSendByte(budget, msg[i]);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	mdelay(16);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	if (burst!=-1) {
100*4882a593Smuzhiyun 		if (burst)
101*4882a593Smuzhiyun 			DiseqcSendByte(budget, 0xff);
102*4882a593Smuzhiyun 		else {
103*4882a593Smuzhiyun 			saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
104*4882a593Smuzhiyun 			mdelay(12);
105*4882a593Smuzhiyun 			udelay(500);
106*4882a593Smuzhiyun 			saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
107*4882a593Smuzhiyun 		}
108*4882a593Smuzhiyun 		msleep(20);
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* shamelessly copy/pasted from budget.c */
budget_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)115*4882a593Smuzhiyun static int budget_set_tone(struct dvb_frontend *fe,
116*4882a593Smuzhiyun 			   enum fe_sec_tone_mode tone)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct budget* budget = (struct budget*) fe->dvb->priv;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	switch (tone) {
121*4882a593Smuzhiyun 	case SEC_TONE_ON:
122*4882a593Smuzhiyun 		gpio_Set22K (budget, 1);
123*4882a593Smuzhiyun 		break;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	case SEC_TONE_OFF:
126*4882a593Smuzhiyun 		gpio_Set22K (budget, 0);
127*4882a593Smuzhiyun 		break;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	default:
130*4882a593Smuzhiyun 		return -EINVAL;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
budget_diseqc_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)136*4882a593Smuzhiyun static int budget_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct budget* budget = (struct budget*) fe->dvb->priv;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	SendDiSEqCMsg (budget, cmd->msg_len, cmd->msg, 0);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
budget_diseqc_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd minicmd)145*4882a593Smuzhiyun static int budget_diseqc_send_burst(struct dvb_frontend *fe,
146*4882a593Smuzhiyun 				    enum fe_sec_mini_cmd minicmd)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	struct budget* budget = (struct budget*) fe->dvb->priv;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	SendDiSEqCMsg (budget, 0, NULL, minicmd);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	return 0;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
budget_av7110_send_fw_cmd(struct budget_patch * budget,u16 * buf,int length)155*4882a593Smuzhiyun static int budget_av7110_send_fw_cmd(struct budget_patch *budget, u16* buf, int length)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	int i;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	for (i = 2; i < length; i++)
162*4882a593Smuzhiyun 	{
163*4882a593Smuzhiyun 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2*i, 2, (u32) buf[i], 0,0);
164*4882a593Smuzhiyun 		  msleep(5);
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 	if (length)
167*4882a593Smuzhiyun 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, (u32) buf[1], 0,0);
168*4882a593Smuzhiyun 	else
169*4882a593Smuzhiyun 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, 0, 0,0);
170*4882a593Smuzhiyun 	msleep(5);
171*4882a593Smuzhiyun 	ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND, 2, (u32) buf[0], 0,0);
172*4882a593Smuzhiyun 	msleep(5);
173*4882a593Smuzhiyun 	return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
av7110_set22k(struct budget_patch * budget,int state)176*4882a593Smuzhiyun static void av7110_set22k(struct budget_patch *budget, int state)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	u16 buf[2] = {( COMTYPE_AUDIODAC << 8) | (state ? ON22K : OFF22K), 0};
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
181*4882a593Smuzhiyun 	budget_av7110_send_fw_cmd(budget, buf, 2);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
av7110_send_diseqc_msg(struct budget_patch * budget,int len,u8 * msg,int burst)184*4882a593Smuzhiyun static int av7110_send_diseqc_msg(struct budget_patch *budget, int len, u8 *msg, int burst)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	int i;
187*4882a593Smuzhiyun 	u16 buf[18] = { ((COMTYPE_AUDIODAC << 8) | SendDiSEqC),
188*4882a593Smuzhiyun 		16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	if (len>10)
193*4882a593Smuzhiyun 		len=10;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	buf[1] = len+2;
196*4882a593Smuzhiyun 	buf[2] = len;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	if (burst != -1)
199*4882a593Smuzhiyun 		buf[3]=burst ? 0x01 : 0x00;
200*4882a593Smuzhiyun 	else
201*4882a593Smuzhiyun 		buf[3]=0xffff;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	for (i=0; i<len; i++)
204*4882a593Smuzhiyun 		buf[i+4]=msg[i];
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	budget_av7110_send_fw_cmd(budget, buf, 18);
207*4882a593Smuzhiyun 	return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
budget_patch_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)210*4882a593Smuzhiyun static int budget_patch_set_tone(struct dvb_frontend *fe,
211*4882a593Smuzhiyun 				 enum fe_sec_tone_mode tone)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	switch (tone) {
216*4882a593Smuzhiyun 	case SEC_TONE_ON:
217*4882a593Smuzhiyun 		av7110_set22k (budget, 1);
218*4882a593Smuzhiyun 		break;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	case SEC_TONE_OFF:
221*4882a593Smuzhiyun 		av7110_set22k (budget, 0);
222*4882a593Smuzhiyun 		break;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	default:
225*4882a593Smuzhiyun 		return -EINVAL;
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	return 0;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun 
budget_patch_diseqc_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)231*4882a593Smuzhiyun static int budget_patch_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	av7110_send_diseqc_msg (budget, cmd->msg_len, cmd->msg, 0);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
budget_patch_diseqc_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd minicmd)240*4882a593Smuzhiyun static int budget_patch_diseqc_send_burst(struct dvb_frontend *fe,
241*4882a593Smuzhiyun 					  enum fe_sec_mini_cmd minicmd)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	av7110_send_diseqc_msg (budget, 0, NULL, minicmd);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return 0;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
alps_bsrv2_tuner_set_params(struct dvb_frontend * fe)250*4882a593Smuzhiyun static int alps_bsrv2_tuner_set_params(struct dvb_frontend *fe)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
253*4882a593Smuzhiyun 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
254*4882a593Smuzhiyun 	u8 pwr = 0;
255*4882a593Smuzhiyun 	u8 buf[4];
256*4882a593Smuzhiyun 	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
257*4882a593Smuzhiyun 	u32 div = (p->frequency + 479500) / 125;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	if (p->frequency > 2000000)
260*4882a593Smuzhiyun 		pwr = 3;
261*4882a593Smuzhiyun 	else if (p->frequency > 1800000)
262*4882a593Smuzhiyun 		pwr = 2;
263*4882a593Smuzhiyun 	else if (p->frequency > 1600000)
264*4882a593Smuzhiyun 		pwr = 1;
265*4882a593Smuzhiyun 	else if (p->frequency > 1200000)
266*4882a593Smuzhiyun 		pwr = 0;
267*4882a593Smuzhiyun 	else if (p->frequency >= 1100000)
268*4882a593Smuzhiyun 		pwr = 1;
269*4882a593Smuzhiyun 	else pwr = 2;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	buf[0] = (div >> 8) & 0x7f;
272*4882a593Smuzhiyun 	buf[1] = div & 0xff;
273*4882a593Smuzhiyun 	buf[2] = ((div & 0x18000) >> 10) | 0x95;
274*4882a593Smuzhiyun 	buf[3] = (pwr << 6) | 0x30;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	// NOTE: since we're using a prescaler of 2, we set the
277*4882a593Smuzhiyun 	// divisor frequency to 62.5kHz and divide by 125 above
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
280*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1);
281*4882a593Smuzhiyun 	if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1)
282*4882a593Smuzhiyun 		return -EIO;
283*4882a593Smuzhiyun 	return 0;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun static struct ves1x93_config alps_bsrv2_config = {
287*4882a593Smuzhiyun 	.demod_address = 0x08,
288*4882a593Smuzhiyun 	.xin = 90100000UL,
289*4882a593Smuzhiyun 	.invert_pwm = 0,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun 
grundig_29504_451_tuner_set_params(struct dvb_frontend * fe)292*4882a593Smuzhiyun static int grundig_29504_451_tuner_set_params(struct dvb_frontend *fe)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
295*4882a593Smuzhiyun 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
296*4882a593Smuzhiyun 	u32 div;
297*4882a593Smuzhiyun 	u8 data[4];
298*4882a593Smuzhiyun 	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	div = p->frequency / 125;
301*4882a593Smuzhiyun 	data[0] = (div >> 8) & 0x7f;
302*4882a593Smuzhiyun 	data[1] = div & 0xff;
303*4882a593Smuzhiyun 	data[2] = 0x8e;
304*4882a593Smuzhiyun 	data[3] = 0x00;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
307*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1);
308*4882a593Smuzhiyun 	if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1)
309*4882a593Smuzhiyun 		return -EIO;
310*4882a593Smuzhiyun 	return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun static struct tda8083_config grundig_29504_451_config = {
314*4882a593Smuzhiyun 	.demod_address = 0x68,
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
frontend_init(struct budget_patch * budget)317*4882a593Smuzhiyun static void frontend_init(struct budget_patch* budget)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun 	switch(budget->dev->pci->subsystem_device) {
320*4882a593Smuzhiyun 	case 0x0000: // Hauppauge/TT WinTV DVB-S rev1.X
321*4882a593Smuzhiyun 	case 0x1013: // SATELCO Multimedia PCI
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 		// try the ALPS BSRV2 first of all
324*4882a593Smuzhiyun 		budget->dvb_frontend = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &budget->i2c_adap);
325*4882a593Smuzhiyun 		if (budget->dvb_frontend) {
326*4882a593Smuzhiyun 			budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params;
327*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_patch_diseqc_send_master_cmd;
328*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_burst = budget_patch_diseqc_send_burst;
329*4882a593Smuzhiyun 			budget->dvb_frontend->ops.set_tone = budget_patch_set_tone;
330*4882a593Smuzhiyun 			break;
331*4882a593Smuzhiyun 		}
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 		// try the ALPS BSRU6 now
334*4882a593Smuzhiyun 		budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config, &budget->i2c_adap);
335*4882a593Smuzhiyun 		if (budget->dvb_frontend) {
336*4882a593Smuzhiyun 			budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
337*4882a593Smuzhiyun 			budget->dvb_frontend->tuner_priv = &budget->i2c_adap;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd;
340*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst;
341*4882a593Smuzhiyun 			budget->dvb_frontend->ops.set_tone = budget_set_tone;
342*4882a593Smuzhiyun 			break;
343*4882a593Smuzhiyun 		}
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 		// Try the grundig 29504-451
346*4882a593Smuzhiyun 		budget->dvb_frontend = dvb_attach(tda8083_attach, &grundig_29504_451_config, &budget->i2c_adap);
347*4882a593Smuzhiyun 		if (budget->dvb_frontend) {
348*4882a593Smuzhiyun 			budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params;
349*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd;
350*4882a593Smuzhiyun 			budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst;
351*4882a593Smuzhiyun 			budget->dvb_frontend->ops.set_tone = budget_set_tone;
352*4882a593Smuzhiyun 			break;
353*4882a593Smuzhiyun 		}
354*4882a593Smuzhiyun 		break;
355*4882a593Smuzhiyun 	}
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	if (budget->dvb_frontend == NULL) {
358*4882a593Smuzhiyun 		printk("dvb-ttpci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
359*4882a593Smuzhiyun 		       budget->dev->pci->vendor,
360*4882a593Smuzhiyun 		       budget->dev->pci->device,
361*4882a593Smuzhiyun 		       budget->dev->pci->subsystem_vendor,
362*4882a593Smuzhiyun 		       budget->dev->pci->subsystem_device);
363*4882a593Smuzhiyun 	} else {
364*4882a593Smuzhiyun 		if (dvb_register_frontend(&budget->dvb_adapter, budget->dvb_frontend)) {
365*4882a593Smuzhiyun 			printk("budget-av: Frontend registration failed!\n");
366*4882a593Smuzhiyun 			dvb_frontend_detach(budget->dvb_frontend);
367*4882a593Smuzhiyun 			budget->dvb_frontend = NULL;
368*4882a593Smuzhiyun 		}
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun /* written by Emard */
budget_patch_attach(struct saa7146_dev * dev,struct saa7146_pci_extension_data * info)373*4882a593Smuzhiyun static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_extension_data *info)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	struct budget_patch *budget;
376*4882a593Smuzhiyun 	int err;
377*4882a593Smuzhiyun 	int count = 0;
378*4882a593Smuzhiyun 	int detected = 0;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #define PATCH_RESET 0
381*4882a593Smuzhiyun #define RPS_IRQ 0
382*4882a593Smuzhiyun #define HPS_SETUP 0
383*4882a593Smuzhiyun #if PATCH_RESET
384*4882a593Smuzhiyun 	saa7146_write(dev, MC1, MASK_31);
385*4882a593Smuzhiyun 	msleep(40);
386*4882a593Smuzhiyun #endif
387*4882a593Smuzhiyun #if HPS_SETUP
388*4882a593Smuzhiyun 	// initialize registers. Better to have it like this
389*4882a593Smuzhiyun 	// than leaving something unconfigured
390*4882a593Smuzhiyun 	saa7146_write(dev, DD1_STREAM_B, 0);
391*4882a593Smuzhiyun 	// port B VSYNC at rising edge
392*4882a593Smuzhiyun 	saa7146_write(dev, DD1_INIT, 0x00000200);  // have this in budget-core too!
393*4882a593Smuzhiyun 	saa7146_write(dev, BRS_CTRL, 0x00000000);  // VBI
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	// debi config
396*4882a593Smuzhiyun 	// saa7146_write(dev, DEBI_CONFIG, MASK_30|MASK_28|MASK_18);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	// zero all HPS registers
399*4882a593Smuzhiyun 	saa7146_write(dev, HPS_H_PRESCALE, 0);                  // r68
400*4882a593Smuzhiyun 	saa7146_write(dev, HPS_H_SCALE, 0);                     // r6c
401*4882a593Smuzhiyun 	saa7146_write(dev, BCS_CTRL, 0);                        // r70
402*4882a593Smuzhiyun 	saa7146_write(dev, HPS_V_SCALE, 0);                     // r60
403*4882a593Smuzhiyun 	saa7146_write(dev, HPS_V_GAIN, 0);                      // r64
404*4882a593Smuzhiyun 	saa7146_write(dev, CHROMA_KEY_RANGE, 0);                // r74
405*4882a593Smuzhiyun 	saa7146_write(dev, CLIP_FORMAT_CTRL, 0);                // r78
406*4882a593Smuzhiyun 	// Set HPS prescaler for port B input
407*4882a593Smuzhiyun 	saa7146_write(dev, HPS_CTRL, (1<<30) | (0<<29) | (1<<28) | (0<<12) );
408*4882a593Smuzhiyun 	saa7146_write(dev, MC2,
409*4882a593Smuzhiyun 	  0 * (MASK_08 | MASK_24)  |   // BRS control
410*4882a593Smuzhiyun 	  0 * (MASK_09 | MASK_25)  |   // a
411*4882a593Smuzhiyun 	  0 * (MASK_10 | MASK_26)  |   // b
412*4882a593Smuzhiyun 	  1 * (MASK_06 | MASK_22)  |   // HPS_CTRL1
413*4882a593Smuzhiyun 	  1 * (MASK_05 | MASK_21)  |   // HPS_CTRL2
414*4882a593Smuzhiyun 	  0 * (MASK_01 | MASK_15)      // DEBI
415*4882a593Smuzhiyun 	   );
416*4882a593Smuzhiyun #endif
417*4882a593Smuzhiyun 	// Disable RPS1 and RPS0
418*4882a593Smuzhiyun 	saa7146_write(dev, MC1, ( MASK_29 | MASK_28));
419*4882a593Smuzhiyun 	// RPS1 timeout disable
420*4882a593Smuzhiyun 	saa7146_write(dev, RPS_TOV1, 0);
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	// code for autodetection
423*4882a593Smuzhiyun 	// will wait for VBI_B event (vertical blank at port B)
424*4882a593Smuzhiyun 	// and will reset GPIO3 after VBI_B is detected.
425*4882a593Smuzhiyun 	// (GPIO3 should be raised high by CPU to
426*4882a593Smuzhiyun 	// test if GPIO3 will generate vertical blank signal
427*4882a593Smuzhiyun 	// in budget patch GPIO3 is connected to VSYNC_B
428*4882a593Smuzhiyun 	count = 0;
429*4882a593Smuzhiyun #if 0
430*4882a593Smuzhiyun 	WRITE_RPS1(CMD_UPLOAD |
431*4882a593Smuzhiyun 	  MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 );
432*4882a593Smuzhiyun #endif
433*4882a593Smuzhiyun 	WRITE_RPS1(CMD_PAUSE | EVT_VBI_B);
434*4882a593Smuzhiyun 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
435*4882a593Smuzhiyun 	WRITE_RPS1(GPIO3_MSK);
436*4882a593Smuzhiyun 	WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
437*4882a593Smuzhiyun #if RPS_IRQ
438*4882a593Smuzhiyun 	// issue RPS1 interrupt to increment counter
439*4882a593Smuzhiyun 	WRITE_RPS1(CMD_INTERRUPT);
440*4882a593Smuzhiyun 	// at least a NOP is neede between two interrupts
441*4882a593Smuzhiyun 	WRITE_RPS1(CMD_NOP);
442*4882a593Smuzhiyun 	// interrupt again
443*4882a593Smuzhiyun 	WRITE_RPS1(CMD_INTERRUPT);
444*4882a593Smuzhiyun #endif
445*4882a593Smuzhiyun 	WRITE_RPS1(CMD_STOP);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun #if RPS_IRQ
448*4882a593Smuzhiyun 	// set event counter 1 source as RPS1 interrupt (0x03)          (rE4 p53)
449*4882a593Smuzhiyun 	// use 0x03 to track RPS1 interrupts - increase by 1 every gpio3 is toggled
450*4882a593Smuzhiyun 	// use 0x15 to track VPE  interrupts - increase by 1 every vpeirq() is called
451*4882a593Smuzhiyun 	saa7146_write(dev, EC1SSR, (0x03<<2) | 3 );
452*4882a593Smuzhiyun 	// set event counter 1 threshold to maximum allowed value        (rEC p55)
453*4882a593Smuzhiyun 	saa7146_write(dev, ECT1R,  0x3fff );
454*4882a593Smuzhiyun #endif
455*4882a593Smuzhiyun 	// Fix VSYNC level
456*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
457*4882a593Smuzhiyun 	// Set RPS1 Address register to point to RPS code               (r108 p42)
458*4882a593Smuzhiyun 	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
459*4882a593Smuzhiyun 	// Enable RPS1,                                                 (rFC p33)
460*4882a593Smuzhiyun 	saa7146_write(dev, MC1, (MASK_13 | MASK_29 ));
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	mdelay(50);
464*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
465*4882a593Smuzhiyun 	mdelay(150);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	if( (saa7146_read(dev, GPIO_CTRL) & 0x10000000) == 0)
469*4882a593Smuzhiyun 		detected = 1;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun #if RPS_IRQ
472*4882a593Smuzhiyun 	printk("Event Counter 1 0x%04x\n", saa7146_read(dev, EC1R) & 0x3fff );
473*4882a593Smuzhiyun #endif
474*4882a593Smuzhiyun 	// Disable RPS1
475*4882a593Smuzhiyun 	saa7146_write(dev, MC1, ( MASK_29 ));
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	if(detected == 0)
478*4882a593Smuzhiyun 		printk("budget-patch not detected or saa7146 in non-default state.\n"
479*4882a593Smuzhiyun 		       "try enabling resetting of 7146 with MASK_31 in MC1 register\n");
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	else
482*4882a593Smuzhiyun 		printk("BUDGET-PATCH DETECTED.\n");
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun /*      OLD (Original design by Roberto Deza):
486*4882a593Smuzhiyun **      This code will setup the SAA7146_RPS1 to generate a square
487*4882a593Smuzhiyun **      wave on GPIO3, changing when a field (TS_HEIGHT/2 "lines" of
488*4882a593Smuzhiyun **      TS_WIDTH packets) has been acquired on SAA7146_D1B video port;
489*4882a593Smuzhiyun **      then, this GPIO3 output which is connected to the D1B_VSYNC
490*4882a593Smuzhiyun **      input, will trigger the acquisition of the alternate field
491*4882a593Smuzhiyun **      and so on.
492*4882a593Smuzhiyun **      Currently, the TT_budget / WinTV_Nova cards have two ICs
493*4882a593Smuzhiyun **      (74HCT4040, LVC74) for the generation of this VSYNC signal,
494*4882a593Smuzhiyun **      which seems that can be done perfectly without this :-)).
495*4882a593Smuzhiyun */
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun /*      New design (By Emard)
498*4882a593Smuzhiyun **      this rps1 code will copy internal HS event to GPIO3 pin.
499*4882a593Smuzhiyun **      GPIO3 is in budget-patch hardware connected to port B VSYNC
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun **      HS is an internal event of 7146, accessible with RPS
502*4882a593Smuzhiyun **      and temporarily raised high every n lines
503*4882a593Smuzhiyun **      (n in defined in the RPS_THRESH1 counter threshold)
504*4882a593Smuzhiyun **      I think HS is raised high on the beginning of the n-th line
505*4882a593Smuzhiyun **      and remains high until this n-th line that triggered
506*4882a593Smuzhiyun **      it is completely received. When the reception of n-th line
507*4882a593Smuzhiyun **      ends, HS is lowered.
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun **      To transmit data over DMA, 7146 needs changing state at
510*4882a593Smuzhiyun **      port B VSYNC pin. Any changing of port B VSYNC will
511*4882a593Smuzhiyun **      cause some DMA data transfer, with more or less packets loss.
512*4882a593Smuzhiyun **      It depends on the phase and frequency of VSYNC and
513*4882a593Smuzhiyun **      the way of 7146 is instructed to trigger on port B (defined
514*4882a593Smuzhiyun **      in DD1_INIT register, 3rd nibble from the right valid
515*4882a593Smuzhiyun **      numbers are 0-7, see datasheet)
516*4882a593Smuzhiyun **
517*4882a593Smuzhiyun **      The correct triggering can minimize packet loss,
518*4882a593Smuzhiyun **      dvbtraffic should give this stable bandwidths:
519*4882a593Smuzhiyun **        22k transponder = 33814 kbit/s
520*4882a593Smuzhiyun **      27.5k transponder = 38045 kbit/s
521*4882a593Smuzhiyun **      by experiment it is found that the best results
522*4882a593Smuzhiyun **      (stable bandwidths and almost no packet loss)
523*4882a593Smuzhiyun **      are obtained using DD1_INIT triggering number 2
524*4882a593Smuzhiyun **      (Va at rising edge of VS Fa = HS x VS-failing forced toggle)
525*4882a593Smuzhiyun **      and a VSYNC phase that occurs in the middle of DMA transfer
526*4882a593Smuzhiyun **      (about byte 188*512=96256 in the DMA window).
527*4882a593Smuzhiyun **
528*4882a593Smuzhiyun **      Phase of HS is still not clear to me how to control,
529*4882a593Smuzhiyun **      It just happens to be so. It can be seen if one enables
530*4882a593Smuzhiyun **      RPS_IRQ and print Event Counter 1 in vpeirq(). Every
531*4882a593Smuzhiyun **      time RPS_INTERRUPT is called, the Event Counter 1 will
532*4882a593Smuzhiyun **      increment. That's how the 7146 is programmed to do event
533*4882a593Smuzhiyun **      counting in this budget-patch.c
534*4882a593Smuzhiyun **      I *think* HPS setting has something to do with the phase
535*4882a593Smuzhiyun **      of HS but I can't be 100% sure in that.
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun **      hardware debug note: a working budget card (including budget patch)
538*4882a593Smuzhiyun **      with vpeirq() interrupt setup in mode "0x90" (every 64K) will
539*4882a593Smuzhiyun **      generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
540*4882a593Smuzhiyun **      and that means 3*25=75 Hz of interrupt frequency, as seen by
541*4882a593Smuzhiyun **      watch cat /proc/interrupts
542*4882a593Smuzhiyun **
543*4882a593Smuzhiyun **      If this frequency is 3x lower (and data received in the DMA
544*4882a593Smuzhiyun **      buffer don't start with 0x47, but in the middle of packets,
545*4882a593Smuzhiyun **      whose lengths appear to be like 188 292 188 104 etc.
546*4882a593Smuzhiyun **      this means VSYNC line is not connected in the hardware.
547*4882a593Smuzhiyun **      (check soldering pcb and pins)
548*4882a593Smuzhiyun **      The same behaviour of missing VSYNC can be duplicated on budget
549*4882a593Smuzhiyun **      cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
550*4882a593Smuzhiyun */
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	// Setup RPS1 "program" (p35)
553*4882a593Smuzhiyun 	count = 0;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	// Wait Source Line Counter Threshold                           (p36)
557*4882a593Smuzhiyun 	WRITE_RPS1(CMD_PAUSE | EVT_HS);
558*4882a593Smuzhiyun 	// Set GPIO3=1                                                  (p42)
559*4882a593Smuzhiyun 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
560*4882a593Smuzhiyun 	WRITE_RPS1(GPIO3_MSK);
561*4882a593Smuzhiyun 	WRITE_RPS1(SAA7146_GPIO_OUTHI<<24);
562*4882a593Smuzhiyun #if RPS_IRQ
563*4882a593Smuzhiyun 	// issue RPS1 interrupt
564*4882a593Smuzhiyun 	WRITE_RPS1(CMD_INTERRUPT);
565*4882a593Smuzhiyun #endif
566*4882a593Smuzhiyun 	// Wait reset Source Line Counter Threshold                     (p36)
567*4882a593Smuzhiyun 	WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS);
568*4882a593Smuzhiyun 	// Set GPIO3=0                                                  (p42)
569*4882a593Smuzhiyun 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
570*4882a593Smuzhiyun 	WRITE_RPS1(GPIO3_MSK);
571*4882a593Smuzhiyun 	WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
572*4882a593Smuzhiyun #if RPS_IRQ
573*4882a593Smuzhiyun 	// issue RPS1 interrupt
574*4882a593Smuzhiyun 	WRITE_RPS1(CMD_INTERRUPT);
575*4882a593Smuzhiyun #endif
576*4882a593Smuzhiyun 	// Jump to begin of RPS program                                 (p37)
577*4882a593Smuzhiyun 	WRITE_RPS1(CMD_JUMP);
578*4882a593Smuzhiyun 	WRITE_RPS1(dev->d_rps1.dma_handle);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	// Fix VSYNC level
581*4882a593Smuzhiyun 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
582*4882a593Smuzhiyun 	// Set RPS1 Address register to point to RPS code               (r108 p42)
583*4882a593Smuzhiyun 	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	if (!(budget = kmalloc (sizeof(struct budget_patch), GFP_KERNEL)))
586*4882a593Smuzhiyun 		return -ENOMEM;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	dprintk(2, "budget: %p\n", budget);
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	err = ttpci_budget_init(budget, dev, info, THIS_MODULE, adapter_nr);
591*4882a593Smuzhiyun 	if (err) {
592*4882a593Smuzhiyun 		kfree(budget);
593*4882a593Smuzhiyun 		return err;
594*4882a593Smuzhiyun 	}
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	// Set Source Line Counter Threshold, using BRS                 (rCC p43)
597*4882a593Smuzhiyun 	// It generates HS event every TS_HEIGHT lines
598*4882a593Smuzhiyun 	// this is related to TS_WIDTH set in register
599*4882a593Smuzhiyun 	// NUM_LINE_BYTE3 in budget-core.c. If NUM_LINE_BYTE
600*4882a593Smuzhiyun 	// low 16 bits are set to TS_WIDTH bytes (TS_WIDTH=2*188
601*4882a593Smuzhiyun 	//,then RPS_THRESH1
602*4882a593Smuzhiyun 	// should be set to trigger every TS_HEIGHT (512) lines.
603*4882a593Smuzhiyun 	//
604*4882a593Smuzhiyun 	saa7146_write(dev, RPS_THRESH1, budget->buffer_height | MASK_12 );
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	// saa7146_write(dev, RPS_THRESH0, ((TS_HEIGHT/2)<<16) |MASK_28| (TS_HEIGHT/2) |MASK_12 );
607*4882a593Smuzhiyun 	// Enable RPS1                                                  (rFC p33)
608*4882a593Smuzhiyun 	saa7146_write(dev, MC1, (MASK_13 | MASK_29));
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	dev->ext_priv = budget;
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	budget->dvb_adapter.priv = budget;
614*4882a593Smuzhiyun 	frontend_init(budget);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	ttpci_budget_init_hooks(budget);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	return 0;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
budget_patch_detach(struct saa7146_dev * dev)621*4882a593Smuzhiyun static int budget_patch_detach (struct saa7146_dev* dev)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun 	struct budget_patch *budget = (struct budget_patch*) dev->ext_priv;
624*4882a593Smuzhiyun 	int err;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	if (budget->dvb_frontend) {
627*4882a593Smuzhiyun 		dvb_unregister_frontend(budget->dvb_frontend);
628*4882a593Smuzhiyun 		dvb_frontend_detach(budget->dvb_frontend);
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun 	err = ttpci_budget_deinit (budget);
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	kfree (budget);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	return err;
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun 
budget_patch_init(void)637*4882a593Smuzhiyun static int __init budget_patch_init(void)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun 	return saa7146_register_extension(&budget_extension);
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun 
budget_patch_exit(void)642*4882a593Smuzhiyun static void __exit budget_patch_exit(void)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun 	saa7146_unregister_extension(&budget_extension);
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun static struct saa7146_extension budget_extension = {
648*4882a593Smuzhiyun 	.name           = "budget_patch dvb",
649*4882a593Smuzhiyun 	.flags          = 0,
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	.module         = THIS_MODULE,
652*4882a593Smuzhiyun 	.pci_tbl        = pci_tbl,
653*4882a593Smuzhiyun 	.attach         = budget_patch_attach,
654*4882a593Smuzhiyun 	.detach         = budget_patch_detach,
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	.irq_mask       = MASK_10,
657*4882a593Smuzhiyun 	.irq_func       = ttpci_budget_irq10_handler,
658*4882a593Smuzhiyun };
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun module_init(budget_patch_init);
661*4882a593Smuzhiyun module_exit(budget_patch_exit);
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun MODULE_LICENSE("GPL");
664*4882a593Smuzhiyun MODULE_AUTHOR("Emard, Roberto Deza, Holger Waechtler, Michael Hunold, others");
665*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for full TS modified DVB-S SAA7146+AV7110 based so-called Budget Patch cards");
666