1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Original author: 6*4882a593Smuzhiyun * Ben Collins <bcollins@ubuntu.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Additional work by: 9*4882a593Smuzhiyun * John Brooks <john.brooks@bluecherry.net> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __SOLO6X10_REGISTERS_H 13*4882a593Smuzhiyun #define __SOLO6X10_REGISTERS_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/bitops.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "solo6x10-offsets.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Global 6010 system configuration */ 20*4882a593Smuzhiyun #define SOLO_SYS_CFG 0x0000 21*4882a593Smuzhiyun #define SOLO_SYS_CFG_FOUT_EN 0x00000001 22*4882a593Smuzhiyun #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002 23*4882a593Smuzhiyun #define SOLO_SYS_CFG_PLL_PWDN 0x00000004 24*4882a593Smuzhiyun #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3) 25*4882a593Smuzhiyun #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5) 26*4882a593Smuzhiyun #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14) 27*4882a593Smuzhiyun #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000 28*4882a593Smuzhiyun #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24) 29*4882a593Smuzhiyun #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26) 30*4882a593Smuzhiyun #define SOLO_SYS_CFG_SDRAM64BIT 0x40000000 31*4882a593Smuzhiyun #define SOLO_SYS_CFG_RESET 0x80000000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SOLO_DMA_CTRL 0x0004 34*4882a593Smuzhiyun #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) 35*4882a593Smuzhiyun /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ 36*4882a593Smuzhiyun #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) 37*4882a593Smuzhiyun #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT BIT(5) 38*4882a593Smuzhiyun #define SOLO_DMA_CTRL_STROBE_SELECT BIT(4) 39*4882a593Smuzhiyun #define SOLO_DMA_CTRL_READ_DATA_SELECT BIT(3) 40*4882a593Smuzhiyun #define SOLO_DMA_CTRL_READ_CLK_SELECT BIT(2) 41*4882a593Smuzhiyun #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Some things we set in this are undocumented. Why Softlogic?!?! */ 44*4882a593Smuzhiyun #define SOLO_DMA_CTRL1 0x0008 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define SOLO_SYS_VCLK 0x000C 47*4882a593Smuzhiyun #define SOLO_VCLK_INVERT BIT(22) 48*4882a593Smuzhiyun /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ 49*4882a593Smuzhiyun #define SOLO_VCLK_SELECT(n) ((n)<<20) 50*4882a593Smuzhiyun #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) 51*4882a593Smuzhiyun #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) 52*4882a593Smuzhiyun #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) 53*4882a593Smuzhiyun #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) 54*4882a593Smuzhiyun #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) 55*4882a593Smuzhiyun #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) 56*4882a593Smuzhiyun #define SOLO_VCLK_VIN0203_DELAY(n) ((n)<<2) 57*4882a593Smuzhiyun #define SOLO_VCLK_VIN0001_DELAY(n) ((n)<<0) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define SOLO_IRQ_STAT 0x0010 60*4882a593Smuzhiyun #define SOLO_IRQ_MASK 0x0014 61*4882a593Smuzhiyun #define SOLO_IRQ_P2M(n) BIT((n) + 17) 62*4882a593Smuzhiyun #define SOLO_IRQ_GPIO BIT(16) 63*4882a593Smuzhiyun #define SOLO_IRQ_VIDEO_LOSS BIT(15) 64*4882a593Smuzhiyun #define SOLO_IRQ_VIDEO_IN BIT(14) 65*4882a593Smuzhiyun #define SOLO_IRQ_MOTION BIT(13) 66*4882a593Smuzhiyun #define SOLO_IRQ_ATA_CMD BIT(12) 67*4882a593Smuzhiyun #define SOLO_IRQ_ATA_DIR BIT(11) 68*4882a593Smuzhiyun #define SOLO_IRQ_PCI_ERR BIT(10) 69*4882a593Smuzhiyun #define SOLO_IRQ_PS2_1 BIT(9) 70*4882a593Smuzhiyun #define SOLO_IRQ_PS2_0 BIT(8) 71*4882a593Smuzhiyun #define SOLO_IRQ_SPI BIT(7) 72*4882a593Smuzhiyun #define SOLO_IRQ_IIC BIT(6) 73*4882a593Smuzhiyun #define SOLO_IRQ_UART(n) BIT((n) + 4) 74*4882a593Smuzhiyun #define SOLO_IRQ_G723 BIT(3) 75*4882a593Smuzhiyun #define SOLO_IRQ_DECODER BIT(1) 76*4882a593Smuzhiyun #define SOLO_IRQ_ENCODER BIT(0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define SOLO_CHIP_OPTION 0x001C 79*4882a593Smuzhiyun #define SOLO_CHIP_ID_MASK 0x00000007 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define SOLO_EEPROM_CTRL 0x0060 84*4882a593Smuzhiyun #define SOLO_EEPROM_ACCESS_EN BIT(7) 85*4882a593Smuzhiyun #define SOLO_EEPROM_CS BIT(3) 86*4882a593Smuzhiyun #define SOLO_EEPROM_CLK BIT(2) 87*4882a593Smuzhiyun #define SOLO_EEPROM_DO BIT(1) 88*4882a593Smuzhiyun #define SOLO_EEPROM_DI BIT(0) 89*4882a593Smuzhiyun #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define SOLO_PCI_ERR 0x0070 92*4882a593Smuzhiyun #define SOLO_PCI_ERR_FATAL 0x00000001 93*4882a593Smuzhiyun #define SOLO_PCI_ERR_PARITY 0x00000002 94*4882a593Smuzhiyun #define SOLO_PCI_ERR_TARGET 0x00000004 95*4882a593Smuzhiyun #define SOLO_PCI_ERR_TIMEOUT 0x00000008 96*4882a593Smuzhiyun #define SOLO_PCI_ERR_P2M 0x00000010 97*4882a593Smuzhiyun #define SOLO_PCI_ERR_ATA 0x00000020 98*4882a593Smuzhiyun #define SOLO_PCI_ERR_P2M_DESC 0x00000040 99*4882a593Smuzhiyun #define SOLO_PCI_ERR_FSM0(__s) (((__s) >> 16) & 0x0f) 100*4882a593Smuzhiyun #define SOLO_PCI_ERR_FSM1(__s) (((__s) >> 20) & 0x0f) 101*4882a593Smuzhiyun #define SOLO_PCI_ERR_FSM2(__s) (((__s) >> 24) & 0x1f) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define SOLO_P2M_BASE 0x0080 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) 106*4882a593Smuzhiyun #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ 107*4882a593Smuzhiyun #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */ 108*4882a593Smuzhiyun /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ 109*4882a593Smuzhiyun #define SOLO_P2M_CSC_16BIT_565 BIT(4) 110*4882a593Smuzhiyun #define SOLO_P2M_UV_SWAP BIT(3) 111*4882a593Smuzhiyun #define SOLO_P2M_PCI_MASTER_MODE BIT(2) 112*4882a593Smuzhiyun #define SOLO_P2M_DESC_INTR_OPT BIT(1) /* 1:Empty, 0:Each */ 113*4882a593Smuzhiyun #define SOLO_P2M_DESC_MODE BIT(0) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define SOLO_P2M_DESC_ID(n) (0x0088 + ((n)*0x20)) 118*4882a593Smuzhiyun #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) 121*4882a593Smuzhiyun #define SOLO_P2M_COMMAND_DONE BIT(8) 122*4882a593Smuzhiyun #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) 125*4882a593Smuzhiyun #define SOLO_P2M_PCI_INC(n) ((n)<<20) 126*4882a593Smuzhiyun #define SOLO_P2M_REPEAT(n) ((n)<<10) 127*4882a593Smuzhiyun /* 0:512, 1:256, 2:128, 3:64, 4:32, 5:128(2page) */ 128*4882a593Smuzhiyun #define SOLO_P2M_BURST_SIZE(n) ((n)<<7) 129*4882a593Smuzhiyun #define SOLO_P2M_BURST_512 0 130*4882a593Smuzhiyun #define SOLO_P2M_BURST_256 1 131*4882a593Smuzhiyun #define SOLO_P2M_BURST_128 2 132*4882a593Smuzhiyun #define SOLO_P2M_BURST_64 3 133*4882a593Smuzhiyun #define SOLO_P2M_BURST_32 4 134*4882a593Smuzhiyun #define SOLO_P2M_CSC_16BIT BIT(6) /* 0:24bit, 1:16bit */ 135*4882a593Smuzhiyun /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ 136*4882a593Smuzhiyun #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) 137*4882a593Smuzhiyun #define SOLO_P2M_CSC_ON BIT(3) 138*4882a593Smuzhiyun #define SOLO_P2M_INTERRUPT_REQ BIT(2) 139*4882a593Smuzhiyun #define SOLO_P2M_WRITE BIT(1) 140*4882a593Smuzhiyun #define SOLO_P2M_TRANS_ON BIT(0) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) 143*4882a593Smuzhiyun #define SOLO_P2M_EXT_INC(n) ((n)<<20) 144*4882a593Smuzhiyun #define SOLO_P2M_COPY_SIZE(n) ((n)<<0) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define SOLO_P2M_TAR_ADR(n) (0x0098 + ((n)*0x20)) 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define SOLO_P2M_EXT_ADR(n) (0x009C + ((n)*0x20)) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define SOLO_P2M_BUFFER(i) (0x2000 + ((i)*4)) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define SOLO_VI_CH_SWITCH_0 0x0100 153*4882a593Smuzhiyun #define SOLO_VI_CH_SWITCH_1 0x0104 154*4882a593Smuzhiyun #define SOLO_VI_CH_SWITCH_2 0x0108 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define SOLO_VI_CH_ENA 0x010C 157*4882a593Smuzhiyun #define SOLO_VI_CH_FORMAT 0x0110 158*4882a593Smuzhiyun #define SOLO_VI_FD_SEL_MASK(n) ((n)<<16) 159*4882a593Smuzhiyun #define SOLO_VI_PROG_MASK(n) ((n)<<0) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define SOLO_VI_FMT_CFG 0x0114 162*4882a593Smuzhiyun #define SOLO_VI_FMT_CHECK_VCOUNT BIT(31) 163*4882a593Smuzhiyun #define SOLO_VI_FMT_CHECK_HCOUNT BIT(30) 164*4882a593Smuzhiyun #define SOLO_VI_FMT_TEST_SIGNAL BIT(28) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define SOLO_VI_PAGE_SW 0x0118 167*4882a593Smuzhiyun #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) 168*4882a593Smuzhiyun #define SOLO_FI_INV_DISP_OUT(n) ((n)<<7) 169*4882a593Smuzhiyun #define SOLO_DISP_SYNC_FI(n) ((n)<<6) 170*4882a593Smuzhiyun #define SOLO_PIP_PAGE_ADD(n) ((n)<<3) 171*4882a593Smuzhiyun #define SOLO_NORMAL_PAGE_ADD(n) ((n)<<0) 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define SOLO_VI_ACT_I_P 0x011C 174*4882a593Smuzhiyun #define SOLO_VI_ACT_I_S 0x0120 175*4882a593Smuzhiyun #define SOLO_VI_ACT_P 0x0124 176*4882a593Smuzhiyun #define SOLO_VI_FI_INVERT BIT(31) 177*4882a593Smuzhiyun #define SOLO_VI_H_START(n) ((n)<<21) 178*4882a593Smuzhiyun #define SOLO_VI_V_START(n) ((n)<<11) 179*4882a593Smuzhiyun #define SOLO_VI_V_STOP(n) ((n)<<0) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define SOLO_VI_STATUS0 0x0128 182*4882a593Smuzhiyun #define SOLO_VI_STATUS0_PAGE(__n) ((__n) & 0x07) 183*4882a593Smuzhiyun #define SOLO_VI_STATUS1 0x012C 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* XXX: Might be better off in kernel level disp.h */ 186*4882a593Smuzhiyun #define DISP_PAGE(stat) ((stat) & 0x07) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define SOLO_VI_PB_CONFIG 0x0130 189*4882a593Smuzhiyun #define SOLO_VI_PB_USER_MODE BIT(1) 190*4882a593Smuzhiyun #define SOLO_VI_PB_PAL BIT(0) 191*4882a593Smuzhiyun #define SOLO_VI_PB_RANGE_HV 0x0134 192*4882a593Smuzhiyun #define SOLO_VI_PB_HSIZE(h) ((h)<<12) 193*4882a593Smuzhiyun #define SOLO_VI_PB_VSIZE(v) ((v)<<0) 194*4882a593Smuzhiyun #define SOLO_VI_PB_ACT_H 0x0138 195*4882a593Smuzhiyun #define SOLO_VI_PB_HSTART(n) ((n)<<12) 196*4882a593Smuzhiyun #define SOLO_VI_PB_HSTOP(n) ((n)<<0) 197*4882a593Smuzhiyun #define SOLO_VI_PB_ACT_V 0x013C 198*4882a593Smuzhiyun #define SOLO_VI_PB_VSTART(n) ((n)<<12) 199*4882a593Smuzhiyun #define SOLO_VI_PB_VSTOP(n) ((n)<<0) 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define SOLO_VI_MOSAIC(ch) (0x0140 + ((ch)*4)) 202*4882a593Smuzhiyun #define SOLO_VI_MOSAIC_SX(x) ((x)<<24) 203*4882a593Smuzhiyun #define SOLO_VI_MOSAIC_EX(x) ((x)<<16) 204*4882a593Smuzhiyun #define SOLO_VI_MOSAIC_SY(x) ((x)<<8) 205*4882a593Smuzhiyun #define SOLO_VI_MOSAIC_EY(x) ((x)<<0) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define SOLO_VI_WIN_CTRL0(ch) (0x0180 + ((ch)*4)) 208*4882a593Smuzhiyun #define SOLO_VI_WIN_CTRL1(ch) (0x01C0 + ((ch)*4)) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define SOLO_VI_WIN_CHANNEL(n) ((n)<<28) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define SOLO_VI_WIN_PIP(n) ((n)<<27) 213*4882a593Smuzhiyun #define SOLO_VI_WIN_SCALE(n) ((n)<<24) 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define SOLO_VI_WIN_SX(x) ((x)<<12) 216*4882a593Smuzhiyun #define SOLO_VI_WIN_EX(x) ((x)<<0) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define SOLO_VI_WIN_SY(x) ((x)<<12) 219*4882a593Smuzhiyun #define SOLO_VI_WIN_EY(x) ((x)<<0) 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define SOLO_VI_WIN_ON(ch) (0x0200 + ((ch)*4)) 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #define SOLO_VI_WIN_SW 0x0240 224*4882a593Smuzhiyun #define SOLO_VI_WIN_LIVE_AUTO_MUTE 0x0244 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define SOLO_VI_MOT_ADR 0x0260 227*4882a593Smuzhiyun #define SOLO_VI_MOTION_EN(mask) ((mask)<<16) 228*4882a593Smuzhiyun #define SOLO_VI_MOT_CTRL 0x0264 229*4882a593Smuzhiyun #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) 230*4882a593Smuzhiyun #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) 231*4882a593Smuzhiyun #define SOLO_VI_MOTION_INTR_START_STOP BIT(15) 232*4882a593Smuzhiyun #define SOLO_VI_MOTION_FREEZE_DATA BIT(14) 233*4882a593Smuzhiyun #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) 234*4882a593Smuzhiyun #define SOLO_VI_MOT_CLEAR 0x0268 235*4882a593Smuzhiyun #define SOLO_VI_MOT_STATUS 0x026C 236*4882a593Smuzhiyun #define SOLO_VI_MOTION_CNT(n) ((n)<<0) 237*4882a593Smuzhiyun #define SOLO_VI_MOTION_BORDER 0x0270 238*4882a593Smuzhiyun #define SOLO_VI_MOTION_BAR 0x0274 239*4882a593Smuzhiyun #define SOLO_VI_MOTION_Y_SET BIT(29) 240*4882a593Smuzhiyun #define SOLO_VI_MOTION_Y_ADD BIT(28) 241*4882a593Smuzhiyun #define SOLO_VI_MOTION_CB_SET BIT(27) 242*4882a593Smuzhiyun #define SOLO_VI_MOTION_CB_ADD BIT(26) 243*4882a593Smuzhiyun #define SOLO_VI_MOTION_CR_SET BIT(25) 244*4882a593Smuzhiyun #define SOLO_VI_MOTION_CR_ADD BIT(24) 245*4882a593Smuzhiyun #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) 246*4882a593Smuzhiyun #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) 247*4882a593Smuzhiyun #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define SOLO_VO_FMT_ENC 0x0300 250*4882a593Smuzhiyun #define SOLO_VO_SCAN_MODE_PROGRESSIVE BIT(31) 251*4882a593Smuzhiyun #define SOLO_VO_FMT_TYPE_PAL BIT(30) 252*4882a593Smuzhiyun #define SOLO_VO_FMT_TYPE_NTSC 0 253*4882a593Smuzhiyun #define SOLO_VO_USER_SET BIT(29) 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define SOLO_VO_FI_CHANGE BIT(20) 256*4882a593Smuzhiyun #define SOLO_VO_USER_COLOR_SET_VSYNC BIT(19) 257*4882a593Smuzhiyun #define SOLO_VO_USER_COLOR_SET_HSYNC BIT(18) 258*4882a593Smuzhiyun #define SOLO_VO_USER_COLOR_SET_NAH BIT(17) 259*4882a593Smuzhiyun #define SOLO_VO_USER_COLOR_SET_NAV BIT(16) 260*4882a593Smuzhiyun #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) 261*4882a593Smuzhiyun #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) 262*4882a593Smuzhiyun #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define SOLO_VO_ACT_H 0x0304 265*4882a593Smuzhiyun #define SOLO_VO_H_BLANK(n) ((n)<<22) 266*4882a593Smuzhiyun #define SOLO_VO_H_START(n) ((n)<<11) 267*4882a593Smuzhiyun #define SOLO_VO_H_STOP(n) ((n)<<0) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #define SOLO_VO_ACT_V 0x0308 270*4882a593Smuzhiyun #define SOLO_VO_V_BLANK(n) ((n)<<22) 271*4882a593Smuzhiyun #define SOLO_VO_V_START(n) ((n)<<11) 272*4882a593Smuzhiyun #define SOLO_VO_V_STOP(n) ((n)<<0) 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define SOLO_VO_RANGE_HV 0x030C 275*4882a593Smuzhiyun #define SOLO_VO_SYNC_INVERT BIT(24) 276*4882a593Smuzhiyun #define SOLO_VO_HSYNC_INVERT BIT(23) 277*4882a593Smuzhiyun #define SOLO_VO_VSYNC_INVERT BIT(22) 278*4882a593Smuzhiyun #define SOLO_VO_H_LEN(n) ((n)<<11) 279*4882a593Smuzhiyun #define SOLO_VO_V_LEN(n) ((n)<<0) 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define SOLO_VO_DISP_CTRL 0x0310 282*4882a593Smuzhiyun #define SOLO_VO_DISP_ON BIT(31) 283*4882a593Smuzhiyun #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) 284*4882a593Smuzhiyun #define SOLO_VO_DISP_DOUBLE_SCAN BIT(22) 285*4882a593Smuzhiyun #define SOLO_VO_DISP_SINGLE_PAGE BIT(21) 286*4882a593Smuzhiyun #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define SOLO_VO_DISP_ERASE 0x0314 289*4882a593Smuzhiyun #define SOLO_VO_DISP_ERASE_ON BIT(0) 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define SOLO_VO_ZOOM_CTRL 0x0318 292*4882a593Smuzhiyun #define SOLO_VO_ZOOM_VER_ON BIT(24) 293*4882a593Smuzhiyun #define SOLO_VO_ZOOM_HOR_ON BIT(23) 294*4882a593Smuzhiyun #define SOLO_VO_ZOOM_V_COMP BIT(22) 295*4882a593Smuzhiyun #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) 296*4882a593Smuzhiyun #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun #define SOLO_VO_FREEZE_CTRL 0x031C 299*4882a593Smuzhiyun #define SOLO_VO_FREEZE_ON BIT(1) 300*4882a593Smuzhiyun #define SOLO_VO_FREEZE_INTERPOLATION BIT(0) 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define SOLO_VO_BKG_COLOR 0x0320 303*4882a593Smuzhiyun #define SOLO_BG_Y(y) ((y)<<16) 304*4882a593Smuzhiyun #define SOLO_BG_U(u) ((u)<<8) 305*4882a593Smuzhiyun #define SOLO_BG_V(v) ((v)<<0) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #define SOLO_VO_DEINTERLACE 0x0324 308*4882a593Smuzhiyun #define SOLO_VO_DEINTERLACE_THRESHOLD(n) ((n)<<8) 309*4882a593Smuzhiyun #define SOLO_VO_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun #define SOLO_VO_BORDER_LINE_COLOR 0x0330 312*4882a593Smuzhiyun #define SOLO_VO_BORDER_FILL_COLOR 0x0334 313*4882a593Smuzhiyun #define SOLO_VO_BORDER_LINE_MASK 0x0338 314*4882a593Smuzhiyun #define SOLO_VO_BORDER_FILL_MASK 0x033c 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun #define SOLO_VO_BORDER_X(n) (0x0340+((n)*4)) 317*4882a593Smuzhiyun #define SOLO_VO_BORDER_Y(n) (0x0354+((n)*4)) 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_SET 0x0368 320*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_START 0x036c 321*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_STOP 0x0370 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_SET2 0x0374 324*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_START2 0x0378 325*4882a593Smuzhiyun #define SOLO_VO_CELL_EXT_STOP2 0x037c 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #define SOLO_VO_RECTANGLE_CTRL(n) (0x0368+((n)*12)) 328*4882a593Smuzhiyun #define SOLO_VO_RECTANGLE_START(n) (0x036c+((n)*12)) 329*4882a593Smuzhiyun #define SOLO_VO_RECTANGLE_STOP(n) (0x0370+((n)*12)) 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun #define SOLO_VO_CURSOR_POS (0x0380) 332*4882a593Smuzhiyun #define SOLO_VO_CURSOR_CLR (0x0384) 333*4882a593Smuzhiyun #define SOLO_VO_CURSOR_CLR2 (0x0388) 334*4882a593Smuzhiyun #define SOLO_VO_CURSOR_MASK(id) (0x0390+((id)*4)) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun #define SOLO_OSG_CONFIG 0x03E0 339*4882a593Smuzhiyun #define SOLO_VO_OSG_ON BIT(31) 340*4882a593Smuzhiyun #define SOLO_VO_OSG_COLOR_MUTE BIT(28) 341*4882a593Smuzhiyun #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) 342*4882a593Smuzhiyun #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) 343*4882a593Smuzhiyun #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #define SOLO_OSG_ERASE 0x03E4 346*4882a593Smuzhiyun #define SOLO_OSG_ERASE_ON (0x80) 347*4882a593Smuzhiyun #define SOLO_OSG_ERASE_OFF (0x00) 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #define SOLO_VO_OSG_BLINK 0x03E8 350*4882a593Smuzhiyun #define SOLO_VO_OSG_BLINK_ON BIT(1) 351*4882a593Smuzhiyun #define SOLO_VO_OSG_BLINK_INTREVAL18 BIT(0) 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define SOLO_CAP_BASE 0x0400 354*4882a593Smuzhiyun #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) 355*4882a593Smuzhiyun #define SOLO_CAP_BASE_ADDR(n) ((n)<<0) 356*4882a593Smuzhiyun #define SOLO_CAP_BTW 0x0404 357*4882a593Smuzhiyun #define SOLO_CAP_PROG_BANDWIDTH(n) ((n)<<8) 358*4882a593Smuzhiyun #define SOLO_CAP_MAX_BANDWIDTH(n) ((n)<<0) 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun #define SOLO_DIM_SCALE1 0x0408 361*4882a593Smuzhiyun #define SOLO_DIM_SCALE2 0x040C 362*4882a593Smuzhiyun #define SOLO_DIM_SCALE3 0x0410 363*4882a593Smuzhiyun #define SOLO_DIM_SCALE4 0x0414 364*4882a593Smuzhiyun #define SOLO_DIM_SCALE5 0x0418 365*4882a593Smuzhiyun #define SOLO_DIM_V_MB_NUM_FRAME(n) ((n)<<16) 366*4882a593Smuzhiyun #define SOLO_DIM_V_MB_NUM_FIELD(n) ((n)<<8) 367*4882a593Smuzhiyun #define SOLO_DIM_H_MB_NUM(n) ((n)<<0) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define SOLO_DIM_PROG 0x041C 370*4882a593Smuzhiyun #define SOLO_CAP_STATUS 0x0420 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #define SOLO_CAP_CH_SCALE(ch) (0x0440+((ch)*4)) 373*4882a593Smuzhiyun #define SOLO_CAP_CH_COMP_ENA_E(ch) (0x0480+((ch)*4)) 374*4882a593Smuzhiyun #define SOLO_CAP_CH_INTV(ch) (0x04C0+((ch)*4)) 375*4882a593Smuzhiyun #define SOLO_CAP_CH_INTV_E(ch) (0x0500+((ch)*4)) 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define SOLO_VE_CFG0 0x0610 379*4882a593Smuzhiyun #define SOLO_VE_TWO_PAGE_MODE BIT(31) 380*4882a593Smuzhiyun #define SOLO_VE_INTR_CTRL(n) ((n)<<24) 381*4882a593Smuzhiyun #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) 382*4882a593Smuzhiyun #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #define SOLO_VE_CFG1 0x0614 385*4882a593Smuzhiyun #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) 386*4882a593Smuzhiyun #define SOLO_VE_INSERT_INDEX BIT(18) 387*4882a593Smuzhiyun #define SOLO_VE_MOTION_MODE(n) ((n)<<16) 388*4882a593Smuzhiyun #define SOLO_VE_MOTION_BASE(n) ((n)<<0) 389*4882a593Smuzhiyun #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ 390*4882a593Smuzhiyun #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ 391*4882a593Smuzhiyun #define SOLO_VE_INSERT_INDEX_JPEG BIT(19) /* 6110 Only */ 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #define SOLO_VE_WMRK_POLY 0x061C 394*4882a593Smuzhiyun #define SOLO_VE_VMRK_INIT_KEY 0x0620 395*4882a593Smuzhiyun #define SOLO_VE_WMRK_STRL 0x0624 396*4882a593Smuzhiyun #define SOLO_VE_ENCRYP_POLY 0x0628 397*4882a593Smuzhiyun #define SOLO_VE_ENCRYP_INIT 0x062C 398*4882a593Smuzhiyun #define SOLO_VE_ATTR 0x0630 399*4882a593Smuzhiyun #define SOLO_VE_LITTLE_ENDIAN BIT(31) 400*4882a593Smuzhiyun #define SOLO_COMP_ATTR_RN BIT(30) 401*4882a593Smuzhiyun #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) 402*4882a593Smuzhiyun #define SOLO_COMP_TIME_INC(n) ((n)<<25) 403*4882a593Smuzhiyun #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) 404*4882a593Smuzhiyun #define SOLO_DCT_INTERVAL(n) ((n)<<16) 405*4882a593Smuzhiyun #define SOLO_VE_COMPT_MOT 0x0634 /* 6110 Only */ 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun #define SOLO_VE_STATE(n) (0x0640+((n)*4)) 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #define SOLO_VE_JPEG_QP_TBL 0x0670 410*4882a593Smuzhiyun #define SOLO_VE_JPEG_QP_CH_L 0x0674 411*4882a593Smuzhiyun #define SOLO_VE_JPEG_QP_CH_H 0x0678 412*4882a593Smuzhiyun #define SOLO_VE_JPEG_CFG 0x067C 413*4882a593Smuzhiyun #define SOLO_VE_JPEG_CTRL 0x0680 414*4882a593Smuzhiyun #define SOLO_VE_CODE_ENCRYPT 0x0684 /* 6110 Only */ 415*4882a593Smuzhiyun #define SOLO_VE_JPEG_CFG1 0x0688 /* 6110 Only */ 416*4882a593Smuzhiyun #define SOLO_VE_WMRK_ENABLE 0x068C /* 6110 Only */ 417*4882a593Smuzhiyun #define SOLO_VE_OSD_CH 0x0690 418*4882a593Smuzhiyun #define SOLO_VE_OSD_BASE 0x0694 419*4882a593Smuzhiyun #define SOLO_VE_OSD_CLR 0x0698 420*4882a593Smuzhiyun #define SOLO_VE_OSD_OPT 0x069C 421*4882a593Smuzhiyun #define SOLO_VE_OSD_V_DOUBLE BIT(16) /* 6110 Only */ 422*4882a593Smuzhiyun #define SOLO_VE_OSD_H_SHADOW BIT(15) 423*4882a593Smuzhiyun #define SOLO_VE_OSD_V_SHADOW BIT(14) 424*4882a593Smuzhiyun #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) 425*4882a593Smuzhiyun #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #define SOLO_VE_CH_INTL(ch) (0x0700+((ch)*4)) 428*4882a593Smuzhiyun #define SOLO_VE_CH_MOT(ch) (0x0740+((ch)*4)) 429*4882a593Smuzhiyun #define SOLO_VE_CH_QP(ch) (0x0780+((ch)*4)) 430*4882a593Smuzhiyun #define SOLO_VE_CH_QP_E(ch) (0x07C0+((ch)*4)) 431*4882a593Smuzhiyun #define SOLO_VE_CH_GOP(ch) (0x0800+((ch)*4)) 432*4882a593Smuzhiyun #define SOLO_VE_CH_GOP_E(ch) (0x0840+((ch)*4)) 433*4882a593Smuzhiyun #define SOLO_VE_CH_REF_BASE(ch) (0x0880+((ch)*4)) 434*4882a593Smuzhiyun #define SOLO_VE_CH_REF_BASE_E(ch) (0x08C0+((ch)*4)) 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun #define SOLO_VE_MPEG4_QUE(n) (0x0A00+((n)*8)) 437*4882a593Smuzhiyun #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun #define SOLO_VD_CFG0 0x0900 440*4882a593Smuzhiyun #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW BIT(24) 441*4882a593Smuzhiyun #define SOLO_VD_CFG_BUSY_WIAT_CODE BIT(23) 442*4882a593Smuzhiyun #define SOLO_VD_CFG_BUSY_WIAT_REF BIT(22) 443*4882a593Smuzhiyun #define SOLO_VD_CFG_BUSY_WIAT_RES BIT(21) 444*4882a593Smuzhiyun #define SOLO_VD_CFG_BUSY_WIAT_MS BIT(20) 445*4882a593Smuzhiyun #define SOLO_VD_CFG_SINGLE_MODE BIT(18) 446*4882a593Smuzhiyun #define SOLO_VD_CFG_SCAL_MANUAL BIT(17) 447*4882a593Smuzhiyun #define SOLO_VD_CFG_USER_PAGE_CTRL BIT(16) 448*4882a593Smuzhiyun #define SOLO_VD_CFG_LITTLE_ENDIAN BIT(15) 449*4882a593Smuzhiyun #define SOLO_VD_CFG_START_FI BIT(14) 450*4882a593Smuzhiyun #define SOLO_VD_CFG_ERR_LOCK BIT(13) 451*4882a593Smuzhiyun #define SOLO_VD_CFG_ERR_INT_ENA BIT(12) 452*4882a593Smuzhiyun #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) 453*4882a593Smuzhiyun #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #define SOLO_VD_CFG1 0x0904 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun #define SOLO_VD_DEINTERLACE 0x0908 458*4882a593Smuzhiyun #define SOLO_VD_DEINTERLACE_THRESHOLD(n) ((n)<<8) 459*4882a593Smuzhiyun #define SOLO_VD_DEINTERLACE_EDGE_VALUE(n) ((n)<<0) 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun #define SOLO_VD_CODE_ADR 0x090C 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define SOLO_VD_CTRL 0x0910 464*4882a593Smuzhiyun #define SOLO_VD_OPER_ON BIT(31) 465*4882a593Smuzhiyun #define SOLO_VD_MAX_ITEM(n) ((n)<<0) 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun #define SOLO_VD_STATUS0 0x0920 468*4882a593Smuzhiyun #define SOLO_VD_STATUS0_INTR_ACK BIT(22) 469*4882a593Smuzhiyun #define SOLO_VD_STATUS0_INTR_EMPTY BIT(21) 470*4882a593Smuzhiyun #define SOLO_VD_STATUS0_INTR_ERR BIT(20) 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun #define SOLO_VD_STATUS1 0x0924 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun #define SOLO_VD_IDX0 0x0930 475*4882a593Smuzhiyun #define SOLO_VD_IDX_INTERLACE BIT(30) 476*4882a593Smuzhiyun #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) 477*4882a593Smuzhiyun #define SOLO_VD_IDX_SIZE(n) ((n)<<0) 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun #define SOLO_VD_IDX1 0x0934 480*4882a593Smuzhiyun #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) 481*4882a593Smuzhiyun #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) 482*4882a593Smuzhiyun #define SOLO_VD_IDX_DEINTERLACE BIT(16) 483*4882a593Smuzhiyun #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) 484*4882a593Smuzhiyun #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun #define SOLO_VD_IDX2 0x0938 487*4882a593Smuzhiyun #define SOLO_VD_IDX_REF_BASE_SIDE BIT(31) 488*4882a593Smuzhiyun #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun #define SOLO_VD_IDX3 0x093C 491*4882a593Smuzhiyun #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) 492*4882a593Smuzhiyun #define SOLO_VD_IDX_INTERLACE_WR BIT(27) 493*4882a593Smuzhiyun #define SOLO_VD_IDX_INTERPOL BIT(26) 494*4882a593Smuzhiyun #define SOLO_VD_IDX_HOR2X BIT(25) 495*4882a593Smuzhiyun #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) 496*4882a593Smuzhiyun #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun #define SOLO_VD_IDX4 0x0940 499*4882a593Smuzhiyun #define SOLO_VD_IDX_DEC_WR_PAGE(n) ((n)<<8) 500*4882a593Smuzhiyun #define SOLO_VD_IDX_DISP_RD_PAGE(n) ((n)<<0) 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun #define SOLO_VD_WR_PAGE(n) (0x03F0 + ((n) * 4)) 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun #define SOLO_GPIO_CONFIG_0 0x0B00 506*4882a593Smuzhiyun #define SOLO_GPIO_CONFIG_1 0x0B04 507*4882a593Smuzhiyun #define SOLO_GPIO_DATA_OUT 0x0B08 508*4882a593Smuzhiyun #define SOLO_GPIO_DATA_IN 0x0B0C 509*4882a593Smuzhiyun #define SOLO_GPIO_INT_ACK_STA 0x0B10 510*4882a593Smuzhiyun #define SOLO_GPIO_INT_ENA 0x0B14 511*4882a593Smuzhiyun #define SOLO_GPIO_INT_CFG_0 0x0B18 512*4882a593Smuzhiyun #define SOLO_GPIO_INT_CFG_1 0x0B1C 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun #define SOLO_IIC_CFG 0x0B20 516*4882a593Smuzhiyun #define SOLO_IIC_ENABLE BIT(8) 517*4882a593Smuzhiyun #define SOLO_IIC_PRESCALE(n) ((n)<<0) 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun #define SOLO_IIC_CTRL 0x0B24 520*4882a593Smuzhiyun #define SOLO_IIC_AUTO_CLEAR BIT(20) 521*4882a593Smuzhiyun #define SOLO_IIC_STATE_RX_ACK BIT(19) 522*4882a593Smuzhiyun #define SOLO_IIC_STATE_BUSY BIT(18) 523*4882a593Smuzhiyun #define SOLO_IIC_STATE_SIG_ERR BIT(17) 524*4882a593Smuzhiyun #define SOLO_IIC_STATE_TRNS BIT(16) 525*4882a593Smuzhiyun #define SOLO_IIC_CH_SET(n) ((n)<<5) 526*4882a593Smuzhiyun #define SOLO_IIC_ACK_EN BIT(4) 527*4882a593Smuzhiyun #define SOLO_IIC_START BIT(3) 528*4882a593Smuzhiyun #define SOLO_IIC_STOP BIT(2) 529*4882a593Smuzhiyun #define SOLO_IIC_READ BIT(1) 530*4882a593Smuzhiyun #define SOLO_IIC_WRITE BIT(0) 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun #define SOLO_IIC_TXD 0x0B28 533*4882a593Smuzhiyun #define SOLO_IIC_RXD 0x0B2C 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* 536*4882a593Smuzhiyun * UART REGISTER 537*4882a593Smuzhiyun */ 538*4882a593Smuzhiyun #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) 539*4882a593Smuzhiyun #define SOLO_UART_CLK_DIV(n) ((n)<<24) 540*4882a593Smuzhiyun #define SOLO_MODEM_CTRL_EN BIT(20) 541*4882a593Smuzhiyun #define SOLO_PARITY_ERROR_DROP BIT(18) 542*4882a593Smuzhiyun #define SOLO_IRQ_ERR_EN BIT(17) 543*4882a593Smuzhiyun #define SOLO_IRQ_RX_EN BIT(16) 544*4882a593Smuzhiyun #define SOLO_IRQ_TX_EN BIT(15) 545*4882a593Smuzhiyun #define SOLO_RX_EN BIT(14) 546*4882a593Smuzhiyun #define SOLO_TX_EN BIT(13) 547*4882a593Smuzhiyun #define SOLO_UART_HALF_DUPLEX BIT(12) 548*4882a593Smuzhiyun #define SOLO_UART_LOOPBACK BIT(11) 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) 551*4882a593Smuzhiyun #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) 552*4882a593Smuzhiyun #define SOLO_BAUDRATE_57600 ((0<<9)|(2<<6)) 553*4882a593Smuzhiyun #define SOLO_BAUDRATE_38400 ((0<<9)|(3<<6)) 554*4882a593Smuzhiyun #define SOLO_BAUDRATE_19200 ((0<<9)|(4<<6)) 555*4882a593Smuzhiyun #define SOLO_BAUDRATE_9600 ((0<<9)|(5<<6)) 556*4882a593Smuzhiyun #define SOLO_BAUDRATE_4800 ((0<<9)|(6<<6)) 557*4882a593Smuzhiyun #define SOLO_BAUDRATE_2400 ((1<<9)|(6<<6)) 558*4882a593Smuzhiyun #define SOLO_BAUDRATE_1200 ((2<<9)|(6<<6)) 559*4882a593Smuzhiyun #define SOLO_BAUDRATE_300 ((3<<9)|(6<<6)) 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun #define SOLO_UART_DATA_BIT_8 (3<<4) 562*4882a593Smuzhiyun #define SOLO_UART_DATA_BIT_7 (2<<4) 563*4882a593Smuzhiyun #define SOLO_UART_DATA_BIT_6 (1<<4) 564*4882a593Smuzhiyun #define SOLO_UART_DATA_BIT_5 (0<<4) 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun #define SOLO_UART_STOP_BIT_1 (0<<2) 567*4882a593Smuzhiyun #define SOLO_UART_STOP_BIT_2 (1<<2) 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun #define SOLO_UART_PARITY_NONE (0<<0) 570*4882a593Smuzhiyun #define SOLO_UART_PARITY_EVEN (2<<0) 571*4882a593Smuzhiyun #define SOLO_UART_PARITY_ODD (3<<0) 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) 574*4882a593Smuzhiyun #define SOLO_UART_CTS BIT(15) 575*4882a593Smuzhiyun #define SOLO_UART_RX_BUSY BIT(14) 576*4882a593Smuzhiyun #define SOLO_UART_OVERRUN BIT(13) 577*4882a593Smuzhiyun #define SOLO_UART_FRAME_ERR BIT(12) 578*4882a593Smuzhiyun #define SOLO_UART_PARITY_ERR BIT(11) 579*4882a593Smuzhiyun #define SOLO_UART_TX_BUSY BIT(5) 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) 582*4882a593Smuzhiyun #define SOLO_UART_RX_BUFF_SIZE 8 583*4882a593Smuzhiyun #define SOLO_UART_TX_BUFF_CNT(stat) (((stat)>>0) & 0x1f) 584*4882a593Smuzhiyun #define SOLO_UART_TX_BUFF_SIZE 8 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) 587*4882a593Smuzhiyun #define SOLO_UART_TX_DATA_PUSH BIT(8) 588*4882a593Smuzhiyun #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) 589*4882a593Smuzhiyun #define SOLO_UART_RX_DATA_POP BIT(8) 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun #define SOLO_TIMER_CLOCK_NUM 0x0be0 592*4882a593Smuzhiyun #define SOLO_TIMER_USEC 0x0be8 593*4882a593Smuzhiyun #define SOLO_TIMER_SEC 0x0bec 594*4882a593Smuzhiyun #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #define SOLO_AUDIO_CONTROL 0x0D00 597*4882a593Smuzhiyun #define SOLO_AUDIO_ENABLE BIT(31) 598*4882a593Smuzhiyun #define SOLO_AUDIO_MASTER_MODE BIT(30) 599*4882a593Smuzhiyun #define SOLO_AUDIO_I2S_MODE BIT(29) 600*4882a593Smuzhiyun #define SOLO_AUDIO_I2S_LR_SWAP BIT(27) 601*4882a593Smuzhiyun #define SOLO_AUDIO_I2S_8BIT BIT(26) 602*4882a593Smuzhiyun #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) 603*4882a593Smuzhiyun #define SOLO_AUDIO_MIX_9TO0 BIT(23) 604*4882a593Smuzhiyun #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) 605*4882a593Smuzhiyun #define SOLO_AUDIO_MIX_19TO10 BIT(19) 606*4882a593Smuzhiyun #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) 607*4882a593Smuzhiyun #define SOLO_AUDIO_MODE(n) ((n)<<0) 608*4882a593Smuzhiyun #define SOLO_AUDIO_SAMPLE 0x0D04 609*4882a593Smuzhiyun #define SOLO_AUDIO_EE_MODE_ON BIT(30) 610*4882a593Smuzhiyun #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) 611*4882a593Smuzhiyun #define SOLO_AUDIO_BITRATE(n) ((n)<<16) 612*4882a593Smuzhiyun #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) 613*4882a593Smuzhiyun #define SOLO_AUDIO_FDMA_INTR 0x0D08 614*4882a593Smuzhiyun #define SOLO_AUDIO_FDMA_INTERVAL(n) ((n)<<19) 615*4882a593Smuzhiyun #define SOLO_AUDIO_INTR_ORDER(n) ((n)<<16) 616*4882a593Smuzhiyun #define SOLO_AUDIO_FDMA_BASE(n) ((n)<<0) 617*4882a593Smuzhiyun #define SOLO_AUDIO_EVOL_0 0x0D0C 618*4882a593Smuzhiyun #define SOLO_AUDIO_EVOL_1 0x0D10 619*4882a593Smuzhiyun #define SOLO_AUDIO_EVOL(ch, value) ((value)<<((ch)%10)) 620*4882a593Smuzhiyun #define SOLO_AUDIO_STA 0x0D14 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun /* 623*4882a593Smuzhiyun * Watchdog configuration 624*4882a593Smuzhiyun */ 625*4882a593Smuzhiyun #define SOLO_WATCHDOG 0x0be4 626*4882a593Smuzhiyun #define SOLO_WATCHDOG_SET(status, sec) (status << 8 | (sec & 0xff)) 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun #endif /* __SOLO6X10_REGISTERS_H */ 629