1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Original author:
6*4882a593Smuzhiyun * Ben Collins <bcollins@ubuntu.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Additional work by:
9*4882a593Smuzhiyun * John Brooks <john.brooks@bluecherry.net>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "solo6x10.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static int multi_p2m;
19*4882a593Smuzhiyun module_param(multi_p2m, uint, 0644);
20*4882a593Smuzhiyun MODULE_PARM_DESC(multi_p2m,
21*4882a593Smuzhiyun "Use multiple P2M DMA channels (default: no, 6010-only)");
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static int desc_mode;
24*4882a593Smuzhiyun module_param(desc_mode, uint, 0644);
25*4882a593Smuzhiyun MODULE_PARM_DESC(desc_mode,
26*4882a593Smuzhiyun "Allow use of descriptor mode DMA (default: no, 6010-only)");
27*4882a593Smuzhiyun
solo_p2m_dma(struct solo_dev * solo_dev,int wr,void * sys_addr,u32 ext_addr,u32 size,int repeat,u32 ext_size)28*4882a593Smuzhiyun int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
29*4882a593Smuzhiyun void *sys_addr, u32 ext_addr, u32 size,
30*4882a593Smuzhiyun int repeat, u32 ext_size)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun dma_addr_t dma_addr;
33*4882a593Smuzhiyun int ret;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
36*4882a593Smuzhiyun return -EINVAL;
37*4882a593Smuzhiyun if (WARN_ON_ONCE(!size))
38*4882a593Smuzhiyun return -EINVAL;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
41*4882a593Smuzhiyun wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
42*4882a593Smuzhiyun if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
43*4882a593Smuzhiyun return -ENOMEM;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
46*4882a593Smuzhiyun repeat, ext_size);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun pci_unmap_single(solo_dev->pdev, dma_addr, size,
49*4882a593Smuzhiyun wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return ret;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Mutex must be held for p2m_id before calling this!! */
solo_p2m_dma_desc(struct solo_dev * solo_dev,struct solo_p2m_desc * desc,dma_addr_t desc_dma,int desc_cnt)55*4882a593Smuzhiyun int solo_p2m_dma_desc(struct solo_dev *solo_dev,
56*4882a593Smuzhiyun struct solo_p2m_desc *desc, dma_addr_t desc_dma,
57*4882a593Smuzhiyun int desc_cnt)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct solo_p2m_dev *p2m_dev;
60*4882a593Smuzhiyun unsigned int timeout;
61*4882a593Smuzhiyun unsigned int config = 0;
62*4882a593Smuzhiyun int ret = 0;
63*4882a593Smuzhiyun unsigned int p2m_id = 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
66*4882a593Smuzhiyun if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
67*4882a593Smuzhiyun p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun p2m_dev = &solo_dev->p2m_dev[p2m_id];
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (mutex_lock_interruptible(&p2m_dev->mutex))
72*4882a593Smuzhiyun return -EINTR;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun reinit_completion(&p2m_dev->completion);
75*4882a593Smuzhiyun p2m_dev->error = 0;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
78*4882a593Smuzhiyun /* For 6010 with more than one desc, we can do a one-shot */
79*4882a593Smuzhiyun p2m_dev->desc_count = p2m_dev->desc_idx = 0;
80*4882a593Smuzhiyun config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
83*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
84*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
85*4882a593Smuzhiyun SOLO_P2M_DESC_MODE);
86*4882a593Smuzhiyun } else {
87*4882a593Smuzhiyun /* For single descriptors and 6110, we need to run each desc */
88*4882a593Smuzhiyun p2m_dev->desc_count = desc_cnt;
89*4882a593Smuzhiyun p2m_dev->desc_idx = 1;
90*4882a593Smuzhiyun p2m_dev->descs = desc;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
93*4882a593Smuzhiyun desc[1].dma_addr);
94*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
95*4882a593Smuzhiyun desc[1].ext_addr);
96*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
97*4882a593Smuzhiyun desc[1].cfg);
98*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
99*4882a593Smuzhiyun desc[1].ctrl);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun timeout = wait_for_completion_timeout(&p2m_dev->completion,
103*4882a593Smuzhiyun solo_dev->p2m_jiffies);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (WARN_ON_ONCE(p2m_dev->error))
106*4882a593Smuzhiyun ret = -EIO;
107*4882a593Smuzhiyun else if (timeout == 0) {
108*4882a593Smuzhiyun solo_dev->p2m_timeouts++;
109*4882a593Smuzhiyun ret = -EAGAIN;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Don't write here for the no_desc_mode case, because config is 0.
115*4882a593Smuzhiyun * We can't test no_desc_mode again, it might race. */
116*4882a593Smuzhiyun if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
117*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun mutex_unlock(&p2m_dev->mutex);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return ret;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
solo_p2m_fill_desc(struct solo_p2m_desc * desc,int wr,dma_addr_t dma_addr,u32 ext_addr,u32 size,int repeat,u32 ext_size)124*4882a593Smuzhiyun void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
125*4882a593Smuzhiyun dma_addr_t dma_addr, u32 ext_addr, u32 size,
126*4882a593Smuzhiyun int repeat, u32 ext_size)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun WARN_ON_ONCE(dma_addr & 0x03);
129*4882a593Smuzhiyun WARN_ON_ONCE(!size);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
132*4882a593Smuzhiyun desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
133*4882a593Smuzhiyun (wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun if (repeat) {
136*4882a593Smuzhiyun desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
137*4882a593Smuzhiyun desc->ctrl |= SOLO_P2M_PCI_INC(size >> 2) |
138*4882a593Smuzhiyun SOLO_P2M_REPEAT(repeat);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun desc->dma_addr = dma_addr;
142*4882a593Smuzhiyun desc->ext_addr = ext_addr;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
solo_p2m_dma_t(struct solo_dev * solo_dev,int wr,dma_addr_t dma_addr,u32 ext_addr,u32 size,int repeat,u32 ext_size)145*4882a593Smuzhiyun int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
146*4882a593Smuzhiyun dma_addr_t dma_addr, u32 ext_addr, u32 size,
147*4882a593Smuzhiyun int repeat, u32 ext_size)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct solo_p2m_desc desc[2];
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
152*4882a593Smuzhiyun ext_size);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* No need for desc_dma since we know it is a single-shot */
155*4882a593Smuzhiyun return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
solo_p2m_isr(struct solo_dev * solo_dev,int id)158*4882a593Smuzhiyun void solo_p2m_isr(struct solo_dev *solo_dev, int id)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
161*4882a593Smuzhiyun struct solo_p2m_desc *desc;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
164*4882a593Smuzhiyun complete(&p2m_dev->completion);
165*4882a593Smuzhiyun return;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Setup next descriptor */
169*4882a593Smuzhiyun p2m_dev->desc_idx++;
170*4882a593Smuzhiyun desc = &p2m_dev->descs[p2m_dev->desc_idx];
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
173*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
174*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
175*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
176*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
solo_p2m_error_isr(struct solo_dev * solo_dev)179*4882a593Smuzhiyun void solo_p2m_error_isr(struct solo_dev *solo_dev)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
182*4882a593Smuzhiyun struct solo_p2m_dev *p2m_dev;
183*4882a593Smuzhiyun int i;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
186*4882a593Smuzhiyun return;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun for (i = 0; i < SOLO_NR_P2M; i++) {
189*4882a593Smuzhiyun p2m_dev = &solo_dev->p2m_dev[i];
190*4882a593Smuzhiyun p2m_dev->error = 1;
191*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
192*4882a593Smuzhiyun complete(&p2m_dev->completion);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
solo_p2m_exit(struct solo_dev * solo_dev)196*4882a593Smuzhiyun void solo_p2m_exit(struct solo_dev *solo_dev)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun int i;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun for (i = 0; i < SOLO_NR_P2M; i++)
201*4882a593Smuzhiyun solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
solo_p2m_test(struct solo_dev * solo_dev,int base,int size)204*4882a593Smuzhiyun static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun u32 *wr_buf;
207*4882a593Smuzhiyun u32 *rd_buf;
208*4882a593Smuzhiyun int i;
209*4882a593Smuzhiyun int ret = -EIO;
210*4882a593Smuzhiyun int order = get_order(size);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
213*4882a593Smuzhiyun if (wr_buf == NULL)
214*4882a593Smuzhiyun return -1;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
217*4882a593Smuzhiyun if (rd_buf == NULL) {
218*4882a593Smuzhiyun free_pages((unsigned long)wr_buf, order);
219*4882a593Smuzhiyun return -1;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun for (i = 0; i < (size >> 3); i++)
223*4882a593Smuzhiyun *(wr_buf + i) = (i << 16) | (i + 1);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun for (i = (size >> 3); i < (size >> 2); i++)
226*4882a593Smuzhiyun *(wr_buf + i) = ~((i << 16) | (i + 1));
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun memset(rd_buf, 0x55, size);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
231*4882a593Smuzhiyun goto test_fail;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
234*4882a593Smuzhiyun goto test_fail;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun for (i = 0; i < (size >> 2); i++) {
237*4882a593Smuzhiyun if (*(wr_buf + i) != *(rd_buf + i))
238*4882a593Smuzhiyun goto test_fail;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun ret = 0;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun test_fail:
244*4882a593Smuzhiyun free_pages((unsigned long)wr_buf, order);
245*4882a593Smuzhiyun free_pages((unsigned long)rd_buf, order);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun return ret;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
solo_p2m_init(struct solo_dev * solo_dev)250*4882a593Smuzhiyun int solo_p2m_init(struct solo_dev *solo_dev)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun struct solo_p2m_dev *p2m_dev;
253*4882a593Smuzhiyun int i;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun for (i = 0; i < SOLO_NR_P2M; i++) {
256*4882a593Smuzhiyun p2m_dev = &solo_dev->p2m_dev[i];
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun mutex_init(&p2m_dev->mutex);
259*4882a593Smuzhiyun init_completion(&p2m_dev->completion);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
262*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
263*4882a593Smuzhiyun SOLO_P2M_CSC_16BIT_565 |
264*4882a593Smuzhiyun SOLO_P2M_DESC_INTR_OPT |
265*4882a593Smuzhiyun SOLO_P2M_DMA_INTERVAL(0) |
266*4882a593Smuzhiyun SOLO_P2M_PCI_MASTER_MODE);
267*4882a593Smuzhiyun solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /* Find correct SDRAM size */
271*4882a593Smuzhiyun for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
272*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_DMA_CTRL,
273*4882a593Smuzhiyun SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
274*4882a593Smuzhiyun SOLO_DMA_CTRL_SDRAM_SIZE(i) |
275*4882a593Smuzhiyun SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
276*4882a593Smuzhiyun SOLO_DMA_CTRL_READ_CLK_SELECT |
277*4882a593Smuzhiyun SOLO_DMA_CTRL_LATENCY(1));
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
280*4882a593Smuzhiyun SOLO_SYS_CFG_RESET);
281*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun switch (i) {
284*4882a593Smuzhiyun case 2:
285*4882a593Smuzhiyun if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
286*4882a593Smuzhiyun solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
287*4882a593Smuzhiyun continue;
288*4882a593Smuzhiyun break;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun case 1:
291*4882a593Smuzhiyun if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
292*4882a593Smuzhiyun continue;
293*4882a593Smuzhiyun break;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun default:
296*4882a593Smuzhiyun if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
297*4882a593Smuzhiyun continue;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun solo_dev->sdram_size = (32 << 20) << i;
301*4882a593Smuzhiyun break;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (!solo_dev->sdram_size) {
305*4882a593Smuzhiyun dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
306*4882a593Smuzhiyun return -EIO;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
310*4882a593Smuzhiyun dev_err(&solo_dev->pdev->dev,
311*4882a593Smuzhiyun "SDRAM is not large enough (%u < %u)\n",
312*4882a593Smuzhiyun solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
313*4882a593Smuzhiyun return -EIO;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318