1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Original author:
6*4882a593Smuzhiyun * Ben Collins <bcollins@ubuntu.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Additional work by:
9*4882a593Smuzhiyun * John Brooks <john.brooks@bluecherry.net>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* XXX: The SOLO6x10 i2c does not have separate interrupts for each i2c
13*4882a593Smuzhiyun * channel. The bus can only handle one i2c event at a time. The below handles
14*4882a593Smuzhiyun * this all wrong. We should be using the status registers to see if the bus
15*4882a593Smuzhiyun * is in use, and have a global lock to check the status register. Also,
16*4882a593Smuzhiyun * the bulk of the work should be handled out-of-interrupt. The ugly loops
17*4882a593Smuzhiyun * that occur during interrupt scare me. The ISR should merely signal
18*4882a593Smuzhiyun * thread context, ACK the interrupt, and move on. -- BenC */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/sched/signal.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "solo6x10.h"
24*4882a593Smuzhiyun
solo_i2c_readbyte(struct solo_dev * solo_dev,int id,u8 addr,u8 off)25*4882a593Smuzhiyun u8 solo_i2c_readbyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct i2c_msg msgs[2];
28*4882a593Smuzhiyun u8 data;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun msgs[0].flags = 0;
31*4882a593Smuzhiyun msgs[0].addr = addr;
32*4882a593Smuzhiyun msgs[0].len = 1;
33*4882a593Smuzhiyun msgs[0].buf = &off;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
36*4882a593Smuzhiyun msgs[1].addr = addr;
37*4882a593Smuzhiyun msgs[1].len = 1;
38*4882a593Smuzhiyun msgs[1].buf = &data;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun i2c_transfer(&solo_dev->i2c_adap[id], msgs, 2);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return data;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
solo_i2c_writebyte(struct solo_dev * solo_dev,int id,u8 addr,u8 off,u8 data)45*4882a593Smuzhiyun void solo_i2c_writebyte(struct solo_dev *solo_dev, int id, u8 addr,
46*4882a593Smuzhiyun u8 off, u8 data)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct i2c_msg msgs;
49*4882a593Smuzhiyun u8 buf[2];
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun buf[0] = off;
52*4882a593Smuzhiyun buf[1] = data;
53*4882a593Smuzhiyun msgs.flags = 0;
54*4882a593Smuzhiyun msgs.addr = addr;
55*4882a593Smuzhiyun msgs.len = 2;
56*4882a593Smuzhiyun msgs.buf = buf;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun i2c_transfer(&solo_dev->i2c_adap[id], &msgs, 1);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
solo_i2c_flush(struct solo_dev * solo_dev,int wr)61*4882a593Smuzhiyun static void solo_i2c_flush(struct solo_dev *solo_dev, int wr)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u32 ctrl;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun ctrl = SOLO_IIC_CH_SET(solo_dev->i2c_id);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (solo_dev->i2c_state == IIC_STATE_START)
68*4882a593Smuzhiyun ctrl |= SOLO_IIC_START;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (wr) {
71*4882a593Smuzhiyun ctrl |= SOLO_IIC_WRITE;
72*4882a593Smuzhiyun } else {
73*4882a593Smuzhiyun ctrl |= SOLO_IIC_READ;
74*4882a593Smuzhiyun if (!(solo_dev->i2c_msg->flags & I2C_M_NO_RD_ACK))
75*4882a593Smuzhiyun ctrl |= SOLO_IIC_ACK_EN;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (solo_dev->i2c_msg_ptr == solo_dev->i2c_msg->len)
79*4882a593Smuzhiyun ctrl |= SOLO_IIC_STOP;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_CTRL, ctrl);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
solo_i2c_start(struct solo_dev * solo_dev)84*4882a593Smuzhiyun static void solo_i2c_start(struct solo_dev *solo_dev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun u32 addr = solo_dev->i2c_msg->addr << 1;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (solo_dev->i2c_msg->flags & I2C_M_RD)
89*4882a593Smuzhiyun addr |= 1;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_START;
92*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_TXD, addr);
93*4882a593Smuzhiyun solo_i2c_flush(solo_dev, 1);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
solo_i2c_stop(struct solo_dev * solo_dev)96*4882a593Smuzhiyun static void solo_i2c_stop(struct solo_dev *solo_dev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun solo_irq_off(solo_dev, SOLO_IRQ_IIC);
99*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_CTRL, 0);
100*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_STOP;
101*4882a593Smuzhiyun wake_up(&solo_dev->i2c_wait);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
solo_i2c_handle_read(struct solo_dev * solo_dev)104*4882a593Smuzhiyun static int solo_i2c_handle_read(struct solo_dev *solo_dev)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun prepare_read:
107*4882a593Smuzhiyun if (solo_dev->i2c_msg_ptr != solo_dev->i2c_msg->len) {
108*4882a593Smuzhiyun solo_i2c_flush(solo_dev, 0);
109*4882a593Smuzhiyun return 0;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun solo_dev->i2c_msg_ptr = 0;
113*4882a593Smuzhiyun solo_dev->i2c_msg++;
114*4882a593Smuzhiyun solo_dev->i2c_msg_num--;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (solo_dev->i2c_msg_num == 0) {
117*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (!(solo_dev->i2c_msg->flags & I2C_M_NOSTART)) {
122*4882a593Smuzhiyun solo_i2c_start(solo_dev);
123*4882a593Smuzhiyun } else {
124*4882a593Smuzhiyun if (solo_dev->i2c_msg->flags & I2C_M_RD)
125*4882a593Smuzhiyun goto prepare_read;
126*4882a593Smuzhiyun else
127*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
solo_i2c_handle_write(struct solo_dev * solo_dev)133*4882a593Smuzhiyun static int solo_i2c_handle_write(struct solo_dev *solo_dev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun retry_write:
136*4882a593Smuzhiyun if (solo_dev->i2c_msg_ptr != solo_dev->i2c_msg->len) {
137*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_TXD,
138*4882a593Smuzhiyun solo_dev->i2c_msg->buf[solo_dev->i2c_msg_ptr]);
139*4882a593Smuzhiyun solo_dev->i2c_msg_ptr++;
140*4882a593Smuzhiyun solo_i2c_flush(solo_dev, 1);
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun solo_dev->i2c_msg_ptr = 0;
145*4882a593Smuzhiyun solo_dev->i2c_msg++;
146*4882a593Smuzhiyun solo_dev->i2c_msg_num--;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun if (solo_dev->i2c_msg_num == 0) {
149*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (!(solo_dev->i2c_msg->flags & I2C_M_NOSTART)) {
154*4882a593Smuzhiyun solo_i2c_start(solo_dev);
155*4882a593Smuzhiyun } else {
156*4882a593Smuzhiyun if (solo_dev->i2c_msg->flags & I2C_M_RD)
157*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
158*4882a593Smuzhiyun else
159*4882a593Smuzhiyun goto retry_write;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
solo_i2c_isr(struct solo_dev * solo_dev)165*4882a593Smuzhiyun int solo_i2c_isr(struct solo_dev *solo_dev)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun u32 status = solo_reg_read(solo_dev, SOLO_IIC_CTRL);
168*4882a593Smuzhiyun int ret = -EINVAL;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun if (CHK_FLAGS(status, SOLO_IIC_STATE_TRNS | SOLO_IIC_STATE_SIG_ERR)
172*4882a593Smuzhiyun || solo_dev->i2c_id < 0) {
173*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
174*4882a593Smuzhiyun return -ENXIO;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun switch (solo_dev->i2c_state) {
178*4882a593Smuzhiyun case IIC_STATE_START:
179*4882a593Smuzhiyun if (solo_dev->i2c_msg->flags & I2C_M_RD) {
180*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_READ;
181*4882a593Smuzhiyun ret = solo_i2c_handle_read(solo_dev);
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_WRITE;
186*4882a593Smuzhiyun fallthrough;
187*4882a593Smuzhiyun case IIC_STATE_WRITE:
188*4882a593Smuzhiyun ret = solo_i2c_handle_write(solo_dev);
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun case IIC_STATE_READ:
192*4882a593Smuzhiyun solo_dev->i2c_msg->buf[solo_dev->i2c_msg_ptr] =
193*4882a593Smuzhiyun solo_reg_read(solo_dev, SOLO_IIC_RXD);
194*4882a593Smuzhiyun solo_dev->i2c_msg_ptr++;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun ret = solo_i2c_handle_read(solo_dev);
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun default:
200*4882a593Smuzhiyun solo_i2c_stop(solo_dev);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun return ret;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
solo_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)206*4882a593Smuzhiyun static int solo_i2c_master_xfer(struct i2c_adapter *adap,
207*4882a593Smuzhiyun struct i2c_msg msgs[], int num)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct solo_dev *solo_dev = adap->algo_data;
210*4882a593Smuzhiyun unsigned long timeout;
211*4882a593Smuzhiyun int ret;
212*4882a593Smuzhiyun int i;
213*4882a593Smuzhiyun DEFINE_WAIT(wait);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
216*4882a593Smuzhiyun if (&solo_dev->i2c_adap[i] == adap)
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (i == SOLO_I2C_ADAPTERS)
221*4882a593Smuzhiyun return num; /* XXX Right return value for failure? */
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun mutex_lock(&solo_dev->i2c_mutex);
224*4882a593Smuzhiyun solo_dev->i2c_id = i;
225*4882a593Smuzhiyun solo_dev->i2c_msg = msgs;
226*4882a593Smuzhiyun solo_dev->i2c_msg_num = num;
227*4882a593Smuzhiyun solo_dev->i2c_msg_ptr = 0;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_CTRL, 0);
230*4882a593Smuzhiyun solo_irq_on(solo_dev, SOLO_IRQ_IIC);
231*4882a593Smuzhiyun solo_i2c_start(solo_dev);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun timeout = HZ / 2;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun for (;;) {
236*4882a593Smuzhiyun prepare_to_wait(&solo_dev->i2c_wait, &wait,
237*4882a593Smuzhiyun TASK_INTERRUPTIBLE);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun if (solo_dev->i2c_state == IIC_STATE_STOP)
240*4882a593Smuzhiyun break;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun timeout = schedule_timeout(timeout);
243*4882a593Smuzhiyun if (!timeout)
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (signal_pending(current))
247*4882a593Smuzhiyun break;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun finish_wait(&solo_dev->i2c_wait, &wait);
251*4882a593Smuzhiyun ret = num - solo_dev->i2c_msg_num;
252*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_IDLE;
253*4882a593Smuzhiyun solo_dev->i2c_id = -1;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun mutex_unlock(&solo_dev->i2c_mutex);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun return ret;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
solo_i2c_functionality(struct i2c_adapter * adap)260*4882a593Smuzhiyun static u32 solo_i2c_functionality(struct i2c_adapter *adap)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun return I2C_FUNC_I2C;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun static const struct i2c_algorithm solo_i2c_algo = {
266*4882a593Smuzhiyun .master_xfer = solo_i2c_master_xfer,
267*4882a593Smuzhiyun .functionality = solo_i2c_functionality,
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun
solo_i2c_init(struct solo_dev * solo_dev)270*4882a593Smuzhiyun int solo_i2c_init(struct solo_dev *solo_dev)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun int i;
273*4882a593Smuzhiyun int ret;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun solo_reg_write(solo_dev, SOLO_IIC_CFG,
276*4882a593Smuzhiyun SOLO_IIC_PRESCALE(8) | SOLO_IIC_ENABLE);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun solo_dev->i2c_id = -1;
279*4882a593Smuzhiyun solo_dev->i2c_state = IIC_STATE_IDLE;
280*4882a593Smuzhiyun init_waitqueue_head(&solo_dev->i2c_wait);
281*4882a593Smuzhiyun mutex_init(&solo_dev->i2c_mutex);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
284*4882a593Smuzhiyun struct i2c_adapter *adap = &solo_dev->i2c_adap[i];
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun snprintf(adap->name, I2C_NAME_SIZE, "%s I2C %d",
287*4882a593Smuzhiyun SOLO6X10_NAME, i);
288*4882a593Smuzhiyun adap->algo = &solo_i2c_algo;
289*4882a593Smuzhiyun adap->algo_data = solo_dev;
290*4882a593Smuzhiyun adap->retries = 1;
291*4882a593Smuzhiyun adap->dev.parent = &solo_dev->pdev->dev;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun ret = i2c_add_adapter(adap);
294*4882a593Smuzhiyun if (ret) {
295*4882a593Smuzhiyun adap->algo_data = NULL;
296*4882a593Smuzhiyun break;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (ret) {
301*4882a593Smuzhiyun for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
302*4882a593Smuzhiyun if (!solo_dev->i2c_adap[i].algo_data)
303*4882a593Smuzhiyun break;
304*4882a593Smuzhiyun i2c_del_adapter(&solo_dev->i2c_adap[i]);
305*4882a593Smuzhiyun solo_dev->i2c_adap[i].algo_data = NULL;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
solo_i2c_exit(struct solo_dev * solo_dev)313*4882a593Smuzhiyun void solo_i2c_exit(struct solo_dev *solo_dev)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun int i;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
318*4882a593Smuzhiyun if (!solo_dev->i2c_adap[i].algo_data)
319*4882a593Smuzhiyun continue;
320*4882a593Smuzhiyun i2c_del_adapter(&solo_dev->i2c_adap[i]);
321*4882a593Smuzhiyun solo_dev->i2c_adap[i].algo_data = NULL;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun }
324