xref: /OK3568_Linux_fs/kernel/drivers/media/pci/solo6x10/solo6x10-enc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Original author:
6*4882a593Smuzhiyun  * Ben Collins <bcollins@ubuntu.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Additional work by:
9*4882a593Smuzhiyun  * John Brooks <john.brooks@bluecherry.net>
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/font.h>
14*4882a593Smuzhiyun #include <linux/bitrev.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include "solo6x10.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define VI_PROG_HSIZE			(1280 - 16)
20*4882a593Smuzhiyun #define VI_PROG_VSIZE			(1024 - 16)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define IRQ_LEVEL			2
23*4882a593Smuzhiyun 
solo_capture_config(struct solo_dev * solo_dev)24*4882a593Smuzhiyun static void solo_capture_config(struct solo_dev *solo_dev)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	unsigned long height;
27*4882a593Smuzhiyun 	unsigned long width;
28*4882a593Smuzhiyun 	void *buf;
29*4882a593Smuzhiyun 	int i;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_CAP_BASE,
32*4882a593Smuzhiyun 		       SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
33*4882a593Smuzhiyun 					  - SOLO_CAP_PAGE_SIZE) >> 16)
34*4882a593Smuzhiyun 		       | SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	/* XXX: Undocumented bits at b17 and b24 */
37*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6110) {
38*4882a593Smuzhiyun 		/* NOTE: Ref driver has (62 << 24) here as well, but it causes
39*4882a593Smuzhiyun 		 * wacked out frame timing on 4-port 6110. */
40*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_BTW,
41*4882a593Smuzhiyun 			       (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
42*4882a593Smuzhiyun 			       SOLO_CAP_MAX_BANDWIDTH(36));
43*4882a593Smuzhiyun 	} else {
44*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_BTW,
45*4882a593Smuzhiyun 			       (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
46*4882a593Smuzhiyun 			       SOLO_CAP_MAX_BANDWIDTH(32));
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	/* Set scale 1, 9 dimension */
50*4882a593Smuzhiyun 	width = solo_dev->video_hsize;
51*4882a593Smuzhiyun 	height = solo_dev->video_vsize;
52*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
53*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
54*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
55*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* Set scale 2, 10 dimension */
58*4882a593Smuzhiyun 	width = solo_dev->video_hsize / 2;
59*4882a593Smuzhiyun 	height = solo_dev->video_vsize;
60*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
61*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
62*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
63*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/* Set scale 3, 11 dimension */
66*4882a593Smuzhiyun 	width = solo_dev->video_hsize / 2;
67*4882a593Smuzhiyun 	height = solo_dev->video_vsize / 2;
68*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
69*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
70*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
71*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* Set scale 4, 12 dimension */
74*4882a593Smuzhiyun 	width = solo_dev->video_hsize / 3;
75*4882a593Smuzhiyun 	height = solo_dev->video_vsize / 3;
76*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
77*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
78*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
79*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	/* Set scale 5, 13 dimension */
82*4882a593Smuzhiyun 	width = solo_dev->video_hsize / 4;
83*4882a593Smuzhiyun 	height = solo_dev->video_vsize / 2;
84*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
85*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
86*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
87*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/* Progressive */
90*4882a593Smuzhiyun 	width = VI_PROG_HSIZE;
91*4882a593Smuzhiyun 	height = VI_PROG_VSIZE;
92*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_DIM_PROG,
93*4882a593Smuzhiyun 		       SOLO_DIM_H_MB_NUM(width / 16) |
94*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FRAME(height / 16) |
95*4882a593Smuzhiyun 		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* Clear OSD */
98*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
99*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
100*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
101*4882a593Smuzhiyun 		       0xF0 << 16 | 0x80 << 8 | 0x80);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6010)
104*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
105*4882a593Smuzhiyun 			       SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
106*4882a593Smuzhiyun 	else
107*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
108*4882a593Smuzhiyun 			       | SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* Clear OSG buffer */
111*4882a593Smuzhiyun 	buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
112*4882a593Smuzhiyun 	if (!buf)
113*4882a593Smuzhiyun 		return;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	for (i = 0; i < solo_dev->nr_chans; i++) {
116*4882a593Smuzhiyun 		solo_p2m_dma(solo_dev, 1, buf,
117*4882a593Smuzhiyun 			     SOLO_EOSD_EXT_ADDR +
118*4882a593Smuzhiyun 			     (SOLO_EOSD_EXT_SIZE(solo_dev) * i),
119*4882a593Smuzhiyun 			     SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 	kfree(buf);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define SOLO_OSD_WRITE_SIZE (16 * OSD_TEXT_MAX)
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* Should be called with enable_lock held */
solo_osd_print(struct solo_enc_dev * solo_enc)127*4882a593Smuzhiyun int solo_osd_print(struct solo_enc_dev *solo_enc)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	struct solo_dev *solo_dev = solo_enc->solo_dev;
130*4882a593Smuzhiyun 	u8 *str = solo_enc->osd_text;
131*4882a593Smuzhiyun 	u8 *buf = solo_enc->osd_buf;
132*4882a593Smuzhiyun 	u32 reg;
133*4882a593Smuzhiyun 	const struct font_desc *vga = find_font("VGA8x16");
134*4882a593Smuzhiyun 	const u8 *vga_data;
135*4882a593Smuzhiyun 	int i, j;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	if (WARN_ON_ONCE(!vga))
138*4882a593Smuzhiyun 		return -ENODEV;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
141*4882a593Smuzhiyun 	if (!*str) {
142*4882a593Smuzhiyun 		/* Disable OSD on this channel */
143*4882a593Smuzhiyun 		reg &= ~(1 << solo_enc->ch);
144*4882a593Smuzhiyun 		goto out;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	memset(buf, 0, SOLO_OSD_WRITE_SIZE);
148*4882a593Smuzhiyun 	vga_data = (const u8 *)vga->data;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	for (i = 0; *str; i++, str++) {
151*4882a593Smuzhiyun 		for (j = 0; j < 16; j++) {
152*4882a593Smuzhiyun 			buf[(j << 1) | (i & 1) | ((i & ~1) << 4)] =
153*4882a593Smuzhiyun 			    bitrev8(vga_data[(*str << 4) | j]);
154*4882a593Smuzhiyun 		}
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	solo_p2m_dma(solo_dev, 1, buf,
158*4882a593Smuzhiyun 		     SOLO_EOSD_EXT_ADDR_CHAN(solo_dev, solo_enc->ch),
159*4882a593Smuzhiyun 		     SOLO_OSD_WRITE_SIZE, 0, 0);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Enable OSD on this channel */
162*4882a593Smuzhiyun 	reg |= (1 << solo_enc->ch);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun out:
165*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
166*4882a593Smuzhiyun 	return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /*
170*4882a593Smuzhiyun  * Set channel Quality Profile (0-3).
171*4882a593Smuzhiyun  */
solo_s_jpeg_qp(struct solo_dev * solo_dev,unsigned int ch,unsigned int qp)172*4882a593Smuzhiyun void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
173*4882a593Smuzhiyun 		    unsigned int qp)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	unsigned long flags;
176*4882a593Smuzhiyun 	unsigned int idx, reg;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if ((ch > 31) || (qp > 3))
179*4882a593Smuzhiyun 		return;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6010)
182*4882a593Smuzhiyun 		return;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	if (ch < 16) {
185*4882a593Smuzhiyun 		idx = 0;
186*4882a593Smuzhiyun 		reg = SOLO_VE_JPEG_QP_CH_L;
187*4882a593Smuzhiyun 	} else {
188*4882a593Smuzhiyun 		ch -= 16;
189*4882a593Smuzhiyun 		idx = 1;
190*4882a593Smuzhiyun 		reg = SOLO_VE_JPEG_QP_CH_H;
191*4882a593Smuzhiyun 	}
192*4882a593Smuzhiyun 	ch *= 2;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	solo_dev->jpeg_qp[idx] &= ~(3 << ch);
197*4882a593Smuzhiyun 	solo_dev->jpeg_qp[idx] |= (qp & 3) << ch;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
solo_g_jpeg_qp(struct solo_dev * solo_dev,unsigned int ch)204*4882a593Smuzhiyun int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	int idx;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6010)
209*4882a593Smuzhiyun 		return 2;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (WARN_ON_ONCE(ch > 31))
212*4882a593Smuzhiyun 		return 2;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	if (ch < 16) {
215*4882a593Smuzhiyun 		idx = 0;
216*4882a593Smuzhiyun 	} else {
217*4882a593Smuzhiyun 		ch -= 16;
218*4882a593Smuzhiyun 		idx = 1;
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 	ch *= 2;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	return (solo_dev->jpeg_qp[idx] >> ch) & 3;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun #define SOLO_QP_INIT 0xaaaaaaaa
226*4882a593Smuzhiyun 
solo_jpeg_config(struct solo_dev * solo_dev)227*4882a593Smuzhiyun static void solo_jpeg_config(struct solo_dev *solo_dev)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6010) {
230*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
231*4882a593Smuzhiyun 			       (2 << 24) | (2 << 16) | (2 << 8) | 2);
232*4882a593Smuzhiyun 	} else {
233*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
234*4882a593Smuzhiyun 			       (4 << 24) | (3 << 16) | (2 << 8) | 1);
235*4882a593Smuzhiyun 	}
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	spin_lock_init(&solo_dev->jpeg_qp_lock);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	/* Initialize Quality Profile for all channels */
240*4882a593Smuzhiyun 	solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
241*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
242*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
245*4882a593Smuzhiyun 		(SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) |
246*4882a593Smuzhiyun 		((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
247*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
248*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6110) {
249*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
250*4882a593Smuzhiyun 			       (0 << 16) | (30 << 8) | 60);
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
solo_mp4e_config(struct solo_dev * solo_dev)254*4882a593Smuzhiyun static void solo_mp4e_config(struct solo_dev *solo_dev)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	int i;
257*4882a593Smuzhiyun 	u32 cfg;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_CFG0,
260*4882a593Smuzhiyun 		       SOLO_VE_INTR_CTRL(IRQ_LEVEL) |
261*4882a593Smuzhiyun 		       SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) |
262*4882a593Smuzhiyun 		       SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	cfg = SOLO_VE_BYTE_ALIGN(2) | SOLO_VE_INSERT_INDEX
266*4882a593Smuzhiyun 		| SOLO_VE_MOTION_MODE(0);
267*4882a593Smuzhiyun 	if (solo_dev->type != SOLO_DEV_6010) {
268*4882a593Smuzhiyun 		cfg |= SOLO_VE_MPEG_SIZE_H(
269*4882a593Smuzhiyun 			(SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
270*4882a593Smuzhiyun 		cfg |= SOLO_VE_JPEG_SIZE_H(
271*4882a593Smuzhiyun 			(SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
272*4882a593Smuzhiyun 	}
273*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
276*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
277*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
278*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6110)
279*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
280*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
281*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	solo_reg_write(solo_dev, SOLO_VE_ATTR,
284*4882a593Smuzhiyun 		       SOLO_VE_LITTLE_ENDIAN |
285*4882a593Smuzhiyun 		       SOLO_COMP_ATTR_FCODE(1) |
286*4882a593Smuzhiyun 		       SOLO_COMP_TIME_INC(0) |
287*4882a593Smuzhiyun 		       SOLO_COMP_TIME_WIDTH(15) |
288*4882a593Smuzhiyun 		       SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	for (i = 0; i < solo_dev->nr_chans; i++) {
291*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
292*4882a593Smuzhiyun 			       (SOLO_EREF_EXT_ADDR(solo_dev) +
293*4882a593Smuzhiyun 			       (i * SOLO_EREF_EXT_SIZE)) >> 16);
294*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
295*4882a593Smuzhiyun 			       (SOLO_EREF_EXT_ADDR(solo_dev) +
296*4882a593Smuzhiyun 			       ((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	if (solo_dev->type == SOLO_DEV_6110) {
300*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
301*4882a593Smuzhiyun 	} else {
302*4882a593Smuzhiyun 		for (i = 0; i < solo_dev->nr_chans; i++)
303*4882a593Smuzhiyun 			solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
304*4882a593Smuzhiyun 	}
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
solo_enc_init(struct solo_dev * solo_dev)307*4882a593Smuzhiyun int solo_enc_init(struct solo_dev *solo_dev)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	int i;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	solo_capture_config(solo_dev);
312*4882a593Smuzhiyun 	solo_mp4e_config(solo_dev);
313*4882a593Smuzhiyun 	solo_jpeg_config(solo_dev);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	for (i = 0; i < solo_dev->nr_chans; i++) {
316*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
317*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
318*4882a593Smuzhiyun 	}
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
solo_enc_exit(struct solo_dev * solo_dev)323*4882a593Smuzhiyun void solo_enc_exit(struct solo_dev *solo_dev)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	int i;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	for (i = 0; i < solo_dev->nr_chans; i++) {
328*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
329*4882a593Smuzhiyun 		solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
330*4882a593Smuzhiyun 	}
331*4882a593Smuzhiyun }
332