1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SMI PCIe driver for DVBSky cards.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "smipcie.h"
9*4882a593Smuzhiyun #include "m88ds3103.h"
10*4882a593Smuzhiyun #include "ts2020.h"
11*4882a593Smuzhiyun #include "m88rs6000t.h"
12*4882a593Smuzhiyun #include "si2168.h"
13*4882a593Smuzhiyun #include "si2157.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
16*4882a593Smuzhiyun
smi_hw_init(struct smi_dev * dev)17*4882a593Smuzhiyun static int smi_hw_init(struct smi_dev *dev)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun u32 port_mux, port_ctrl, int_stat;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* set port mux.*/
22*4882a593Smuzhiyun port_mux = smi_read(MUX_MODE_CTRL);
23*4882a593Smuzhiyun port_mux &= ~(rbPaMSMask);
24*4882a593Smuzhiyun port_mux |= rbPaMSDtvNoGpio;
25*4882a593Smuzhiyun port_mux &= ~(rbPbMSMask);
26*4882a593Smuzhiyun port_mux |= rbPbMSDtvNoGpio;
27*4882a593Smuzhiyun port_mux &= ~(0x0f0000);
28*4882a593Smuzhiyun port_mux |= 0x50000;
29*4882a593Smuzhiyun smi_write(MUX_MODE_CTRL, port_mux);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* set DTV register.*/
32*4882a593Smuzhiyun /* Port A */
33*4882a593Smuzhiyun port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
34*4882a593Smuzhiyun port_ctrl &= ~0x01;
35*4882a593Smuzhiyun smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
36*4882a593Smuzhiyun port_ctrl = smi_read(MPEG2_CTRL_A);
37*4882a593Smuzhiyun port_ctrl &= ~0x40;
38*4882a593Smuzhiyun port_ctrl |= 0x80;
39*4882a593Smuzhiyun smi_write(MPEG2_CTRL_A, port_ctrl);
40*4882a593Smuzhiyun /* Port B */
41*4882a593Smuzhiyun port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
42*4882a593Smuzhiyun port_ctrl &= ~0x01;
43*4882a593Smuzhiyun smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
44*4882a593Smuzhiyun port_ctrl = smi_read(MPEG2_CTRL_B);
45*4882a593Smuzhiyun port_ctrl &= ~0x40;
46*4882a593Smuzhiyun port_ctrl |= 0x80;
47*4882a593Smuzhiyun smi_write(MPEG2_CTRL_B, port_ctrl);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* disable and clear interrupt.*/
50*4882a593Smuzhiyun smi_write(MSI_INT_ENA_CLR, ALL_INT);
51*4882a593Smuzhiyun int_stat = smi_read(MSI_INT_STATUS);
52*4882a593Smuzhiyun smi_write(MSI_INT_STATUS_CLR, int_stat);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* reset demod.*/
55*4882a593Smuzhiyun smi_clear(PERIPHERAL_CTRL, 0x0303);
56*4882a593Smuzhiyun msleep(50);
57*4882a593Smuzhiyun smi_set(PERIPHERAL_CTRL, 0x0101);
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* i2c bit bus.*/
smi_i2c_cfg(struct smi_dev * dev,u32 sw_ctl)62*4882a593Smuzhiyun static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun u32 dwCtrl;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun dwCtrl = smi_read(sw_ctl);
67*4882a593Smuzhiyun dwCtrl &= ~0x18; /* disable output.*/
68*4882a593Smuzhiyun dwCtrl |= 0x21; /* reset and software mode.*/
69*4882a593Smuzhiyun dwCtrl &= ~0xff00;
70*4882a593Smuzhiyun dwCtrl |= 0x6400;
71*4882a593Smuzhiyun smi_write(sw_ctl, dwCtrl);
72*4882a593Smuzhiyun msleep(20);
73*4882a593Smuzhiyun dwCtrl = smi_read(sw_ctl);
74*4882a593Smuzhiyun dwCtrl &= ~0x20;
75*4882a593Smuzhiyun smi_write(sw_ctl, dwCtrl);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
smi_i2c_setsda(struct smi_dev * dev,int state,u32 sw_ctl)78*4882a593Smuzhiyun static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun if (state) {
81*4882a593Smuzhiyun /* set as input.*/
82*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
83*4882a593Smuzhiyun } else {
84*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
85*4882a593Smuzhiyun /* set as output.*/
86*4882a593Smuzhiyun smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
smi_i2c_setscl(void * data,int state,u32 sw_ctl)90*4882a593Smuzhiyun static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct smi_dev *dev = data;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (state) {
95*4882a593Smuzhiyun /* set as input.*/
96*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
97*4882a593Smuzhiyun } else {
98*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
99*4882a593Smuzhiyun /* set as output.*/
100*4882a593Smuzhiyun smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
smi_i2c_getsda(void * data,u32 sw_ctl)104*4882a593Smuzhiyun static int smi_i2c_getsda(void *data, u32 sw_ctl)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct smi_dev *dev = data;
107*4882a593Smuzhiyun /* set as input.*/
108*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
109*4882a593Smuzhiyun udelay(1);
110*4882a593Smuzhiyun return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
smi_i2c_getscl(void * data,u32 sw_ctl)113*4882a593Smuzhiyun static int smi_i2c_getscl(void *data, u32 sw_ctl)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct smi_dev *dev = data;
116*4882a593Smuzhiyun /* set as input.*/
117*4882a593Smuzhiyun smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
118*4882a593Smuzhiyun udelay(1);
119*4882a593Smuzhiyun return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun /* i2c 0.*/
smi_i2c0_setsda(void * data,int state)122*4882a593Smuzhiyun static void smi_i2c0_setsda(void *data, int state)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct smi_dev *dev = data;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
smi_i2c0_setscl(void * data,int state)129*4882a593Smuzhiyun static void smi_i2c0_setscl(void *data, int state)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun struct smi_dev *dev = data;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
smi_i2c0_getsda(void * data)136*4882a593Smuzhiyun static int smi_i2c0_getsda(void *data)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct smi_dev *dev = data;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return smi_i2c_getsda(dev, I2C_A_SW_CTL);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
smi_i2c0_getscl(void * data)143*4882a593Smuzhiyun static int smi_i2c0_getscl(void *data)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun struct smi_dev *dev = data;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return smi_i2c_getscl(dev, I2C_A_SW_CTL);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun /* i2c 1.*/
smi_i2c1_setsda(void * data,int state)150*4882a593Smuzhiyun static void smi_i2c1_setsda(void *data, int state)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct smi_dev *dev = data;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
smi_i2c1_setscl(void * data,int state)157*4882a593Smuzhiyun static void smi_i2c1_setscl(void *data, int state)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct smi_dev *dev = data;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
smi_i2c1_getsda(void * data)164*4882a593Smuzhiyun static int smi_i2c1_getsda(void *data)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct smi_dev *dev = data;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return smi_i2c_getsda(dev, I2C_B_SW_CTL);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
smi_i2c1_getscl(void * data)171*4882a593Smuzhiyun static int smi_i2c1_getscl(void *data)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct smi_dev *dev = data;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return smi_i2c_getscl(dev, I2C_B_SW_CTL);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
smi_i2c_init(struct smi_dev * dev)178*4882a593Smuzhiyun static int smi_i2c_init(struct smi_dev *dev)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun int ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* i2c bus 0 */
183*4882a593Smuzhiyun smi_i2c_cfg(dev, I2C_A_SW_CTL);
184*4882a593Smuzhiyun i2c_set_adapdata(&dev->i2c_bus[0], dev);
185*4882a593Smuzhiyun strscpy(dev->i2c_bus[0].name, "SMI-I2C0", sizeof(dev->i2c_bus[0].name));
186*4882a593Smuzhiyun dev->i2c_bus[0].owner = THIS_MODULE;
187*4882a593Smuzhiyun dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
188*4882a593Smuzhiyun dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
189*4882a593Smuzhiyun dev->i2c_bit[0].data = dev;
190*4882a593Smuzhiyun dev->i2c_bit[0].setsda = smi_i2c0_setsda;
191*4882a593Smuzhiyun dev->i2c_bit[0].setscl = smi_i2c0_setscl;
192*4882a593Smuzhiyun dev->i2c_bit[0].getsda = smi_i2c0_getsda;
193*4882a593Smuzhiyun dev->i2c_bit[0].getscl = smi_i2c0_getscl;
194*4882a593Smuzhiyun dev->i2c_bit[0].udelay = 12;
195*4882a593Smuzhiyun dev->i2c_bit[0].timeout = 10;
196*4882a593Smuzhiyun /* Raise SCL and SDA */
197*4882a593Smuzhiyun smi_i2c0_setsda(dev, 1);
198*4882a593Smuzhiyun smi_i2c0_setscl(dev, 1);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
201*4882a593Smuzhiyun if (ret < 0)
202*4882a593Smuzhiyun return ret;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* i2c bus 1 */
205*4882a593Smuzhiyun smi_i2c_cfg(dev, I2C_B_SW_CTL);
206*4882a593Smuzhiyun i2c_set_adapdata(&dev->i2c_bus[1], dev);
207*4882a593Smuzhiyun strscpy(dev->i2c_bus[1].name, "SMI-I2C1", sizeof(dev->i2c_bus[1].name));
208*4882a593Smuzhiyun dev->i2c_bus[1].owner = THIS_MODULE;
209*4882a593Smuzhiyun dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
210*4882a593Smuzhiyun dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
211*4882a593Smuzhiyun dev->i2c_bit[1].data = dev;
212*4882a593Smuzhiyun dev->i2c_bit[1].setsda = smi_i2c1_setsda;
213*4882a593Smuzhiyun dev->i2c_bit[1].setscl = smi_i2c1_setscl;
214*4882a593Smuzhiyun dev->i2c_bit[1].getsda = smi_i2c1_getsda;
215*4882a593Smuzhiyun dev->i2c_bit[1].getscl = smi_i2c1_getscl;
216*4882a593Smuzhiyun dev->i2c_bit[1].udelay = 12;
217*4882a593Smuzhiyun dev->i2c_bit[1].timeout = 10;
218*4882a593Smuzhiyun /* Raise SCL and SDA */
219*4882a593Smuzhiyun smi_i2c1_setsda(dev, 1);
220*4882a593Smuzhiyun smi_i2c1_setscl(dev, 1);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
223*4882a593Smuzhiyun if (ret < 0)
224*4882a593Smuzhiyun i2c_del_adapter(&dev->i2c_bus[0]);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun return ret;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
smi_i2c_exit(struct smi_dev * dev)229*4882a593Smuzhiyun static void smi_i2c_exit(struct smi_dev *dev)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun i2c_del_adapter(&dev->i2c_bus[0]);
232*4882a593Smuzhiyun i2c_del_adapter(&dev->i2c_bus[1]);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
smi_read_eeprom(struct i2c_adapter * i2c,u16 reg,u8 * data,u16 size)235*4882a593Smuzhiyun static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun int ret;
238*4882a593Smuzhiyun u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun struct i2c_msg msg[] = {
241*4882a593Smuzhiyun { .addr = 0x50, .flags = 0,
242*4882a593Smuzhiyun .buf = b0, .len = 2 },
243*4882a593Smuzhiyun { .addr = 0x50, .flags = I2C_M_RD,
244*4882a593Smuzhiyun .buf = data, .len = size }
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun ret = i2c_transfer(i2c, msg, 2);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (ret != 2) {
250*4882a593Smuzhiyun dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
251*4882a593Smuzhiyun __func__, reg, ret);
252*4882a593Smuzhiyun return ret;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /* ts port interrupt operations */
smi_port_disableInterrupt(struct smi_port * port)258*4882a593Smuzhiyun static void smi_port_disableInterrupt(struct smi_port *port)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun smi_write(MSI_INT_ENA_CLR,
263*4882a593Smuzhiyun (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
smi_port_enableInterrupt(struct smi_port * port)266*4882a593Smuzhiyun static void smi_port_enableInterrupt(struct smi_port *port)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun smi_write(MSI_INT_ENA_SET,
271*4882a593Smuzhiyun (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
smi_port_clearInterrupt(struct smi_port * port)274*4882a593Smuzhiyun static void smi_port_clearInterrupt(struct smi_port *port)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun smi_write(MSI_INT_STATUS_CLR,
279*4882a593Smuzhiyun (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* tasklet handler: DMA data to dmx.*/
smi_dma_xfer(struct tasklet_struct * t)283*4882a593Smuzhiyun static void smi_dma_xfer(struct tasklet_struct *t)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun struct smi_port *port = from_tasklet(port, t, tasklet);
286*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
287*4882a593Smuzhiyun u32 intr_status, finishedData, dmaManagement;
288*4882a593Smuzhiyun u8 dmaChan0State, dmaChan1State;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun intr_status = port->_int_status;
291*4882a593Smuzhiyun dmaManagement = smi_read(port->DMA_MANAGEMENT);
292*4882a593Smuzhiyun dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
293*4882a593Smuzhiyun dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* CH-0 DMA interrupt.*/
296*4882a593Smuzhiyun if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
297*4882a593Smuzhiyun dev_dbg(&dev->pci_dev->dev,
298*4882a593Smuzhiyun "Port[%d]-DMA CH0 engine complete successful !\n",
299*4882a593Smuzhiyun port->idx);
300*4882a593Smuzhiyun finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
301*4882a593Smuzhiyun finishedData &= 0x003FFFFF;
302*4882a593Smuzhiyun /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
303*4882a593Smuzhiyun * indicate dma total transfer length and
304*4882a593Smuzhiyun * zero of [21:0] indicate dma total transfer length
305*4882a593Smuzhiyun * equal to 0x400000 (4MB)*/
306*4882a593Smuzhiyun if (finishedData == 0)
307*4882a593Smuzhiyun finishedData = 0x00400000;
308*4882a593Smuzhiyun if (finishedData != SMI_TS_DMA_BUF_SIZE) {
309*4882a593Smuzhiyun dev_dbg(&dev->pci_dev->dev,
310*4882a593Smuzhiyun "DMA CH0 engine complete length mismatched, finish data=%d !\n",
311*4882a593Smuzhiyun finishedData);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun dvb_dmx_swfilter_packets(&port->demux,
314*4882a593Smuzhiyun port->cpu_addr[0], (finishedData / 188));
315*4882a593Smuzhiyun /*dvb_dmx_swfilter(&port->demux,
316*4882a593Smuzhiyun port->cpu_addr[0], finishedData);*/
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun /* CH-1 DMA interrupt.*/
319*4882a593Smuzhiyun if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
320*4882a593Smuzhiyun dev_dbg(&dev->pci_dev->dev,
321*4882a593Smuzhiyun "Port[%d]-DMA CH1 engine complete successful !\n",
322*4882a593Smuzhiyun port->idx);
323*4882a593Smuzhiyun finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
324*4882a593Smuzhiyun finishedData &= 0x003FFFFF;
325*4882a593Smuzhiyun /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
326*4882a593Smuzhiyun * indicate dma total transfer length and
327*4882a593Smuzhiyun * zero of [21:0] indicate dma total transfer length
328*4882a593Smuzhiyun * equal to 0x400000 (4MB)*/
329*4882a593Smuzhiyun if (finishedData == 0)
330*4882a593Smuzhiyun finishedData = 0x00400000;
331*4882a593Smuzhiyun if (finishedData != SMI_TS_DMA_BUF_SIZE) {
332*4882a593Smuzhiyun dev_dbg(&dev->pci_dev->dev,
333*4882a593Smuzhiyun "DMA CH1 engine complete length mismatched, finish data=%d !\n",
334*4882a593Smuzhiyun finishedData);
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun dvb_dmx_swfilter_packets(&port->demux,
337*4882a593Smuzhiyun port->cpu_addr[1], (finishedData / 188));
338*4882a593Smuzhiyun /*dvb_dmx_swfilter(&port->demux,
339*4882a593Smuzhiyun port->cpu_addr[1], finishedData);*/
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun /* restart DMA.*/
342*4882a593Smuzhiyun if (intr_status & port->_dmaInterruptCH0)
343*4882a593Smuzhiyun dmaManagement |= 0x00000002;
344*4882a593Smuzhiyun if (intr_status & port->_dmaInterruptCH1)
345*4882a593Smuzhiyun dmaManagement |= 0x00020000;
346*4882a593Smuzhiyun smi_write(port->DMA_MANAGEMENT, dmaManagement);
347*4882a593Smuzhiyun /* Re-enable interrupts */
348*4882a593Smuzhiyun smi_port_enableInterrupt(port);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
smi_port_dma_free(struct smi_port * port)351*4882a593Smuzhiyun static void smi_port_dma_free(struct smi_port *port)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun if (port->cpu_addr[0]) {
354*4882a593Smuzhiyun pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
355*4882a593Smuzhiyun port->cpu_addr[0], port->dma_addr[0]);
356*4882a593Smuzhiyun port->cpu_addr[0] = NULL;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun if (port->cpu_addr[1]) {
359*4882a593Smuzhiyun pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
360*4882a593Smuzhiyun port->cpu_addr[1], port->dma_addr[1]);
361*4882a593Smuzhiyun port->cpu_addr[1] = NULL;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
smi_port_init(struct smi_port * port,int dmaChanUsed)365*4882a593Smuzhiyun static int smi_port_init(struct smi_port *port, int dmaChanUsed)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun dev_dbg(&port->dev->pci_dev->dev,
368*4882a593Smuzhiyun "%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
369*4882a593Smuzhiyun port->enable = 0;
370*4882a593Smuzhiyun if (port->idx == 0) {
371*4882a593Smuzhiyun /* Port A */
372*4882a593Smuzhiyun port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
373*4882a593Smuzhiyun port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
376*4882a593Smuzhiyun port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
377*4882a593Smuzhiyun port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
378*4882a593Smuzhiyun port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
379*4882a593Smuzhiyun port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
380*4882a593Smuzhiyun port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
381*4882a593Smuzhiyun port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
382*4882a593Smuzhiyun port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
383*4882a593Smuzhiyun port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
384*4882a593Smuzhiyun } else {
385*4882a593Smuzhiyun /* Port B */
386*4882a593Smuzhiyun port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
387*4882a593Smuzhiyun port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
390*4882a593Smuzhiyun port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
391*4882a593Smuzhiyun port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
392*4882a593Smuzhiyun port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
393*4882a593Smuzhiyun port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
394*4882a593Smuzhiyun port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
395*4882a593Smuzhiyun port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
396*4882a593Smuzhiyun port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
397*4882a593Smuzhiyun port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun if (port->_dmaInterruptCH0) {
401*4882a593Smuzhiyun port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev,
402*4882a593Smuzhiyun SMI_TS_DMA_BUF_SIZE,
403*4882a593Smuzhiyun &port->dma_addr[0]);
404*4882a593Smuzhiyun if (!port->cpu_addr[0]) {
405*4882a593Smuzhiyun dev_err(&port->dev->pci_dev->dev,
406*4882a593Smuzhiyun "Port[%d] DMA CH0 memory allocation failed!\n",
407*4882a593Smuzhiyun port->idx);
408*4882a593Smuzhiyun goto err;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (port->_dmaInterruptCH1) {
413*4882a593Smuzhiyun port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev,
414*4882a593Smuzhiyun SMI_TS_DMA_BUF_SIZE,
415*4882a593Smuzhiyun &port->dma_addr[1]);
416*4882a593Smuzhiyun if (!port->cpu_addr[1]) {
417*4882a593Smuzhiyun dev_err(&port->dev->pci_dev->dev,
418*4882a593Smuzhiyun "Port[%d] DMA CH1 memory allocation failed!\n",
419*4882a593Smuzhiyun port->idx);
420*4882a593Smuzhiyun goto err;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun smi_port_disableInterrupt(port);
425*4882a593Smuzhiyun tasklet_setup(&port->tasklet, smi_dma_xfer);
426*4882a593Smuzhiyun tasklet_disable(&port->tasklet);
427*4882a593Smuzhiyun port->enable = 1;
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun err:
430*4882a593Smuzhiyun smi_port_dma_free(port);
431*4882a593Smuzhiyun return -ENOMEM;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
smi_port_exit(struct smi_port * port)434*4882a593Smuzhiyun static void smi_port_exit(struct smi_port *port)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun smi_port_disableInterrupt(port);
437*4882a593Smuzhiyun tasklet_kill(&port->tasklet);
438*4882a593Smuzhiyun smi_port_dma_free(port);
439*4882a593Smuzhiyun port->enable = 0;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
smi_port_irq(struct smi_port * port,u32 int_status)442*4882a593Smuzhiyun static int smi_port_irq(struct smi_port *port, u32 int_status)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
445*4882a593Smuzhiyun int handled = 0;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun if (int_status & port_req_irq) {
448*4882a593Smuzhiyun smi_port_disableInterrupt(port);
449*4882a593Smuzhiyun port->_int_status = int_status;
450*4882a593Smuzhiyun smi_port_clearInterrupt(port);
451*4882a593Smuzhiyun tasklet_schedule(&port->tasklet);
452*4882a593Smuzhiyun handled = 1;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun return handled;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
smi_irq_handler(int irq,void * dev_id)457*4882a593Smuzhiyun static irqreturn_t smi_irq_handler(int irq, void *dev_id)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun struct smi_dev *dev = dev_id;
460*4882a593Smuzhiyun struct smi_port *port0 = &dev->ts_port[0];
461*4882a593Smuzhiyun struct smi_port *port1 = &dev->ts_port[1];
462*4882a593Smuzhiyun struct smi_rc *ir = &dev->ir;
463*4882a593Smuzhiyun int handled = 0;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun u32 intr_status = smi_read(MSI_INT_STATUS);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* ts0 interrupt.*/
468*4882a593Smuzhiyun if (dev->info->ts_0)
469*4882a593Smuzhiyun handled += smi_port_irq(port0, intr_status);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* ts1 interrupt.*/
472*4882a593Smuzhiyun if (dev->info->ts_1)
473*4882a593Smuzhiyun handled += smi_port_irq(port1, intr_status);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* ir interrupt.*/
476*4882a593Smuzhiyun handled += smi_ir_irq(ir, intr_status);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun return IRQ_RETVAL(handled);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
smi_add_i2c_client(struct i2c_adapter * adapter,struct i2c_board_info * info)481*4882a593Smuzhiyun static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
482*4882a593Smuzhiyun struct i2c_board_info *info)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun struct i2c_client *client;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun request_module(info->type);
487*4882a593Smuzhiyun client = i2c_new_client_device(adapter, info);
488*4882a593Smuzhiyun if (!i2c_client_has_driver(client))
489*4882a593Smuzhiyun goto err_add_i2c_client;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun if (!try_module_get(client->dev.driver->owner)) {
492*4882a593Smuzhiyun i2c_unregister_device(client);
493*4882a593Smuzhiyun goto err_add_i2c_client;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun return client;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun err_add_i2c_client:
498*4882a593Smuzhiyun client = NULL;
499*4882a593Smuzhiyun return client;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
smi_del_i2c_client(struct i2c_client * client)502*4882a593Smuzhiyun static void smi_del_i2c_client(struct i2c_client *client)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun module_put(client->dev.driver->owner);
505*4882a593Smuzhiyun i2c_unregister_device(client);
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
509*4882a593Smuzhiyun .i2c_addr = 0x68,
510*4882a593Smuzhiyun .clock = 27000000,
511*4882a593Smuzhiyun .i2c_wr_max = 33,
512*4882a593Smuzhiyun .clock_out = 0,
513*4882a593Smuzhiyun .ts_mode = M88DS3103_TS_PARALLEL,
514*4882a593Smuzhiyun .ts_clk = 16000,
515*4882a593Smuzhiyun .ts_clk_pol = 1,
516*4882a593Smuzhiyun .agc = 0x99,
517*4882a593Smuzhiyun .lnb_hv_pol = 0,
518*4882a593Smuzhiyun .lnb_en_pol = 1,
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun
smi_dvbsky_m88ds3103_fe_attach(struct smi_port * port)521*4882a593Smuzhiyun static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun int ret = 0;
524*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
525*4882a593Smuzhiyun struct i2c_adapter *i2c;
526*4882a593Smuzhiyun /* tuner I2C module */
527*4882a593Smuzhiyun struct i2c_adapter *tuner_i2c_adapter;
528*4882a593Smuzhiyun struct i2c_client *tuner_client;
529*4882a593Smuzhiyun struct i2c_board_info tuner_info;
530*4882a593Smuzhiyun struct ts2020_config ts2020_config = {};
531*4882a593Smuzhiyun memset(&tuner_info, 0, sizeof(struct i2c_board_info));
532*4882a593Smuzhiyun i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* attach demod */
535*4882a593Smuzhiyun port->fe = dvb_attach(m88ds3103_attach,
536*4882a593Smuzhiyun &smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
537*4882a593Smuzhiyun if (!port->fe) {
538*4882a593Smuzhiyun ret = -ENODEV;
539*4882a593Smuzhiyun return ret;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun /* attach tuner */
542*4882a593Smuzhiyun ts2020_config.fe = port->fe;
543*4882a593Smuzhiyun strscpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
544*4882a593Smuzhiyun tuner_info.addr = 0x60;
545*4882a593Smuzhiyun tuner_info.platform_data = &ts2020_config;
546*4882a593Smuzhiyun tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
547*4882a593Smuzhiyun if (!tuner_client) {
548*4882a593Smuzhiyun ret = -ENODEV;
549*4882a593Smuzhiyun goto err_tuner_i2c_device;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* delegate signal strength measurement to tuner */
553*4882a593Smuzhiyun port->fe->ops.read_signal_strength =
554*4882a593Smuzhiyun port->fe->ops.tuner_ops.get_rf_strength;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun port->i2c_client_tuner = tuner_client;
557*4882a593Smuzhiyun return ret;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun err_tuner_i2c_device:
560*4882a593Smuzhiyun dvb_frontend_detach(port->fe);
561*4882a593Smuzhiyun return ret;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
565*4882a593Smuzhiyun .i2c_addr = 0x69,
566*4882a593Smuzhiyun .clock = 27000000,
567*4882a593Smuzhiyun .i2c_wr_max = 33,
568*4882a593Smuzhiyun .ts_mode = M88DS3103_TS_PARALLEL,
569*4882a593Smuzhiyun .ts_clk = 16000,
570*4882a593Smuzhiyun .ts_clk_pol = 1,
571*4882a593Smuzhiyun .agc = 0x99,
572*4882a593Smuzhiyun .lnb_hv_pol = 0,
573*4882a593Smuzhiyun .lnb_en_pol = 1,
574*4882a593Smuzhiyun };
575*4882a593Smuzhiyun
smi_dvbsky_m88rs6000_fe_attach(struct smi_port * port)576*4882a593Smuzhiyun static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun int ret = 0;
579*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
580*4882a593Smuzhiyun struct i2c_adapter *i2c;
581*4882a593Smuzhiyun /* tuner I2C module */
582*4882a593Smuzhiyun struct i2c_adapter *tuner_i2c_adapter;
583*4882a593Smuzhiyun struct i2c_client *tuner_client;
584*4882a593Smuzhiyun struct i2c_board_info tuner_info;
585*4882a593Smuzhiyun struct m88rs6000t_config m88rs6000t_config;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun memset(&tuner_info, 0, sizeof(struct i2c_board_info));
588*4882a593Smuzhiyun i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* attach demod */
591*4882a593Smuzhiyun port->fe = dvb_attach(m88ds3103_attach,
592*4882a593Smuzhiyun &smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
593*4882a593Smuzhiyun if (!port->fe) {
594*4882a593Smuzhiyun ret = -ENODEV;
595*4882a593Smuzhiyun return ret;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun /* attach tuner */
598*4882a593Smuzhiyun m88rs6000t_config.fe = port->fe;
599*4882a593Smuzhiyun strscpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
600*4882a593Smuzhiyun tuner_info.addr = 0x21;
601*4882a593Smuzhiyun tuner_info.platform_data = &m88rs6000t_config;
602*4882a593Smuzhiyun tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
603*4882a593Smuzhiyun if (!tuner_client) {
604*4882a593Smuzhiyun ret = -ENODEV;
605*4882a593Smuzhiyun goto err_tuner_i2c_device;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun /* delegate signal strength measurement to tuner */
609*4882a593Smuzhiyun port->fe->ops.read_signal_strength =
610*4882a593Smuzhiyun port->fe->ops.tuner_ops.get_rf_strength;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun port->i2c_client_tuner = tuner_client;
613*4882a593Smuzhiyun return ret;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun err_tuner_i2c_device:
616*4882a593Smuzhiyun dvb_frontend_detach(port->fe);
617*4882a593Smuzhiyun return ret;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
smi_dvbsky_sit2_fe_attach(struct smi_port * port)620*4882a593Smuzhiyun static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun int ret = 0;
623*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
624*4882a593Smuzhiyun struct i2c_adapter *i2c;
625*4882a593Smuzhiyun struct i2c_adapter *tuner_i2c_adapter;
626*4882a593Smuzhiyun struct i2c_client *client_tuner, *client_demod;
627*4882a593Smuzhiyun struct i2c_board_info client_info;
628*4882a593Smuzhiyun struct si2168_config si2168_config;
629*4882a593Smuzhiyun struct si2157_config si2157_config;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun /* select i2c bus */
632*4882a593Smuzhiyun i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun /* attach demod */
635*4882a593Smuzhiyun memset(&si2168_config, 0, sizeof(si2168_config));
636*4882a593Smuzhiyun si2168_config.i2c_adapter = &tuner_i2c_adapter;
637*4882a593Smuzhiyun si2168_config.fe = &port->fe;
638*4882a593Smuzhiyun si2168_config.ts_mode = SI2168_TS_PARALLEL;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun memset(&client_info, 0, sizeof(struct i2c_board_info));
641*4882a593Smuzhiyun strscpy(client_info.type, "si2168", I2C_NAME_SIZE);
642*4882a593Smuzhiyun client_info.addr = 0x64;
643*4882a593Smuzhiyun client_info.platform_data = &si2168_config;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun client_demod = smi_add_i2c_client(i2c, &client_info);
646*4882a593Smuzhiyun if (!client_demod) {
647*4882a593Smuzhiyun ret = -ENODEV;
648*4882a593Smuzhiyun return ret;
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun port->i2c_client_demod = client_demod;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* attach tuner */
653*4882a593Smuzhiyun memset(&si2157_config, 0, sizeof(si2157_config));
654*4882a593Smuzhiyun si2157_config.fe = port->fe;
655*4882a593Smuzhiyun si2157_config.if_port = 1;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun memset(&client_info, 0, sizeof(struct i2c_board_info));
658*4882a593Smuzhiyun strscpy(client_info.type, "si2157", I2C_NAME_SIZE);
659*4882a593Smuzhiyun client_info.addr = 0x60;
660*4882a593Smuzhiyun client_info.platform_data = &si2157_config;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
663*4882a593Smuzhiyun if (!client_tuner) {
664*4882a593Smuzhiyun smi_del_i2c_client(port->i2c_client_demod);
665*4882a593Smuzhiyun port->i2c_client_demod = NULL;
666*4882a593Smuzhiyun ret = -ENODEV;
667*4882a593Smuzhiyun return ret;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun port->i2c_client_tuner = client_tuner;
670*4882a593Smuzhiyun return ret;
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
smi_fe_init(struct smi_port * port)673*4882a593Smuzhiyun static int smi_fe_init(struct smi_port *port)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun int ret = 0;
676*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
677*4882a593Smuzhiyun struct dvb_adapter *adap = &port->dvb_adapter;
678*4882a593Smuzhiyun u8 mac_ee[16];
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun dev_dbg(&port->dev->pci_dev->dev,
681*4882a593Smuzhiyun "%s: port %d, fe_type = %d\n",
682*4882a593Smuzhiyun __func__, port->idx, port->fe_type);
683*4882a593Smuzhiyun switch (port->fe_type) {
684*4882a593Smuzhiyun case DVBSKY_FE_M88DS3103:
685*4882a593Smuzhiyun ret = smi_dvbsky_m88ds3103_fe_attach(port);
686*4882a593Smuzhiyun break;
687*4882a593Smuzhiyun case DVBSKY_FE_M88RS6000:
688*4882a593Smuzhiyun ret = smi_dvbsky_m88rs6000_fe_attach(port);
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun case DVBSKY_FE_SIT2:
691*4882a593Smuzhiyun ret = smi_dvbsky_sit2_fe_attach(port);
692*4882a593Smuzhiyun break;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun if (ret < 0)
695*4882a593Smuzhiyun return ret;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun /* register dvb frontend */
698*4882a593Smuzhiyun ret = dvb_register_frontend(adap, port->fe);
699*4882a593Smuzhiyun if (ret < 0) {
700*4882a593Smuzhiyun if (port->i2c_client_tuner)
701*4882a593Smuzhiyun smi_del_i2c_client(port->i2c_client_tuner);
702*4882a593Smuzhiyun if (port->i2c_client_demod)
703*4882a593Smuzhiyun smi_del_i2c_client(port->i2c_client_demod);
704*4882a593Smuzhiyun dvb_frontend_detach(port->fe);
705*4882a593Smuzhiyun return ret;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun /* init MAC.*/
708*4882a593Smuzhiyun ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
709*4882a593Smuzhiyun dev_info(&port->dev->pci_dev->dev,
710*4882a593Smuzhiyun "%s port %d MAC: %pM\n", dev->info->name,
711*4882a593Smuzhiyun port->idx, mac_ee + (port->idx)*8);
712*4882a593Smuzhiyun memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
713*4882a593Smuzhiyun return ret;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
smi_fe_exit(struct smi_port * port)716*4882a593Smuzhiyun static void smi_fe_exit(struct smi_port *port)
717*4882a593Smuzhiyun {
718*4882a593Smuzhiyun dvb_unregister_frontend(port->fe);
719*4882a593Smuzhiyun /* remove I2C demod and tuner */
720*4882a593Smuzhiyun if (port->i2c_client_tuner)
721*4882a593Smuzhiyun smi_del_i2c_client(port->i2c_client_tuner);
722*4882a593Smuzhiyun if (port->i2c_client_demod)
723*4882a593Smuzhiyun smi_del_i2c_client(port->i2c_client_demod);
724*4882a593Smuzhiyun dvb_frontend_detach(port->fe);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
my_dvb_dmx_ts_card_init(struct dvb_demux * dvbdemux,char * id,int (* start_feed)(struct dvb_demux_feed *),int (* stop_feed)(struct dvb_demux_feed *),void * priv)727*4882a593Smuzhiyun static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
728*4882a593Smuzhiyun int (*start_feed)(struct dvb_demux_feed *),
729*4882a593Smuzhiyun int (*stop_feed)(struct dvb_demux_feed *),
730*4882a593Smuzhiyun void *priv)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun dvbdemux->priv = priv;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun dvbdemux->filternum = 256;
735*4882a593Smuzhiyun dvbdemux->feednum = 256;
736*4882a593Smuzhiyun dvbdemux->start_feed = start_feed;
737*4882a593Smuzhiyun dvbdemux->stop_feed = stop_feed;
738*4882a593Smuzhiyun dvbdemux->write_to_decoder = NULL;
739*4882a593Smuzhiyun dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
740*4882a593Smuzhiyun DMX_SECTION_FILTERING |
741*4882a593Smuzhiyun DMX_MEMORY_BASED_FILTERING);
742*4882a593Smuzhiyun return dvb_dmx_init(dvbdemux);
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
my_dvb_dmxdev_ts_card_init(struct dmxdev * dmxdev,struct dvb_demux * dvbdemux,struct dmx_frontend * hw_frontend,struct dmx_frontend * mem_frontend,struct dvb_adapter * dvb_adapter)745*4882a593Smuzhiyun static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
746*4882a593Smuzhiyun struct dvb_demux *dvbdemux,
747*4882a593Smuzhiyun struct dmx_frontend *hw_frontend,
748*4882a593Smuzhiyun struct dmx_frontend *mem_frontend,
749*4882a593Smuzhiyun struct dvb_adapter *dvb_adapter)
750*4882a593Smuzhiyun {
751*4882a593Smuzhiyun int ret;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun dmxdev->filternum = 256;
754*4882a593Smuzhiyun dmxdev->demux = &dvbdemux->dmx;
755*4882a593Smuzhiyun dmxdev->capabilities = 0;
756*4882a593Smuzhiyun ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
757*4882a593Smuzhiyun if (ret < 0)
758*4882a593Smuzhiyun return ret;
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun hw_frontend->source = DMX_FRONTEND_0;
761*4882a593Smuzhiyun dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
762*4882a593Smuzhiyun mem_frontend->source = DMX_MEMORY_FE;
763*4882a593Smuzhiyun dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
764*4882a593Smuzhiyun return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
smi_config_DMA(struct smi_port * port)767*4882a593Smuzhiyun static u32 smi_config_DMA(struct smi_port *port)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
770*4882a593Smuzhiyun u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
771*4882a593Smuzhiyun u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
772*4882a593Smuzhiyun u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
773*4882a593Smuzhiyun u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
774*4882a593Smuzhiyun u64 mem;
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun dmaManagement = smi_read(port->DMA_MANAGEMENT);
777*4882a593Smuzhiyun /* Setup Channel-0 */
778*4882a593Smuzhiyun if (port->_dmaInterruptCH0) {
779*4882a593Smuzhiyun totalLength = SMI_TS_DMA_BUF_SIZE;
780*4882a593Smuzhiyun mem = port->dma_addr[0];
781*4882a593Smuzhiyun dmaMemPtrLow = mem & 0xffffffff;
782*4882a593Smuzhiyun dmaMemPtrHi = mem >> 32;
783*4882a593Smuzhiyun dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
784*4882a593Smuzhiyun | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
785*4882a593Smuzhiyun dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
786*4882a593Smuzhiyun | (chanLatencyTimer << 8);
787*4882a593Smuzhiyun /* write DMA register, start DMA engine */
788*4882a593Smuzhiyun smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
789*4882a593Smuzhiyun smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
790*4882a593Smuzhiyun smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun /* Setup Channel-1 */
793*4882a593Smuzhiyun if (port->_dmaInterruptCH1) {
794*4882a593Smuzhiyun totalLength = SMI_TS_DMA_BUF_SIZE;
795*4882a593Smuzhiyun mem = port->dma_addr[1];
796*4882a593Smuzhiyun dmaMemPtrLow = mem & 0xffffffff;
797*4882a593Smuzhiyun dmaMemPtrHi = mem >> 32;
798*4882a593Smuzhiyun dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
799*4882a593Smuzhiyun | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
800*4882a593Smuzhiyun dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
801*4882a593Smuzhiyun | (chanLatencyTimer << 24);
802*4882a593Smuzhiyun /* write DMA register, start DMA engine */
803*4882a593Smuzhiyun smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
804*4882a593Smuzhiyun smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
805*4882a593Smuzhiyun smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun return dmaManagement;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
smi_start_feed(struct dvb_demux_feed * dvbdmxfeed)810*4882a593Smuzhiyun static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
811*4882a593Smuzhiyun {
812*4882a593Smuzhiyun struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
813*4882a593Smuzhiyun struct smi_port *port = dvbdmx->priv;
814*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
815*4882a593Smuzhiyun u32 dmaManagement;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun if (port->users++ == 0) {
818*4882a593Smuzhiyun dmaManagement = smi_config_DMA(port);
819*4882a593Smuzhiyun smi_port_clearInterrupt(port);
820*4882a593Smuzhiyun smi_port_enableInterrupt(port);
821*4882a593Smuzhiyun smi_write(port->DMA_MANAGEMENT, dmaManagement);
822*4882a593Smuzhiyun tasklet_enable(&port->tasklet);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun return port->users;
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun
smi_stop_feed(struct dvb_demux_feed * dvbdmxfeed)827*4882a593Smuzhiyun static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
830*4882a593Smuzhiyun struct smi_port *port = dvbdmx->priv;
831*4882a593Smuzhiyun struct smi_dev *dev = port->dev;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (--port->users)
834*4882a593Smuzhiyun return port->users;
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun tasklet_disable(&port->tasklet);
837*4882a593Smuzhiyun smi_port_disableInterrupt(port);
838*4882a593Smuzhiyun smi_clear(port->DMA_MANAGEMENT, 0x30003);
839*4882a593Smuzhiyun return 0;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
smi_dvb_init(struct smi_port * port)842*4882a593Smuzhiyun static int smi_dvb_init(struct smi_port *port)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun int ret;
845*4882a593Smuzhiyun struct dvb_adapter *adap = &port->dvb_adapter;
846*4882a593Smuzhiyun struct dvb_demux *dvbdemux = &port->demux;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun dev_dbg(&port->dev->pci_dev->dev,
849*4882a593Smuzhiyun "%s, port %d\n", __func__, port->idx);
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
852*4882a593Smuzhiyun &port->dev->pci_dev->dev,
853*4882a593Smuzhiyun adapter_nr);
854*4882a593Smuzhiyun if (ret < 0) {
855*4882a593Smuzhiyun dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
856*4882a593Smuzhiyun return ret;
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
859*4882a593Smuzhiyun smi_start_feed,
860*4882a593Smuzhiyun smi_stop_feed, port);
861*4882a593Smuzhiyun if (ret < 0)
862*4882a593Smuzhiyun goto err_del_dvb_register_adapter;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
865*4882a593Smuzhiyun &port->hw_frontend,
866*4882a593Smuzhiyun &port->mem_frontend, adap);
867*4882a593Smuzhiyun if (ret < 0)
868*4882a593Smuzhiyun goto err_del_dvb_dmx;
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
871*4882a593Smuzhiyun if (ret < 0)
872*4882a593Smuzhiyun goto err_del_dvb_dmxdev;
873*4882a593Smuzhiyun return 0;
874*4882a593Smuzhiyun err_del_dvb_dmxdev:
875*4882a593Smuzhiyun dvbdemux->dmx.close(&dvbdemux->dmx);
876*4882a593Smuzhiyun dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
877*4882a593Smuzhiyun dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
878*4882a593Smuzhiyun dvb_dmxdev_release(&port->dmxdev);
879*4882a593Smuzhiyun err_del_dvb_dmx:
880*4882a593Smuzhiyun dvb_dmx_release(&port->demux);
881*4882a593Smuzhiyun err_del_dvb_register_adapter:
882*4882a593Smuzhiyun dvb_unregister_adapter(&port->dvb_adapter);
883*4882a593Smuzhiyun return ret;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
smi_dvb_exit(struct smi_port * port)886*4882a593Smuzhiyun static void smi_dvb_exit(struct smi_port *port)
887*4882a593Smuzhiyun {
888*4882a593Smuzhiyun struct dvb_demux *dvbdemux = &port->demux;
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun dvb_net_release(&port->dvbnet);
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun dvbdemux->dmx.close(&dvbdemux->dmx);
893*4882a593Smuzhiyun dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
894*4882a593Smuzhiyun dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
895*4882a593Smuzhiyun dvb_dmxdev_release(&port->dmxdev);
896*4882a593Smuzhiyun dvb_dmx_release(&port->demux);
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun dvb_unregister_adapter(&port->dvb_adapter);
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
smi_port_attach(struct smi_dev * dev,struct smi_port * port,int index)901*4882a593Smuzhiyun static int smi_port_attach(struct smi_dev *dev,
902*4882a593Smuzhiyun struct smi_port *port, int index)
903*4882a593Smuzhiyun {
904*4882a593Smuzhiyun int ret, dmachs;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun port->dev = dev;
907*4882a593Smuzhiyun port->idx = index;
908*4882a593Smuzhiyun port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
909*4882a593Smuzhiyun dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
910*4882a593Smuzhiyun /* port init.*/
911*4882a593Smuzhiyun ret = smi_port_init(port, dmachs);
912*4882a593Smuzhiyun if (ret < 0)
913*4882a593Smuzhiyun return ret;
914*4882a593Smuzhiyun /* dvb init.*/
915*4882a593Smuzhiyun ret = smi_dvb_init(port);
916*4882a593Smuzhiyun if (ret < 0)
917*4882a593Smuzhiyun goto err_del_port_init;
918*4882a593Smuzhiyun /* fe init.*/
919*4882a593Smuzhiyun ret = smi_fe_init(port);
920*4882a593Smuzhiyun if (ret < 0)
921*4882a593Smuzhiyun goto err_del_dvb_init;
922*4882a593Smuzhiyun return 0;
923*4882a593Smuzhiyun err_del_dvb_init:
924*4882a593Smuzhiyun smi_dvb_exit(port);
925*4882a593Smuzhiyun err_del_port_init:
926*4882a593Smuzhiyun smi_port_exit(port);
927*4882a593Smuzhiyun return ret;
928*4882a593Smuzhiyun }
929*4882a593Smuzhiyun
smi_port_detach(struct smi_port * port)930*4882a593Smuzhiyun static void smi_port_detach(struct smi_port *port)
931*4882a593Smuzhiyun {
932*4882a593Smuzhiyun smi_fe_exit(port);
933*4882a593Smuzhiyun smi_dvb_exit(port);
934*4882a593Smuzhiyun smi_port_exit(port);
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
smi_probe(struct pci_dev * pdev,const struct pci_device_id * id)937*4882a593Smuzhiyun static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun struct smi_dev *dev;
940*4882a593Smuzhiyun int ret = -ENOMEM;
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun if (pci_enable_device(pdev) < 0)
943*4882a593Smuzhiyun return -ENODEV;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
946*4882a593Smuzhiyun if (!dev) {
947*4882a593Smuzhiyun ret = -ENOMEM;
948*4882a593Smuzhiyun goto err_pci_disable_device;
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun dev->pci_dev = pdev;
952*4882a593Smuzhiyun pci_set_drvdata(pdev, dev);
953*4882a593Smuzhiyun dev->info = (struct smi_cfg_info *) id->driver_data;
954*4882a593Smuzhiyun dev_info(&dev->pci_dev->dev,
955*4882a593Smuzhiyun "card detected: %s\n", dev->info->name);
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun dev->nr = dev->info->type;
958*4882a593Smuzhiyun dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
959*4882a593Smuzhiyun pci_resource_len(dev->pci_dev, 0));
960*4882a593Smuzhiyun if (!dev->lmmio) {
961*4882a593Smuzhiyun ret = -ENOMEM;
962*4882a593Smuzhiyun goto err_kfree;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun /* should we set to 32bit DMA? */
966*4882a593Smuzhiyun ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
967*4882a593Smuzhiyun if (ret < 0)
968*4882a593Smuzhiyun goto err_pci_iounmap;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun pci_set_master(pdev);
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun ret = smi_hw_init(dev);
973*4882a593Smuzhiyun if (ret < 0)
974*4882a593Smuzhiyun goto err_pci_iounmap;
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun ret = smi_i2c_init(dev);
977*4882a593Smuzhiyun if (ret < 0)
978*4882a593Smuzhiyun goto err_pci_iounmap;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun if (dev->info->ts_0) {
981*4882a593Smuzhiyun ret = smi_port_attach(dev, &dev->ts_port[0], 0);
982*4882a593Smuzhiyun if (ret < 0)
983*4882a593Smuzhiyun goto err_del_i2c_adaptor;
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun if (dev->info->ts_1) {
987*4882a593Smuzhiyun ret = smi_port_attach(dev, &dev->ts_port[1], 1);
988*4882a593Smuzhiyun if (ret < 0)
989*4882a593Smuzhiyun goto err_del_port0_attach;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun ret = smi_ir_init(dev);
993*4882a593Smuzhiyun if (ret < 0)
994*4882a593Smuzhiyun goto err_del_port1_attach;
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun #ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
997*4882a593Smuzhiyun if (pci_msi_enabled())
998*4882a593Smuzhiyun ret = pci_enable_msi(dev->pci_dev);
999*4882a593Smuzhiyun if (ret)
1000*4882a593Smuzhiyun dev_info(&dev->pci_dev->dev, "MSI not available.\n");
1001*4882a593Smuzhiyun #endif
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
1004*4882a593Smuzhiyun IRQF_SHARED, "SMI_PCIE", dev);
1005*4882a593Smuzhiyun if (ret < 0)
1006*4882a593Smuzhiyun goto err_del_ir;
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun smi_ir_start(&dev->ir);
1009*4882a593Smuzhiyun return 0;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun err_del_ir:
1012*4882a593Smuzhiyun smi_ir_exit(dev);
1013*4882a593Smuzhiyun err_del_port1_attach:
1014*4882a593Smuzhiyun if (dev->info->ts_1)
1015*4882a593Smuzhiyun smi_port_detach(&dev->ts_port[1]);
1016*4882a593Smuzhiyun err_del_port0_attach:
1017*4882a593Smuzhiyun if (dev->info->ts_0)
1018*4882a593Smuzhiyun smi_port_detach(&dev->ts_port[0]);
1019*4882a593Smuzhiyun err_del_i2c_adaptor:
1020*4882a593Smuzhiyun smi_i2c_exit(dev);
1021*4882a593Smuzhiyun err_pci_iounmap:
1022*4882a593Smuzhiyun iounmap(dev->lmmio);
1023*4882a593Smuzhiyun err_kfree:
1024*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
1025*4882a593Smuzhiyun kfree(dev);
1026*4882a593Smuzhiyun err_pci_disable_device:
1027*4882a593Smuzhiyun pci_disable_device(pdev);
1028*4882a593Smuzhiyun return ret;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
smi_remove(struct pci_dev * pdev)1031*4882a593Smuzhiyun static void smi_remove(struct pci_dev *pdev)
1032*4882a593Smuzhiyun {
1033*4882a593Smuzhiyun struct smi_dev *dev = pci_get_drvdata(pdev);
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun smi_write(MSI_INT_ENA_CLR, ALL_INT);
1036*4882a593Smuzhiyun free_irq(dev->pci_dev->irq, dev);
1037*4882a593Smuzhiyun #ifdef CONFIG_PCI_MSI
1038*4882a593Smuzhiyun pci_disable_msi(dev->pci_dev);
1039*4882a593Smuzhiyun #endif
1040*4882a593Smuzhiyun if (dev->info->ts_1)
1041*4882a593Smuzhiyun smi_port_detach(&dev->ts_port[1]);
1042*4882a593Smuzhiyun if (dev->info->ts_0)
1043*4882a593Smuzhiyun smi_port_detach(&dev->ts_port[0]);
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun smi_ir_exit(dev);
1046*4882a593Smuzhiyun smi_i2c_exit(dev);
1047*4882a593Smuzhiyun iounmap(dev->lmmio);
1048*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
1049*4882a593Smuzhiyun pci_disable_device(pdev);
1050*4882a593Smuzhiyun kfree(dev);
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun /* DVBSky cards */
1054*4882a593Smuzhiyun static const struct smi_cfg_info dvbsky_s950_cfg = {
1055*4882a593Smuzhiyun .type = SMI_DVBSKY_S950,
1056*4882a593Smuzhiyun .name = "DVBSky S950 V3",
1057*4882a593Smuzhiyun .ts_0 = SMI_TS_NULL,
1058*4882a593Smuzhiyun .ts_1 = SMI_TS_DMA_BOTH,
1059*4882a593Smuzhiyun .fe_0 = DVBSKY_FE_NULL,
1060*4882a593Smuzhiyun .fe_1 = DVBSKY_FE_M88DS3103,
1061*4882a593Smuzhiyun .rc_map = RC_MAP_DVBSKY,
1062*4882a593Smuzhiyun };
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun static const struct smi_cfg_info dvbsky_s952_cfg = {
1065*4882a593Smuzhiyun .type = SMI_DVBSKY_S952,
1066*4882a593Smuzhiyun .name = "DVBSky S952 V3",
1067*4882a593Smuzhiyun .ts_0 = SMI_TS_DMA_BOTH,
1068*4882a593Smuzhiyun .ts_1 = SMI_TS_DMA_BOTH,
1069*4882a593Smuzhiyun .fe_0 = DVBSKY_FE_M88RS6000,
1070*4882a593Smuzhiyun .fe_1 = DVBSKY_FE_M88RS6000,
1071*4882a593Smuzhiyun .rc_map = RC_MAP_DVBSKY,
1072*4882a593Smuzhiyun };
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun static const struct smi_cfg_info dvbsky_t9580_cfg = {
1075*4882a593Smuzhiyun .type = SMI_DVBSKY_T9580,
1076*4882a593Smuzhiyun .name = "DVBSky T9580 V3",
1077*4882a593Smuzhiyun .ts_0 = SMI_TS_DMA_BOTH,
1078*4882a593Smuzhiyun .ts_1 = SMI_TS_DMA_BOTH,
1079*4882a593Smuzhiyun .fe_0 = DVBSKY_FE_SIT2,
1080*4882a593Smuzhiyun .fe_1 = DVBSKY_FE_M88DS3103,
1081*4882a593Smuzhiyun .rc_map = RC_MAP_DVBSKY,
1082*4882a593Smuzhiyun };
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun static const struct smi_cfg_info technotrend_s2_4200_cfg = {
1085*4882a593Smuzhiyun .type = SMI_TECHNOTREND_S2_4200,
1086*4882a593Smuzhiyun .name = "TechnoTrend TT-budget S2-4200 Twin",
1087*4882a593Smuzhiyun .ts_0 = SMI_TS_DMA_BOTH,
1088*4882a593Smuzhiyun .ts_1 = SMI_TS_DMA_BOTH,
1089*4882a593Smuzhiyun .fe_0 = DVBSKY_FE_M88RS6000,
1090*4882a593Smuzhiyun .fe_1 = DVBSKY_FE_M88RS6000,
1091*4882a593Smuzhiyun .rc_map = RC_MAP_TT_1500,
1092*4882a593Smuzhiyun };
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun /* PCI IDs */
1095*4882a593Smuzhiyun #define SMI_ID(_subvend, _subdev, _driverdata) { \
1096*4882a593Smuzhiyun .vendor = SMI_VID, .device = SMI_PID, \
1097*4882a593Smuzhiyun .subvendor = _subvend, .subdevice = _subdev, \
1098*4882a593Smuzhiyun .driver_data = (unsigned long)&_driverdata }
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun static const struct pci_device_id smi_id_table[] = {
1101*4882a593Smuzhiyun SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
1102*4882a593Smuzhiyun SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
1103*4882a593Smuzhiyun SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
1104*4882a593Smuzhiyun SMI_ID(0x13c2, 0x3016, technotrend_s2_4200_cfg),
1105*4882a593Smuzhiyun {0}
1106*4882a593Smuzhiyun };
1107*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, smi_id_table);
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun static struct pci_driver smipcie_driver = {
1110*4882a593Smuzhiyun .name = "SMI PCIe driver",
1111*4882a593Smuzhiyun .id_table = smi_id_table,
1112*4882a593Smuzhiyun .probe = smi_probe,
1113*4882a593Smuzhiyun .remove = smi_remove,
1114*4882a593Smuzhiyun };
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun module_pci_driver(smipcie_driver);
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun MODULE_AUTHOR("Max nibble <nibble.max@gmail.com>");
1119*4882a593Smuzhiyun MODULE_DESCRIPTION("SMI PCIe driver");
1120*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1121