1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * philips saa7134 registers 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* ------------------------------------------------------------------ */ 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * PCI ID's 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_PHILIPS_SAA7130 12*4882a593Smuzhiyun # define PCI_DEVICE_ID_PHILIPS_SAA7130 0x7130 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_PHILIPS_SAA7133 15*4882a593Smuzhiyun # define PCI_DEVICE_ID_PHILIPS_SAA7133 0x7133 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_PHILIPS_SAA7134 18*4882a593Smuzhiyun # define PCI_DEVICE_ID_PHILIPS_SAA7134 0x7134 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_PHILIPS_SAA7135 21*4882a593Smuzhiyun # define PCI_DEVICE_ID_PHILIPS_SAA7135 0x7135 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* ------------------------------------------------------------------ */ 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * registers -- 32 bit 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* DMA channels, n = 0 ... 6 */ 30*4882a593Smuzhiyun #define SAA7134_RS_BA1(n) ((0x200 >> 2) + 4*n) 31*4882a593Smuzhiyun #define SAA7134_RS_BA2(n) ((0x204 >> 2) + 4*n) 32*4882a593Smuzhiyun #define SAA7134_RS_PITCH(n) ((0x208 >> 2) + 4*n) 33*4882a593Smuzhiyun #define SAA7134_RS_CONTROL(n) ((0x20c >> 2) + 4*n) 34*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_WSWAP (0x01 << 25) 35*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BSWAP (0x01 << 24) 36*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_2 (0x01 << 21) 37*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_4 (0x02 << 21) 38*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_8 (0x03 << 21) 39*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_16 (0x04 << 21) 40*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_32 (0x05 << 21) 41*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_64 (0x06 << 21) 42*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_BURST_MAX (0x07 << 21) 43*4882a593Smuzhiyun #define SAA7134_RS_CONTROL_ME (0x01 << 20) 44*4882a593Smuzhiyun #define SAA7134_FIFO_SIZE (0x2a0 >> 2) 45*4882a593Smuzhiyun #define SAA7134_THRESHOULD (0x2a4 >> 2) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define SAA7133_NUM_SAMPLES (0x588 >> 2) 48*4882a593Smuzhiyun #define SAA7133_AUDIO_CHANNEL (0x58c >> 2) 49*4882a593Smuzhiyun #define SAA7133_AUDIO_FORMAT (0x58f >> 2) 50*4882a593Smuzhiyun #define SAA7133_DIGITAL_OUTPUT_SEL1 (0x46c >> 2) 51*4882a593Smuzhiyun #define SAA7133_DIGITAL_OUTPUT_SEL2 (0x470 >> 2) 52*4882a593Smuzhiyun #define SAA7133_DIGITAL_INPUT_XBAR1 (0x464 >> 2) 53*4882a593Smuzhiyun #define SAA7133_ANALOG_IO_SELECT (0x594 >> 2) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* main control */ 56*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL (0x2a8 >> 2) 57*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_VPLLE (1 << 15) 58*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_APLLE (1 << 14) 59*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_EXOSC (1 << 13) 60*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_EVFE1 (1 << 12) 61*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_EVFE2 (1 << 11) 62*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_ESFE (1 << 10) 63*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_EBADC (1 << 9) 64*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_EBDAC (1 << 8) 65*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE6 (1 << 6) 66*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE5 (1 << 5) 67*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE4 (1 << 4) 68*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE3 (1 << 3) 69*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE2 (1 << 2) 70*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE1 (1 << 1) 71*4882a593Smuzhiyun #define SAA7134_MAIN_CTRL_TE0 (1 << 0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* DMA status */ 74*4882a593Smuzhiyun #define SAA7134_DMA_STATUS (0x2ac >> 2) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* audio / video status */ 77*4882a593Smuzhiyun #define SAA7134_AV_STATUS (0x2c0 >> 2) 78*4882a593Smuzhiyun #define SAA7134_AV_STATUS_STEREO (1 << 17) 79*4882a593Smuzhiyun #define SAA7134_AV_STATUS_DUAL (1 << 16) 80*4882a593Smuzhiyun #define SAA7134_AV_STATUS_PILOT (1 << 15) 81*4882a593Smuzhiyun #define SAA7134_AV_STATUS_SMB (1 << 14) 82*4882a593Smuzhiyun #define SAA7134_AV_STATUS_DMB (1 << 13) 83*4882a593Smuzhiyun #define SAA7134_AV_STATUS_VDSP (1 << 12) 84*4882a593Smuzhiyun #define SAA7134_AV_STATUS_IIC_STATUS (3 << 10) 85*4882a593Smuzhiyun #define SAA7134_AV_STATUS_MVM (7 << 7) 86*4882a593Smuzhiyun #define SAA7134_AV_STATUS_FIDT (1 << 6) 87*4882a593Smuzhiyun #define SAA7134_AV_STATUS_INTL (1 << 5) 88*4882a593Smuzhiyun #define SAA7134_AV_STATUS_RDCAP (1 << 4) 89*4882a593Smuzhiyun #define SAA7134_AV_STATUS_PWR_ON (1 << 3) 90*4882a593Smuzhiyun #define SAA7134_AV_STATUS_LOAD_ERR (1 << 2) 91*4882a593Smuzhiyun #define SAA7134_AV_STATUS_TRIG_ERR (1 << 1) 92*4882a593Smuzhiyun #define SAA7134_AV_STATUS_CONF_ERR (1 << 0) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* interrupt */ 95*4882a593Smuzhiyun #define SAA7134_IRQ1 (0x2c4 >> 2) 96*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA3_1 (1 << 25) 97*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA3_0 (1 << 24) 98*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA2_3 (1 << 19) 99*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA2_2 (1 << 18) 100*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA2_1 (1 << 17) 101*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA2_0 (1 << 16) 102*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA1_3 (1 << 11) 103*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA1_2 (1 << 10) 104*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA1_1 (1 << 9) 105*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA1_0 (1 << 8) 106*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_7 (1 << 7) 107*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_6 (1 << 6) 108*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_5 (1 << 5) 109*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_4 (1 << 4) 110*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_3 (1 << 3) 111*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_2 (1 << 2) 112*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_1 (1 << 1) 113*4882a593Smuzhiyun #define SAA7134_IRQ1_INTE_RA0_0 (1 << 0) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define SAA7134_IRQ2 (0x2c8 >> 2) 116*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO23_N (1 << 17) /* negative edge */ 117*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO23_P (1 << 16) /* positive edge */ 118*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO22_N (1 << 15) /* negative edge */ 119*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO22_P (1 << 14) /* positive edge */ 120*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO18_N (1 << 13) /* negative edge */ 121*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO18_P (1 << 12) /* positive edge */ 122*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO16_N (1 << 11) /* negative edge */ 123*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_GPIO16_P (1 << 10) /* positive edge */ 124*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_SC2 (1 << 9) 125*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_SC1 (1 << 8) 126*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_SC0 (1 << 7) 127*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_DEC4 (1 << 6) 128*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_DEC3 (1 << 5) 129*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_DEC2 (1 << 4) 130*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_DEC1 (1 << 3) 131*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_DEC0 (1 << 2) 132*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_PE (1 << 1) 133*4882a593Smuzhiyun #define SAA7134_IRQ2_INTE_AR (1 << 0) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT (0x2cc >> 2) 136*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_GPIO23 (1 << 17) 137*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_GPIO22 (1 << 16) 138*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_GPIO18 (1 << 15) 139*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_GPIO16 (1 << 14) 140*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_LOAD_ERR (1 << 13) 141*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_CONF_ERR (1 << 12) 142*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_TRIG_ERR (1 << 11) 143*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_MMC (1 << 10) 144*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_FIDT (1 << 9) 145*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_INTL (1 << 8) 146*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_RDCAP (1 << 7) 147*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_PWR_ON (1 << 6) 148*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_PE (1 << 5) 149*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_AR (1 << 4) 150*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_DONE_RA3 (1 << 3) 151*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_DONE_RA2 (1 << 2) 152*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_DONE_RA1 (1 << 1) 153*4882a593Smuzhiyun #define SAA7134_IRQ_REPORT_DONE_RA0 (1 << 0) 154*4882a593Smuzhiyun #define SAA7134_IRQ_STATUS (0x2d0 >> 2) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* ------------------------------------------------------------------ */ 158*4882a593Smuzhiyun /* 159*4882a593Smuzhiyun * registers -- 8 bit 160*4882a593Smuzhiyun */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* video decoder */ 163*4882a593Smuzhiyun #define SAA7134_INCR_DELAY 0x101 164*4882a593Smuzhiyun #define SAA7134_ANALOG_IN_CTRL1 0x102 165*4882a593Smuzhiyun #define SAA7134_ANALOG_IN_CTRL2 0x103 166*4882a593Smuzhiyun #define SAA7134_ANALOG_IN_CTRL3 0x104 167*4882a593Smuzhiyun #define SAA7134_ANALOG_IN_CTRL4 0x105 168*4882a593Smuzhiyun #define SAA7134_HSYNC_START 0x106 169*4882a593Smuzhiyun #define SAA7134_HSYNC_STOP 0x107 170*4882a593Smuzhiyun #define SAA7134_SYNC_CTRL 0x108 171*4882a593Smuzhiyun #define SAA7134_SYNC_CTRL_AUFD (1 << 7) 172*4882a593Smuzhiyun #define SAA7134_LUMA_CTRL 0x109 173*4882a593Smuzhiyun #define SAA7134_LUMA_CTRL_LDEL (1 << 5) 174*4882a593Smuzhiyun #define SAA7134_DEC_LUMA_BRIGHT 0x10a 175*4882a593Smuzhiyun #define SAA7134_DEC_LUMA_CONTRAST 0x10b 176*4882a593Smuzhiyun #define SAA7134_DEC_CHROMA_SATURATION 0x10c 177*4882a593Smuzhiyun #define SAA7134_DEC_CHROMA_HUE 0x10d 178*4882a593Smuzhiyun #define SAA7134_CHROMA_CTRL1 0x10e 179*4882a593Smuzhiyun #define SAA7134_CHROMA_CTRL1_AUTO0 (1 << 1) 180*4882a593Smuzhiyun #define SAA7134_CHROMA_CTRL1_FCTC (1 << 2) 181*4882a593Smuzhiyun #define SAA7134_CHROMA_GAIN 0x10f 182*4882a593Smuzhiyun #define SAA7134_CHROMA_CTRL2 0x110 183*4882a593Smuzhiyun #define SAA7134_MODE_DELAY_CTRL 0x111 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define SAA7134_ANALOG_ADC 0x114 186*4882a593Smuzhiyun #define SAA7134_ANALOG_ADC_AUTO1 (1 << 2) 187*4882a593Smuzhiyun #define SAA7134_VGATE_START 0x115 188*4882a593Smuzhiyun #define SAA7134_VGATE_STOP 0x116 189*4882a593Smuzhiyun #define SAA7134_MISC_VGATE_MSB 0x117 190*4882a593Smuzhiyun #define SAA7134_RAW_DATA_GAIN 0x118 191*4882a593Smuzhiyun #define SAA7134_RAW_DATA_OFFSET 0x119 192*4882a593Smuzhiyun #define SAA7134_STATUS_VIDEO1 0x11e 193*4882a593Smuzhiyun #define SAA7134_STATUS_VIDEO2 0x11f 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* video scaler */ 196*4882a593Smuzhiyun #define SAA7134_SOURCE_TIMING1 0x000 197*4882a593Smuzhiyun #define SAA7134_SOURCE_TIMING2 0x001 198*4882a593Smuzhiyun #define SAA7134_REGION_ENABLE 0x004 199*4882a593Smuzhiyun #define SAA7134_SCALER_STATUS0 0x006 200*4882a593Smuzhiyun #define SAA7134_SCALER_STATUS1 0x007 201*4882a593Smuzhiyun #define SAA7134_START_GREEN 0x00c 202*4882a593Smuzhiyun #define SAA7134_START_BLUE 0x00d 203*4882a593Smuzhiyun #define SAA7134_START_RED 0x00e 204*4882a593Smuzhiyun #define SAA7134_GREEN_PATH(x) (0x010 +x) 205*4882a593Smuzhiyun #define SAA7134_BLUE_PATH(x) (0x020 +x) 206*4882a593Smuzhiyun #define SAA7134_RED_PATH(x) (0x030 +x) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define TASK_A 0x040 209*4882a593Smuzhiyun #define TASK_B 0x080 210*4882a593Smuzhiyun #define SAA7134_TASK_CONDITIONS(t) (0x000 +t) 211*4882a593Smuzhiyun #define SAA7134_FIELD_HANDLING(t) (0x001 +t) 212*4882a593Smuzhiyun #define SAA7134_DATA_PATH(t) (0x002 +t) 213*4882a593Smuzhiyun #define SAA7134_VBI_H_START1(t) (0x004 +t) 214*4882a593Smuzhiyun #define SAA7134_VBI_H_START2(t) (0x005 +t) 215*4882a593Smuzhiyun #define SAA7134_VBI_H_STOP1(t) (0x006 +t) 216*4882a593Smuzhiyun #define SAA7134_VBI_H_STOP2(t) (0x007 +t) 217*4882a593Smuzhiyun #define SAA7134_VBI_V_START1(t) (0x008 +t) 218*4882a593Smuzhiyun #define SAA7134_VBI_V_START2(t) (0x009 +t) 219*4882a593Smuzhiyun #define SAA7134_VBI_V_STOP1(t) (0x00a +t) 220*4882a593Smuzhiyun #define SAA7134_VBI_V_STOP2(t) (0x00b +t) 221*4882a593Smuzhiyun #define SAA7134_VBI_H_LEN1(t) (0x00c +t) 222*4882a593Smuzhiyun #define SAA7134_VBI_H_LEN2(t) (0x00d +t) 223*4882a593Smuzhiyun #define SAA7134_VBI_V_LEN1(t) (0x00e +t) 224*4882a593Smuzhiyun #define SAA7134_VBI_V_LEN2(t) (0x00f +t) 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define SAA7134_VIDEO_H_START1(t) (0x014 +t) 227*4882a593Smuzhiyun #define SAA7134_VIDEO_H_START2(t) (0x015 +t) 228*4882a593Smuzhiyun #define SAA7134_VIDEO_H_STOP1(t) (0x016 +t) 229*4882a593Smuzhiyun #define SAA7134_VIDEO_H_STOP2(t) (0x017 +t) 230*4882a593Smuzhiyun #define SAA7134_VIDEO_V_START1(t) (0x018 +t) 231*4882a593Smuzhiyun #define SAA7134_VIDEO_V_START2(t) (0x019 +t) 232*4882a593Smuzhiyun #define SAA7134_VIDEO_V_STOP1(t) (0x01a +t) 233*4882a593Smuzhiyun #define SAA7134_VIDEO_V_STOP2(t) (0x01b +t) 234*4882a593Smuzhiyun #define SAA7134_VIDEO_PIXELS1(t) (0x01c +t) 235*4882a593Smuzhiyun #define SAA7134_VIDEO_PIXELS2(t) (0x01d +t) 236*4882a593Smuzhiyun #define SAA7134_VIDEO_LINES1(t) (0x01e +t) 237*4882a593Smuzhiyun #define SAA7134_VIDEO_LINES2(t) (0x01f +t) 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define SAA7134_H_PRESCALE(t) (0x020 +t) 240*4882a593Smuzhiyun #define SAA7134_ACC_LENGTH(t) (0x021 +t) 241*4882a593Smuzhiyun #define SAA7134_LEVEL_CTRL(t) (0x022 +t) 242*4882a593Smuzhiyun #define SAA7134_FIR_PREFILTER_CTRL(t) (0x023 +t) 243*4882a593Smuzhiyun #define SAA7134_LUMA_BRIGHT(t) (0x024 +t) 244*4882a593Smuzhiyun #define SAA7134_LUMA_CONTRAST(t) (0x025 +t) 245*4882a593Smuzhiyun #define SAA7134_CHROMA_SATURATION(t) (0x026 +t) 246*4882a593Smuzhiyun #define SAA7134_VBI_H_SCALE_INC1(t) (0x028 +t) 247*4882a593Smuzhiyun #define SAA7134_VBI_H_SCALE_INC2(t) (0x029 +t) 248*4882a593Smuzhiyun #define SAA7134_VBI_PHASE_OFFSET_LUMA(t) (0x02a +t) 249*4882a593Smuzhiyun #define SAA7134_VBI_PHASE_OFFSET_CHROMA(t) (0x02b +t) 250*4882a593Smuzhiyun #define SAA7134_H_SCALE_INC1(t) (0x02c +t) 251*4882a593Smuzhiyun #define SAA7134_H_SCALE_INC2(t) (0x02d +t) 252*4882a593Smuzhiyun #define SAA7134_H_PHASE_OFF_LUMA(t) (0x02e +t) 253*4882a593Smuzhiyun #define SAA7134_H_PHASE_OFF_CHROMA(t) (0x02f +t) 254*4882a593Smuzhiyun #define SAA7134_V_SCALE_RATIO1(t) (0x030 +t) 255*4882a593Smuzhiyun #define SAA7134_V_SCALE_RATIO2(t) (0x031 +t) 256*4882a593Smuzhiyun #define SAA7134_V_FILTER(t) (0x032 +t) 257*4882a593Smuzhiyun #define SAA7134_V_PHASE_OFFSET0(t) (0x034 +t) 258*4882a593Smuzhiyun #define SAA7134_V_PHASE_OFFSET1(t) (0x035 +t) 259*4882a593Smuzhiyun #define SAA7134_V_PHASE_OFFSET2(t) (0x036 +t) 260*4882a593Smuzhiyun #define SAA7134_V_PHASE_OFFSET3(t) (0x037 +t) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* clipping & dma */ 263*4882a593Smuzhiyun #define SAA7134_OFMT_VIDEO_A 0x300 264*4882a593Smuzhiyun #define SAA7134_OFMT_DATA_A 0x301 265*4882a593Smuzhiyun #define SAA7134_OFMT_VIDEO_B 0x302 266*4882a593Smuzhiyun #define SAA7134_OFMT_DATA_B 0x303 267*4882a593Smuzhiyun #define SAA7134_ALPHA_NOCLIP 0x304 268*4882a593Smuzhiyun #define SAA7134_ALPHA_CLIP 0x305 269*4882a593Smuzhiyun #define SAA7134_UV_PIXEL 0x308 270*4882a593Smuzhiyun #define SAA7134_CLIP_RED 0x309 271*4882a593Smuzhiyun #define SAA7134_CLIP_GREEN 0x30a 272*4882a593Smuzhiyun #define SAA7134_CLIP_BLUE 0x30b 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* i2c bus */ 275*4882a593Smuzhiyun #define SAA7134_I2C_ATTR_STATUS 0x180 276*4882a593Smuzhiyun #define SAA7134_I2C_DATA 0x181 277*4882a593Smuzhiyun #define SAA7134_I2C_CLOCK_SELECT 0x182 278*4882a593Smuzhiyun #define SAA7134_I2C_TIMER 0x183 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* audio */ 281*4882a593Smuzhiyun #define SAA7134_NICAM_ADD_DATA1 0x140 282*4882a593Smuzhiyun #define SAA7134_NICAM_ADD_DATA2 0x141 283*4882a593Smuzhiyun #define SAA7134_NICAM_STATUS 0x142 284*4882a593Smuzhiyun #define SAA7134_AUDIO_STATUS 0x143 285*4882a593Smuzhiyun #define SAA7134_NICAM_ERROR_COUNT 0x144 286*4882a593Smuzhiyun #define SAA7134_IDENT_SIF 0x145 287*4882a593Smuzhiyun #define SAA7134_LEVEL_READOUT1 0x146 288*4882a593Smuzhiyun #define SAA7134_LEVEL_READOUT2 0x147 289*4882a593Smuzhiyun #define SAA7134_NICAM_ERROR_LOW 0x148 290*4882a593Smuzhiyun #define SAA7134_NICAM_ERROR_HIGH 0x149 291*4882a593Smuzhiyun #define SAA7134_DCXO_IDENT_CTRL 0x14a 292*4882a593Smuzhiyun #define SAA7134_DEMODULATOR 0x14b 293*4882a593Smuzhiyun #define SAA7134_AGC_GAIN_SELECT 0x14c 294*4882a593Smuzhiyun #define SAA7134_CARRIER1_FREQ0 0x150 295*4882a593Smuzhiyun #define SAA7134_CARRIER1_FREQ1 0x151 296*4882a593Smuzhiyun #define SAA7134_CARRIER1_FREQ2 0x152 297*4882a593Smuzhiyun #define SAA7134_CARRIER2_FREQ0 0x154 298*4882a593Smuzhiyun #define SAA7134_CARRIER2_FREQ1 0x155 299*4882a593Smuzhiyun #define SAA7134_CARRIER2_FREQ2 0x156 300*4882a593Smuzhiyun #define SAA7134_NUM_SAMPLES0 0x158 301*4882a593Smuzhiyun #define SAA7134_NUM_SAMPLES1 0x159 302*4882a593Smuzhiyun #define SAA7134_NUM_SAMPLES2 0x15a 303*4882a593Smuzhiyun #define SAA7134_AUDIO_FORMAT_CTRL 0x15b 304*4882a593Smuzhiyun #define SAA7134_MONITOR_SELECT 0x160 305*4882a593Smuzhiyun #define SAA7134_FM_DEEMPHASIS 0x161 306*4882a593Smuzhiyun #define SAA7134_FM_DEMATRIX 0x162 307*4882a593Smuzhiyun #define SAA7134_CHANNEL1_LEVEL 0x163 308*4882a593Smuzhiyun #define SAA7134_CHANNEL2_LEVEL 0x164 309*4882a593Smuzhiyun #define SAA7134_NICAM_CONFIG 0x165 310*4882a593Smuzhiyun #define SAA7134_NICAM_LEVEL_ADJUST 0x166 311*4882a593Smuzhiyun #define SAA7134_STEREO_DAC_OUTPUT_SELECT 0x167 312*4882a593Smuzhiyun #define SAA7134_I2S_OUTPUT_FORMAT 0x168 313*4882a593Smuzhiyun #define SAA7134_I2S_OUTPUT_SELECT 0x169 314*4882a593Smuzhiyun #define SAA7134_I2S_OUTPUT_LEVEL 0x16a 315*4882a593Smuzhiyun #define SAA7134_DSP_OUTPUT_SELECT 0x16b 316*4882a593Smuzhiyun #define SAA7134_AUDIO_MUTE_CTRL 0x16c 317*4882a593Smuzhiyun #define SAA7134_SIF_SAMPLE_FREQ 0x16d 318*4882a593Smuzhiyun #define SAA7134_ANALOG_IO_SELECT 0x16e 319*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCK0 0x170 320*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCK1 0x171 321*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCK2 0x172 322*4882a593Smuzhiyun #define SAA7134_AUDIO_PLL_CTRL 0x173 323*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCKS_PER_FIELD0 0x174 324*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCKS_PER_FIELD1 0x175 325*4882a593Smuzhiyun #define SAA7134_AUDIO_CLOCKS_PER_FIELD2 0x176 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* video port output */ 328*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL0 0x190 329*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL1 0x191 330*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL2 0x192 331*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL3 0x193 332*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL4 0x194 333*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL5 0x195 334*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL6 0x196 335*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL7 0x197 336*4882a593Smuzhiyun #define SAA7134_VIDEO_PORT_CTRL8 0x198 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* transport stream interface */ 339*4882a593Smuzhiyun #define SAA7134_TS_PARALLEL 0x1a0 340*4882a593Smuzhiyun #define SAA7134_TS_PARALLEL_SERIAL 0x1a1 341*4882a593Smuzhiyun #define SAA7134_TS_SERIAL0 0x1a2 342*4882a593Smuzhiyun #define SAA7134_TS_SERIAL1 0x1a3 343*4882a593Smuzhiyun #define SAA7134_TS_DMA0 0x1a4 344*4882a593Smuzhiyun #define SAA7134_TS_DMA1 0x1a5 345*4882a593Smuzhiyun #define SAA7134_TS_DMA2 0x1a6 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* GPIO Controls */ 348*4882a593Smuzhiyun #define SAA7134_GPIO_GPRESCAN 0x80 349*4882a593Smuzhiyun #define SAA7134_GPIO_27_25 0x0E 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun #define SAA7134_GPIO_GPMODE0 0x1B0 352*4882a593Smuzhiyun #define SAA7134_GPIO_GPMODE1 0x1B1 353*4882a593Smuzhiyun #define SAA7134_GPIO_GPMODE2 0x1B2 354*4882a593Smuzhiyun #define SAA7134_GPIO_GPMODE3 0x1B3 355*4882a593Smuzhiyun #define SAA7134_GPIO_GPSTATUS0 0x1B4 356*4882a593Smuzhiyun #define SAA7134_GPIO_GPSTATUS1 0x1B5 357*4882a593Smuzhiyun #define SAA7134_GPIO_GPSTATUS2 0x1B6 358*4882a593Smuzhiyun #define SAA7134_GPIO_GPSTATUS3 0x1B7 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* I2S output */ 361*4882a593Smuzhiyun #define SAA7134_I2S_AUDIO_OUTPUT 0x1c0 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun /* test modes */ 364*4882a593Smuzhiyun #define SAA7134_SPECIAL_MODE 0x1d0 365*4882a593Smuzhiyun #define SAA7134_PRODUCTION_TEST_MODE 0x1d1 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun /* audio -- saa7133 + saa7135 only */ 368*4882a593Smuzhiyun #define SAA7135_DSP_RWSTATE 0x580 369*4882a593Smuzhiyun #define SAA7135_DSP_RWSTATE_ERR (1 << 3) 370*4882a593Smuzhiyun #define SAA7135_DSP_RWSTATE_IDA (1 << 2) 371*4882a593Smuzhiyun #define SAA7135_DSP_RWSTATE_RDB (1 << 1) 372*4882a593Smuzhiyun #define SAA7135_DSP_RWSTATE_WRR (1 << 0) 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define SAA7135_DSP_RWCLEAR 0x586 375*4882a593Smuzhiyun #define SAA7135_DSP_RWCLEAR_RERR 1 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #define SAA7133_I2S_AUDIO_CONTROL 0x591 378