1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * driver for Earthsoft PT1/PT2
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * based on pt1dvr - http://pt1dvr.sourceforge.jp/
8*4882a593Smuzhiyun * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/sched.h>
13*4882a593Smuzhiyun #include <linux/sched/signal.h>
14*4882a593Smuzhiyun #include <linux/hrtimer.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/vmalloc.h>
19*4882a593Smuzhiyun #include <linux/pci.h>
20*4882a593Smuzhiyun #include <linux/kthread.h>
21*4882a593Smuzhiyun #include <linux/freezer.h>
22*4882a593Smuzhiyun #include <linux/ratelimit.h>
23*4882a593Smuzhiyun #include <linux/string.h>
24*4882a593Smuzhiyun #include <linux/i2c.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <media/dvbdev.h>
27*4882a593Smuzhiyun #include <media/dvb_demux.h>
28*4882a593Smuzhiyun #include <media/dmxdev.h>
29*4882a593Smuzhiyun #include <media/dvb_net.h>
30*4882a593Smuzhiyun #include <media/dvb_frontend.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include "tc90522.h"
33*4882a593Smuzhiyun #include "qm1d1b0004.h"
34*4882a593Smuzhiyun #include "dvb-pll.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DRIVER_NAME "earth-pt1"
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define PT1_PAGE_SHIFT 12
39*4882a593Smuzhiyun #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
40*4882a593Smuzhiyun #define PT1_NR_UPACKETS 1024
41*4882a593Smuzhiyun #define PT1_NR_BUFS 511
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct pt1_buffer_page {
44*4882a593Smuzhiyun __le32 upackets[PT1_NR_UPACKETS];
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct pt1_table_page {
48*4882a593Smuzhiyun __le32 next_pfn;
49*4882a593Smuzhiyun __le32 buf_pfns[PT1_NR_BUFS];
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct pt1_buffer {
53*4882a593Smuzhiyun struct pt1_buffer_page *page;
54*4882a593Smuzhiyun dma_addr_t addr;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct pt1_table {
58*4882a593Smuzhiyun struct pt1_table_page *page;
59*4882a593Smuzhiyun dma_addr_t addr;
60*4882a593Smuzhiyun struct pt1_buffer bufs[PT1_NR_BUFS];
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun enum pt1_fe_clk {
64*4882a593Smuzhiyun PT1_FE_CLK_20MHZ, /* PT1 */
65*4882a593Smuzhiyun PT1_FE_CLK_25MHZ, /* PT2 */
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define PT1_NR_ADAPS 4
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct pt1_adapter;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct pt1 {
73*4882a593Smuzhiyun struct pci_dev *pdev;
74*4882a593Smuzhiyun void __iomem *regs;
75*4882a593Smuzhiyun struct i2c_adapter i2c_adap;
76*4882a593Smuzhiyun int i2c_running;
77*4882a593Smuzhiyun struct pt1_adapter *adaps[PT1_NR_ADAPS];
78*4882a593Smuzhiyun struct pt1_table *tables;
79*4882a593Smuzhiyun struct task_struct *kthread;
80*4882a593Smuzhiyun int table_index;
81*4882a593Smuzhiyun int buf_index;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct mutex lock;
84*4882a593Smuzhiyun int power;
85*4882a593Smuzhiyun int reset;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun enum pt1_fe_clk fe_clk;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct pt1_adapter {
91*4882a593Smuzhiyun struct pt1 *pt1;
92*4882a593Smuzhiyun int index;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun u8 *buf;
95*4882a593Smuzhiyun int upacket_count;
96*4882a593Smuzhiyun int packet_count;
97*4882a593Smuzhiyun int st_count;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct dvb_adapter adap;
100*4882a593Smuzhiyun struct dvb_demux demux;
101*4882a593Smuzhiyun int users;
102*4882a593Smuzhiyun struct dmxdev dmxdev;
103*4882a593Smuzhiyun struct dvb_frontend *fe;
104*4882a593Smuzhiyun struct i2c_client *demod_i2c_client;
105*4882a593Smuzhiyun struct i2c_client *tuner_i2c_client;
106*4882a593Smuzhiyun int (*orig_set_voltage)(struct dvb_frontend *fe,
107*4882a593Smuzhiyun enum fe_sec_voltage voltage);
108*4882a593Smuzhiyun int (*orig_sleep)(struct dvb_frontend *fe);
109*4882a593Smuzhiyun int (*orig_init)(struct dvb_frontend *fe);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun enum fe_sec_voltage voltage;
112*4882a593Smuzhiyun int sleep;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun union pt1_tuner_config {
116*4882a593Smuzhiyun struct qm1d1b0004_config qm1d1b0004;
117*4882a593Smuzhiyun struct dvb_pll_config tda6651;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct pt1_config {
121*4882a593Smuzhiyun struct i2c_board_info demod_info;
122*4882a593Smuzhiyun struct tc90522_config demod_cfg;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun struct i2c_board_info tuner_info;
125*4882a593Smuzhiyun union pt1_tuner_config tuner_cfg;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const struct pt1_config pt1_configs[PT1_NR_ADAPS] = {
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun .demod_info = {
131*4882a593Smuzhiyun I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun .tuner_info = {
134*4882a593Smuzhiyun I2C_BOARD_INFO("qm1d1b0004", 0x60),
135*4882a593Smuzhiyun },
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun .demod_info = {
139*4882a593Smuzhiyun I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
140*4882a593Smuzhiyun },
141*4882a593Smuzhiyun .tuner_info = {
142*4882a593Smuzhiyun I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
143*4882a593Smuzhiyun },
144*4882a593Smuzhiyun },
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun .demod_info = {
147*4882a593Smuzhiyun I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun .tuner_info = {
150*4882a593Smuzhiyun I2C_BOARD_INFO("qm1d1b0004", 0x60),
151*4882a593Smuzhiyun },
152*4882a593Smuzhiyun },
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun .demod_info = {
155*4882a593Smuzhiyun I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
156*4882a593Smuzhiyun },
157*4882a593Smuzhiyun .tuner_info = {
158*4882a593Smuzhiyun I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
159*4882a593Smuzhiyun },
160*4882a593Smuzhiyun },
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const u8 va1j5jf8007s_20mhz_configs[][2] = {
164*4882a593Smuzhiyun {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
165*4882a593Smuzhiyun {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
166*4882a593Smuzhiyun {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69},
167*4882a593Smuzhiyun {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const u8 va1j5jf8007s_25mhz_configs[][2] = {
171*4882a593Smuzhiyun {0x04, 0x02}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, {0x1c, 0x0a},
172*4882a593Smuzhiyun {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, {0x52, 0x89},
173*4882a593Smuzhiyun {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, {0x87, 0x04},
174*4882a593Smuzhiyun {0x8e, 0x26}, {0xa3, 0xf7}, {0xa5, 0xc0},
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static const u8 va1j5jf8007t_20mhz_configs[][2] = {
178*4882a593Smuzhiyun {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2},
179*4882a593Smuzhiyun {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00},
180*4882a593Smuzhiyun {0x3b, 0x11}, {0x3c, 0x3f},
181*4882a593Smuzhiyun {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03},
182*4882a593Smuzhiyun {0xef, 0x01}
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static const u8 va1j5jf8007t_25mhz_configs[][2] = {
186*4882a593Smuzhiyun {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
187*4882a593Smuzhiyun {0x3a, 0x04}, {0x3b, 0x11}, {0x3c, 0x3f}, {0x5c, 0x40}, {0x5f, 0x80},
188*4882a593Smuzhiyun {0x75, 0x0a}, {0x76, 0x4c}, {0x77, 0x03}, {0xef, 0x01}
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
config_demod(struct i2c_client * cl,enum pt1_fe_clk clk)191*4882a593Smuzhiyun static int config_demod(struct i2c_client *cl, enum pt1_fe_clk clk)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun int ret;
194*4882a593Smuzhiyun bool is_sat;
195*4882a593Smuzhiyun const u8 (*cfg_data)[2];
196*4882a593Smuzhiyun int i, len;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun is_sat = !strncmp(cl->name, TC90522_I2C_DEV_SAT,
199*4882a593Smuzhiyun strlen(TC90522_I2C_DEV_SAT));
200*4882a593Smuzhiyun if (is_sat) {
201*4882a593Smuzhiyun struct i2c_msg msg[2];
202*4882a593Smuzhiyun u8 wbuf, rbuf;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun wbuf = 0x07;
205*4882a593Smuzhiyun msg[0].addr = cl->addr;
206*4882a593Smuzhiyun msg[0].flags = 0;
207*4882a593Smuzhiyun msg[0].len = 1;
208*4882a593Smuzhiyun msg[0].buf = &wbuf;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun msg[1].addr = cl->addr;
211*4882a593Smuzhiyun msg[1].flags = I2C_M_RD;
212*4882a593Smuzhiyun msg[1].len = 1;
213*4882a593Smuzhiyun msg[1].buf = &rbuf;
214*4882a593Smuzhiyun ret = i2c_transfer(cl->adapter, msg, 2);
215*4882a593Smuzhiyun if (ret < 0)
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun if (rbuf != 0x41)
218*4882a593Smuzhiyun return -EIO;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /* frontend init */
222*4882a593Smuzhiyun if (clk == PT1_FE_CLK_20MHZ) {
223*4882a593Smuzhiyun if (is_sat) {
224*4882a593Smuzhiyun cfg_data = va1j5jf8007s_20mhz_configs;
225*4882a593Smuzhiyun len = ARRAY_SIZE(va1j5jf8007s_20mhz_configs);
226*4882a593Smuzhiyun } else {
227*4882a593Smuzhiyun cfg_data = va1j5jf8007t_20mhz_configs;
228*4882a593Smuzhiyun len = ARRAY_SIZE(va1j5jf8007t_20mhz_configs);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun } else {
231*4882a593Smuzhiyun if (is_sat) {
232*4882a593Smuzhiyun cfg_data = va1j5jf8007s_25mhz_configs;
233*4882a593Smuzhiyun len = ARRAY_SIZE(va1j5jf8007s_25mhz_configs);
234*4882a593Smuzhiyun } else {
235*4882a593Smuzhiyun cfg_data = va1j5jf8007t_25mhz_configs;
236*4882a593Smuzhiyun len = ARRAY_SIZE(va1j5jf8007t_25mhz_configs);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun for (i = 0; i < len; i++) {
241*4882a593Smuzhiyun ret = i2c_master_send(cl, cfg_data[i], 2);
242*4882a593Smuzhiyun if (ret < 0)
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun return 0;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /*
249*4882a593Smuzhiyun * Init registers for (each pair of) terrestrial/satellite block in demod.
250*4882a593Smuzhiyun * Note that resetting terr. block also resets its peer sat. block as well.
251*4882a593Smuzhiyun * This function must be called before configuring any demod block
252*4882a593Smuzhiyun * (before pt1_wakeup(), fe->ops.init()).
253*4882a593Smuzhiyun */
pt1_demod_block_init(struct pt1 * pt1)254*4882a593Smuzhiyun static int pt1_demod_block_init(struct pt1 *pt1)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun struct i2c_client *cl;
257*4882a593Smuzhiyun u8 buf[2] = {0x01, 0x80};
258*4882a593Smuzhiyun int ret;
259*4882a593Smuzhiyun int i;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* reset all terr. & sat. pairs first */
262*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++) {
263*4882a593Smuzhiyun cl = pt1->adaps[i]->demod_i2c_client;
264*4882a593Smuzhiyun if (strncmp(cl->name, TC90522_I2C_DEV_TER,
265*4882a593Smuzhiyun strlen(TC90522_I2C_DEV_TER)))
266*4882a593Smuzhiyun continue;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun ret = i2c_master_send(cl, buf, 2);
269*4882a593Smuzhiyun if (ret < 0)
270*4882a593Smuzhiyun return ret;
271*4882a593Smuzhiyun usleep_range(30000, 50000);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++) {
275*4882a593Smuzhiyun cl = pt1->adaps[i]->demod_i2c_client;
276*4882a593Smuzhiyun if (strncmp(cl->name, TC90522_I2C_DEV_SAT,
277*4882a593Smuzhiyun strlen(TC90522_I2C_DEV_SAT)))
278*4882a593Smuzhiyun continue;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun ret = i2c_master_send(cl, buf, 2);
281*4882a593Smuzhiyun if (ret < 0)
282*4882a593Smuzhiyun return ret;
283*4882a593Smuzhiyun usleep_range(30000, 50000);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun return 0;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
pt1_write_reg(struct pt1 * pt1,int reg,u32 data)288*4882a593Smuzhiyun static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun writel(data, pt1->regs + reg * 4);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
pt1_read_reg(struct pt1 * pt1,int reg)293*4882a593Smuzhiyun static u32 pt1_read_reg(struct pt1 *pt1, int reg)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun return readl(pt1->regs + reg * 4);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static unsigned int pt1_nr_tables = 8;
299*4882a593Smuzhiyun module_param_named(nr_tables, pt1_nr_tables, uint, 0);
300*4882a593Smuzhiyun
pt1_increment_table_count(struct pt1 * pt1)301*4882a593Smuzhiyun static void pt1_increment_table_count(struct pt1 *pt1)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000020);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
pt1_init_table_count(struct pt1 * pt1)306*4882a593Smuzhiyun static void pt1_init_table_count(struct pt1 *pt1)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000010);
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
pt1_register_tables(struct pt1 * pt1,u32 first_pfn)311*4882a593Smuzhiyun static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun pt1_write_reg(pt1, 5, first_pfn);
314*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x0c000040);
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
pt1_unregister_tables(struct pt1 * pt1)317*4882a593Smuzhiyun static void pt1_unregister_tables(struct pt1 *pt1)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x08080000);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
pt1_sync(struct pt1 * pt1)322*4882a593Smuzhiyun static int pt1_sync(struct pt1 *pt1)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun int i;
325*4882a593Smuzhiyun for (i = 0; i < 57; i++) {
326*4882a593Smuzhiyun if (pt1_read_reg(pt1, 0) & 0x20000000)
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000008);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun dev_err(&pt1->pdev->dev, "could not sync\n");
331*4882a593Smuzhiyun return -EIO;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
pt1_identify(struct pt1 * pt1)334*4882a593Smuzhiyun static u64 pt1_identify(struct pt1 *pt1)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun int i;
337*4882a593Smuzhiyun u64 id;
338*4882a593Smuzhiyun id = 0;
339*4882a593Smuzhiyun for (i = 0; i < 57; i++) {
340*4882a593Smuzhiyun id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
341*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000008);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun return id;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
pt1_unlock(struct pt1 * pt1)346*4882a593Smuzhiyun static int pt1_unlock(struct pt1 *pt1)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun int i;
349*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000008);
350*4882a593Smuzhiyun for (i = 0; i < 3; i++) {
351*4882a593Smuzhiyun if (pt1_read_reg(pt1, 0) & 0x80000000)
352*4882a593Smuzhiyun return 0;
353*4882a593Smuzhiyun usleep_range(1000, 2000);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun dev_err(&pt1->pdev->dev, "could not unlock\n");
356*4882a593Smuzhiyun return -EIO;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
pt1_reset_pci(struct pt1 * pt1)359*4882a593Smuzhiyun static int pt1_reset_pci(struct pt1 *pt1)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun int i;
362*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x01010000);
363*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x01000000);
364*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
365*4882a593Smuzhiyun if (pt1_read_reg(pt1, 0) & 0x00000001)
366*4882a593Smuzhiyun return 0;
367*4882a593Smuzhiyun usleep_range(1000, 2000);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun dev_err(&pt1->pdev->dev, "could not reset PCI\n");
370*4882a593Smuzhiyun return -EIO;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
pt1_reset_ram(struct pt1 * pt1)373*4882a593Smuzhiyun static int pt1_reset_ram(struct pt1 *pt1)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun int i;
376*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x02020000);
377*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x02000000);
378*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
379*4882a593Smuzhiyun if (pt1_read_reg(pt1, 0) & 0x00000002)
380*4882a593Smuzhiyun return 0;
381*4882a593Smuzhiyun usleep_range(1000, 2000);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun dev_err(&pt1->pdev->dev, "could not reset RAM\n");
384*4882a593Smuzhiyun return -EIO;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
pt1_do_enable_ram(struct pt1 * pt1)387*4882a593Smuzhiyun static int pt1_do_enable_ram(struct pt1 *pt1)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun int i, j;
390*4882a593Smuzhiyun u32 status;
391*4882a593Smuzhiyun status = pt1_read_reg(pt1, 0) & 0x00000004;
392*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000002);
393*4882a593Smuzhiyun for (i = 0; i < 10; i++) {
394*4882a593Smuzhiyun for (j = 0; j < 1024; j++) {
395*4882a593Smuzhiyun if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
396*4882a593Smuzhiyun return 0;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun usleep_range(1000, 2000);
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun dev_err(&pt1->pdev->dev, "could not enable RAM\n");
401*4882a593Smuzhiyun return -EIO;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
pt1_enable_ram(struct pt1 * pt1)404*4882a593Smuzhiyun static int pt1_enable_ram(struct pt1 *pt1)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun int i, ret;
407*4882a593Smuzhiyun int phase;
408*4882a593Smuzhiyun usleep_range(1000, 2000);
409*4882a593Smuzhiyun phase = pt1->pdev->device == 0x211a ? 128 : 166;
410*4882a593Smuzhiyun for (i = 0; i < phase; i++) {
411*4882a593Smuzhiyun ret = pt1_do_enable_ram(pt1);
412*4882a593Smuzhiyun if (ret < 0)
413*4882a593Smuzhiyun return ret;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun return 0;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
pt1_disable_ram(struct pt1 * pt1)418*4882a593Smuzhiyun static void pt1_disable_ram(struct pt1 *pt1)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x0b0b0000);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
pt1_set_stream(struct pt1 * pt1,int index,int enabled)423*4882a593Smuzhiyun static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
pt1_init_streams(struct pt1 * pt1)428*4882a593Smuzhiyun static void pt1_init_streams(struct pt1 *pt1)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun int i;
431*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++)
432*4882a593Smuzhiyun pt1_set_stream(pt1, i, 0);
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
pt1_filter(struct pt1 * pt1,struct pt1_buffer_page * page)435*4882a593Smuzhiyun static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun u32 upacket;
438*4882a593Smuzhiyun int i;
439*4882a593Smuzhiyun int index;
440*4882a593Smuzhiyun struct pt1_adapter *adap;
441*4882a593Smuzhiyun int offset;
442*4882a593Smuzhiyun u8 *buf;
443*4882a593Smuzhiyun int sc;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (!page->upackets[PT1_NR_UPACKETS - 1])
446*4882a593Smuzhiyun return 0;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun for (i = 0; i < PT1_NR_UPACKETS; i++) {
449*4882a593Smuzhiyun upacket = le32_to_cpu(page->upackets[i]);
450*4882a593Smuzhiyun index = (upacket >> 29) - 1;
451*4882a593Smuzhiyun if (index < 0 || index >= PT1_NR_ADAPS)
452*4882a593Smuzhiyun continue;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun adap = pt1->adaps[index];
455*4882a593Smuzhiyun if (upacket >> 25 & 1)
456*4882a593Smuzhiyun adap->upacket_count = 0;
457*4882a593Smuzhiyun else if (!adap->upacket_count)
458*4882a593Smuzhiyun continue;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (upacket >> 24 & 1)
461*4882a593Smuzhiyun printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
462*4882a593Smuzhiyun pt1->table_index, pt1->buf_index);
463*4882a593Smuzhiyun sc = upacket >> 26 & 0x7;
464*4882a593Smuzhiyun if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
465*4882a593Smuzhiyun printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
466*4882a593Smuzhiyun index);
467*4882a593Smuzhiyun adap->st_count = sc;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun buf = adap->buf;
470*4882a593Smuzhiyun offset = adap->packet_count * 188 + adap->upacket_count * 3;
471*4882a593Smuzhiyun buf[offset] = upacket >> 16;
472*4882a593Smuzhiyun buf[offset + 1] = upacket >> 8;
473*4882a593Smuzhiyun if (adap->upacket_count != 62)
474*4882a593Smuzhiyun buf[offset + 2] = upacket;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun if (++adap->upacket_count >= 63) {
477*4882a593Smuzhiyun adap->upacket_count = 0;
478*4882a593Smuzhiyun if (++adap->packet_count >= 21) {
479*4882a593Smuzhiyun dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
480*4882a593Smuzhiyun adap->packet_count = 0;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun page->upackets[PT1_NR_UPACKETS - 1] = 0;
486*4882a593Smuzhiyun return 1;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
pt1_thread(void * data)489*4882a593Smuzhiyun static int pt1_thread(void *data)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct pt1 *pt1;
492*4882a593Smuzhiyun struct pt1_buffer_page *page;
493*4882a593Smuzhiyun bool was_frozen;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun #define PT1_FETCH_DELAY 10
496*4882a593Smuzhiyun #define PT1_FETCH_DELAY_DELTA 2
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun pt1 = data;
499*4882a593Smuzhiyun set_freezable();
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun while (!kthread_freezable_should_stop(&was_frozen)) {
502*4882a593Smuzhiyun if (was_frozen) {
503*4882a593Smuzhiyun int i;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++)
506*4882a593Smuzhiyun pt1_set_stream(pt1, i, !!pt1->adaps[i]->users);
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
510*4882a593Smuzhiyun if (!pt1_filter(pt1, page)) {
511*4882a593Smuzhiyun ktime_t delay;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun delay = ktime_set(0, PT1_FETCH_DELAY * NSEC_PER_MSEC);
514*4882a593Smuzhiyun set_current_state(TASK_INTERRUPTIBLE);
515*4882a593Smuzhiyun schedule_hrtimeout_range(&delay,
516*4882a593Smuzhiyun PT1_FETCH_DELAY_DELTA * NSEC_PER_MSEC,
517*4882a593Smuzhiyun HRTIMER_MODE_REL);
518*4882a593Smuzhiyun continue;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (++pt1->buf_index >= PT1_NR_BUFS) {
522*4882a593Smuzhiyun pt1_increment_table_count(pt1);
523*4882a593Smuzhiyun pt1->buf_index = 0;
524*4882a593Smuzhiyun if (++pt1->table_index >= pt1_nr_tables)
525*4882a593Smuzhiyun pt1->table_index = 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun
pt1_free_page(struct pt1 * pt1,void * page,dma_addr_t addr)532*4882a593Smuzhiyun static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun
pt1_alloc_page(struct pt1 * pt1,dma_addr_t * addrp,u32 * pfnp)537*4882a593Smuzhiyun static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun void *page;
540*4882a593Smuzhiyun dma_addr_t addr;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
543*4882a593Smuzhiyun GFP_KERNEL);
544*4882a593Smuzhiyun if (page == NULL)
545*4882a593Smuzhiyun return NULL;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun BUG_ON(addr & (PT1_PAGE_SIZE - 1));
548*4882a593Smuzhiyun BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun *addrp = addr;
551*4882a593Smuzhiyun *pfnp = addr >> PT1_PAGE_SHIFT;
552*4882a593Smuzhiyun return page;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
pt1_cleanup_buffer(struct pt1 * pt1,struct pt1_buffer * buf)555*4882a593Smuzhiyun static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun pt1_free_page(pt1, buf->page, buf->addr);
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun static int
pt1_init_buffer(struct pt1 * pt1,struct pt1_buffer * buf,u32 * pfnp)561*4882a593Smuzhiyun pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun struct pt1_buffer_page *page;
564*4882a593Smuzhiyun dma_addr_t addr;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun page = pt1_alloc_page(pt1, &addr, pfnp);
567*4882a593Smuzhiyun if (page == NULL)
568*4882a593Smuzhiyun return -ENOMEM;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun page->upackets[PT1_NR_UPACKETS - 1] = 0;
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun buf->page = page;
573*4882a593Smuzhiyun buf->addr = addr;
574*4882a593Smuzhiyun return 0;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun
pt1_cleanup_table(struct pt1 * pt1,struct pt1_table * table)577*4882a593Smuzhiyun static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun int i;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun for (i = 0; i < PT1_NR_BUFS; i++)
582*4882a593Smuzhiyun pt1_cleanup_buffer(pt1, &table->bufs[i]);
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun pt1_free_page(pt1, table->page, table->addr);
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static int
pt1_init_table(struct pt1 * pt1,struct pt1_table * table,u32 * pfnp)588*4882a593Smuzhiyun pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun struct pt1_table_page *page;
591*4882a593Smuzhiyun dma_addr_t addr;
592*4882a593Smuzhiyun int i, ret;
593*4882a593Smuzhiyun u32 buf_pfn;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun page = pt1_alloc_page(pt1, &addr, pfnp);
596*4882a593Smuzhiyun if (page == NULL)
597*4882a593Smuzhiyun return -ENOMEM;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun for (i = 0; i < PT1_NR_BUFS; i++) {
600*4882a593Smuzhiyun ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
601*4882a593Smuzhiyun if (ret < 0)
602*4882a593Smuzhiyun goto err;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun page->buf_pfns[i] = cpu_to_le32(buf_pfn);
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun pt1_increment_table_count(pt1);
608*4882a593Smuzhiyun table->page = page;
609*4882a593Smuzhiyun table->addr = addr;
610*4882a593Smuzhiyun return 0;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun err:
613*4882a593Smuzhiyun while (i--)
614*4882a593Smuzhiyun pt1_cleanup_buffer(pt1, &table->bufs[i]);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun pt1_free_page(pt1, page, addr);
617*4882a593Smuzhiyun return ret;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
pt1_cleanup_tables(struct pt1 * pt1)620*4882a593Smuzhiyun static void pt1_cleanup_tables(struct pt1 *pt1)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun struct pt1_table *tables;
623*4882a593Smuzhiyun int i;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun tables = pt1->tables;
626*4882a593Smuzhiyun pt1_unregister_tables(pt1);
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun for (i = 0; i < pt1_nr_tables; i++)
629*4882a593Smuzhiyun pt1_cleanup_table(pt1, &tables[i]);
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun vfree(tables);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
pt1_init_tables(struct pt1 * pt1)634*4882a593Smuzhiyun static int pt1_init_tables(struct pt1 *pt1)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun struct pt1_table *tables;
637*4882a593Smuzhiyun int i, ret;
638*4882a593Smuzhiyun u32 first_pfn, pfn;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun if (!pt1_nr_tables)
641*4882a593Smuzhiyun return 0;
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun tables = vmalloc(array_size(pt1_nr_tables, sizeof(struct pt1_table)));
644*4882a593Smuzhiyun if (tables == NULL)
645*4882a593Smuzhiyun return -ENOMEM;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun pt1_init_table_count(pt1);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun i = 0;
650*4882a593Smuzhiyun ret = pt1_init_table(pt1, &tables[0], &first_pfn);
651*4882a593Smuzhiyun if (ret)
652*4882a593Smuzhiyun goto err;
653*4882a593Smuzhiyun i++;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun while (i < pt1_nr_tables) {
656*4882a593Smuzhiyun ret = pt1_init_table(pt1, &tables[i], &pfn);
657*4882a593Smuzhiyun if (ret)
658*4882a593Smuzhiyun goto err;
659*4882a593Smuzhiyun tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
660*4882a593Smuzhiyun i++;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun pt1_register_tables(pt1, first_pfn);
666*4882a593Smuzhiyun pt1->tables = tables;
667*4882a593Smuzhiyun return 0;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun err:
670*4882a593Smuzhiyun while (i--)
671*4882a593Smuzhiyun pt1_cleanup_table(pt1, &tables[i]);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun vfree(tables);
674*4882a593Smuzhiyun return ret;
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun
pt1_start_polling(struct pt1 * pt1)677*4882a593Smuzhiyun static int pt1_start_polling(struct pt1 *pt1)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun int ret = 0;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun mutex_lock(&pt1->lock);
682*4882a593Smuzhiyun if (!pt1->kthread) {
683*4882a593Smuzhiyun pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
684*4882a593Smuzhiyun if (IS_ERR(pt1->kthread)) {
685*4882a593Smuzhiyun ret = PTR_ERR(pt1->kthread);
686*4882a593Smuzhiyun pt1->kthread = NULL;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun mutex_unlock(&pt1->lock);
690*4882a593Smuzhiyun return ret;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
pt1_start_feed(struct dvb_demux_feed * feed)693*4882a593Smuzhiyun static int pt1_start_feed(struct dvb_demux_feed *feed)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun struct pt1_adapter *adap;
696*4882a593Smuzhiyun adap = container_of(feed->demux, struct pt1_adapter, demux);
697*4882a593Smuzhiyun if (!adap->users++) {
698*4882a593Smuzhiyun int ret;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun ret = pt1_start_polling(adap->pt1);
701*4882a593Smuzhiyun if (ret)
702*4882a593Smuzhiyun return ret;
703*4882a593Smuzhiyun pt1_set_stream(adap->pt1, adap->index, 1);
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun return 0;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
pt1_stop_polling(struct pt1 * pt1)708*4882a593Smuzhiyun static void pt1_stop_polling(struct pt1 *pt1)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun int i, count;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun mutex_lock(&pt1->lock);
713*4882a593Smuzhiyun for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
714*4882a593Smuzhiyun count += pt1->adaps[i]->users;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun if (count == 0 && pt1->kthread) {
717*4882a593Smuzhiyun kthread_stop(pt1->kthread);
718*4882a593Smuzhiyun pt1->kthread = NULL;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun mutex_unlock(&pt1->lock);
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
pt1_stop_feed(struct dvb_demux_feed * feed)723*4882a593Smuzhiyun static int pt1_stop_feed(struct dvb_demux_feed *feed)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun struct pt1_adapter *adap;
726*4882a593Smuzhiyun adap = container_of(feed->demux, struct pt1_adapter, demux);
727*4882a593Smuzhiyun if (!--adap->users) {
728*4882a593Smuzhiyun pt1_set_stream(adap->pt1, adap->index, 0);
729*4882a593Smuzhiyun pt1_stop_polling(adap->pt1);
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun return 0;
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun static void
pt1_update_power(struct pt1 * pt1)735*4882a593Smuzhiyun pt1_update_power(struct pt1 *pt1)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun int bits;
738*4882a593Smuzhiyun int i;
739*4882a593Smuzhiyun struct pt1_adapter *adap;
740*4882a593Smuzhiyun static const int sleep_bits[] = {
741*4882a593Smuzhiyun 1 << 4,
742*4882a593Smuzhiyun 1 << 6 | 1 << 7,
743*4882a593Smuzhiyun 1 << 5,
744*4882a593Smuzhiyun 1 << 6 | 1 << 8,
745*4882a593Smuzhiyun };
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun bits = pt1->power | !pt1->reset << 3;
748*4882a593Smuzhiyun mutex_lock(&pt1->lock);
749*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++) {
750*4882a593Smuzhiyun adap = pt1->adaps[i];
751*4882a593Smuzhiyun switch (adap->voltage) {
752*4882a593Smuzhiyun case SEC_VOLTAGE_13: /* actually 11V */
753*4882a593Smuzhiyun bits |= 1 << 2;
754*4882a593Smuzhiyun break;
755*4882a593Smuzhiyun case SEC_VOLTAGE_18: /* actually 15V */
756*4882a593Smuzhiyun bits |= 1 << 1 | 1 << 2;
757*4882a593Smuzhiyun break;
758*4882a593Smuzhiyun default:
759*4882a593Smuzhiyun break;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun /* XXX: The bits should be changed depending on adap->sleep. */
763*4882a593Smuzhiyun bits |= sleep_bits[i];
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun pt1_write_reg(pt1, 1, bits);
766*4882a593Smuzhiyun mutex_unlock(&pt1->lock);
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
pt1_set_voltage(struct dvb_frontend * fe,enum fe_sec_voltage voltage)769*4882a593Smuzhiyun static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun struct pt1_adapter *adap;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun adap = container_of(fe->dvb, struct pt1_adapter, adap);
774*4882a593Smuzhiyun adap->voltage = voltage;
775*4882a593Smuzhiyun pt1_update_power(adap->pt1);
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun if (adap->orig_set_voltage)
778*4882a593Smuzhiyun return adap->orig_set_voltage(fe, voltage);
779*4882a593Smuzhiyun else
780*4882a593Smuzhiyun return 0;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
pt1_sleep(struct dvb_frontend * fe)783*4882a593Smuzhiyun static int pt1_sleep(struct dvb_frontend *fe)
784*4882a593Smuzhiyun {
785*4882a593Smuzhiyun struct pt1_adapter *adap;
786*4882a593Smuzhiyun int ret;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun adap = container_of(fe->dvb, struct pt1_adapter, adap);
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun ret = 0;
791*4882a593Smuzhiyun if (adap->orig_sleep)
792*4882a593Smuzhiyun ret = adap->orig_sleep(fe);
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun adap->sleep = 1;
795*4882a593Smuzhiyun pt1_update_power(adap->pt1);
796*4882a593Smuzhiyun return ret;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
pt1_wakeup(struct dvb_frontend * fe)799*4882a593Smuzhiyun static int pt1_wakeup(struct dvb_frontend *fe)
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun struct pt1_adapter *adap;
802*4882a593Smuzhiyun int ret;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun adap = container_of(fe->dvb, struct pt1_adapter, adap);
805*4882a593Smuzhiyun adap->sleep = 0;
806*4882a593Smuzhiyun pt1_update_power(adap->pt1);
807*4882a593Smuzhiyun usleep_range(1000, 2000);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun ret = config_demod(adap->demod_i2c_client, adap->pt1->fe_clk);
810*4882a593Smuzhiyun if (ret == 0 && adap->orig_init)
811*4882a593Smuzhiyun ret = adap->orig_init(fe);
812*4882a593Smuzhiyun return ret;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
pt1_free_adapter(struct pt1_adapter * adap)815*4882a593Smuzhiyun static void pt1_free_adapter(struct pt1_adapter *adap)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun adap->demux.dmx.close(&adap->demux.dmx);
818*4882a593Smuzhiyun dvb_dmxdev_release(&adap->dmxdev);
819*4882a593Smuzhiyun dvb_dmx_release(&adap->demux);
820*4882a593Smuzhiyun dvb_unregister_adapter(&adap->adap);
821*4882a593Smuzhiyun free_page((unsigned long)adap->buf);
822*4882a593Smuzhiyun kfree(adap);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun static struct pt1_adapter *
pt1_alloc_adapter(struct pt1 * pt1)828*4882a593Smuzhiyun pt1_alloc_adapter(struct pt1 *pt1)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun struct pt1_adapter *adap;
831*4882a593Smuzhiyun void *buf;
832*4882a593Smuzhiyun struct dvb_adapter *dvb_adap;
833*4882a593Smuzhiyun struct dvb_demux *demux;
834*4882a593Smuzhiyun struct dmxdev *dmxdev;
835*4882a593Smuzhiyun int ret;
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
838*4882a593Smuzhiyun if (!adap) {
839*4882a593Smuzhiyun ret = -ENOMEM;
840*4882a593Smuzhiyun goto err;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun adap->pt1 = pt1;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun adap->voltage = SEC_VOLTAGE_OFF;
846*4882a593Smuzhiyun adap->sleep = 1;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun buf = (u8 *)__get_free_page(GFP_KERNEL);
849*4882a593Smuzhiyun if (!buf) {
850*4882a593Smuzhiyun ret = -ENOMEM;
851*4882a593Smuzhiyun goto err_kfree;
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun adap->buf = buf;
855*4882a593Smuzhiyun adap->upacket_count = 0;
856*4882a593Smuzhiyun adap->packet_count = 0;
857*4882a593Smuzhiyun adap->st_count = -1;
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun dvb_adap = &adap->adap;
860*4882a593Smuzhiyun dvb_adap->priv = adap;
861*4882a593Smuzhiyun ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
862*4882a593Smuzhiyun &pt1->pdev->dev, adapter_nr);
863*4882a593Smuzhiyun if (ret < 0)
864*4882a593Smuzhiyun goto err_free_page;
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun demux = &adap->demux;
867*4882a593Smuzhiyun demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
868*4882a593Smuzhiyun demux->priv = adap;
869*4882a593Smuzhiyun demux->feednum = 256;
870*4882a593Smuzhiyun demux->filternum = 256;
871*4882a593Smuzhiyun demux->start_feed = pt1_start_feed;
872*4882a593Smuzhiyun demux->stop_feed = pt1_stop_feed;
873*4882a593Smuzhiyun demux->write_to_decoder = NULL;
874*4882a593Smuzhiyun ret = dvb_dmx_init(demux);
875*4882a593Smuzhiyun if (ret < 0)
876*4882a593Smuzhiyun goto err_unregister_adapter;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun dmxdev = &adap->dmxdev;
879*4882a593Smuzhiyun dmxdev->filternum = 256;
880*4882a593Smuzhiyun dmxdev->demux = &demux->dmx;
881*4882a593Smuzhiyun dmxdev->capabilities = 0;
882*4882a593Smuzhiyun ret = dvb_dmxdev_init(dmxdev, dvb_adap);
883*4882a593Smuzhiyun if (ret < 0)
884*4882a593Smuzhiyun goto err_dmx_release;
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun return adap;
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun err_dmx_release:
889*4882a593Smuzhiyun dvb_dmx_release(demux);
890*4882a593Smuzhiyun err_unregister_adapter:
891*4882a593Smuzhiyun dvb_unregister_adapter(dvb_adap);
892*4882a593Smuzhiyun err_free_page:
893*4882a593Smuzhiyun free_page((unsigned long)buf);
894*4882a593Smuzhiyun err_kfree:
895*4882a593Smuzhiyun kfree(adap);
896*4882a593Smuzhiyun err:
897*4882a593Smuzhiyun return ERR_PTR(ret);
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
pt1_cleanup_adapters(struct pt1 * pt1)900*4882a593Smuzhiyun static void pt1_cleanup_adapters(struct pt1 *pt1)
901*4882a593Smuzhiyun {
902*4882a593Smuzhiyun int i;
903*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++)
904*4882a593Smuzhiyun pt1_free_adapter(pt1->adaps[i]);
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun
pt1_init_adapters(struct pt1 * pt1)907*4882a593Smuzhiyun static int pt1_init_adapters(struct pt1 *pt1)
908*4882a593Smuzhiyun {
909*4882a593Smuzhiyun int i;
910*4882a593Smuzhiyun struct pt1_adapter *adap;
911*4882a593Smuzhiyun int ret;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++) {
914*4882a593Smuzhiyun adap = pt1_alloc_adapter(pt1);
915*4882a593Smuzhiyun if (IS_ERR(adap)) {
916*4882a593Smuzhiyun ret = PTR_ERR(adap);
917*4882a593Smuzhiyun goto err;
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun adap->index = i;
921*4882a593Smuzhiyun pt1->adaps[i] = adap;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun return 0;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun err:
926*4882a593Smuzhiyun while (i--)
927*4882a593Smuzhiyun pt1_free_adapter(pt1->adaps[i]);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun return ret;
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
pt1_cleanup_frontend(struct pt1_adapter * adap)932*4882a593Smuzhiyun static void pt1_cleanup_frontend(struct pt1_adapter *adap)
933*4882a593Smuzhiyun {
934*4882a593Smuzhiyun dvb_unregister_frontend(adap->fe);
935*4882a593Smuzhiyun dvb_module_release(adap->tuner_i2c_client);
936*4882a593Smuzhiyun dvb_module_release(adap->demod_i2c_client);
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun
pt1_init_frontend(struct pt1_adapter * adap,struct dvb_frontend * fe)939*4882a593Smuzhiyun static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun int ret;
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun adap->orig_set_voltage = fe->ops.set_voltage;
944*4882a593Smuzhiyun adap->orig_sleep = fe->ops.sleep;
945*4882a593Smuzhiyun adap->orig_init = fe->ops.init;
946*4882a593Smuzhiyun fe->ops.set_voltage = pt1_set_voltage;
947*4882a593Smuzhiyun fe->ops.sleep = pt1_sleep;
948*4882a593Smuzhiyun fe->ops.init = pt1_wakeup;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun ret = dvb_register_frontend(&adap->adap, fe);
951*4882a593Smuzhiyun if (ret < 0)
952*4882a593Smuzhiyun return ret;
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun adap->fe = fe;
955*4882a593Smuzhiyun return 0;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun
pt1_cleanup_frontends(struct pt1 * pt1)958*4882a593Smuzhiyun static void pt1_cleanup_frontends(struct pt1 *pt1)
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun int i;
961*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++)
962*4882a593Smuzhiyun pt1_cleanup_frontend(pt1->adaps[i]);
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
pt1_init_frontends(struct pt1 * pt1)965*4882a593Smuzhiyun static int pt1_init_frontends(struct pt1 *pt1)
966*4882a593Smuzhiyun {
967*4882a593Smuzhiyun int i;
968*4882a593Smuzhiyun int ret;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pt1_configs); i++) {
971*4882a593Smuzhiyun const struct i2c_board_info *info;
972*4882a593Smuzhiyun struct tc90522_config dcfg;
973*4882a593Smuzhiyun struct i2c_client *cl;
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun info = &pt1_configs[i].demod_info;
976*4882a593Smuzhiyun dcfg = pt1_configs[i].demod_cfg;
977*4882a593Smuzhiyun dcfg.tuner_i2c = NULL;
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun ret = -ENODEV;
980*4882a593Smuzhiyun cl = dvb_module_probe("tc90522", info->type, &pt1->i2c_adap,
981*4882a593Smuzhiyun info->addr, &dcfg);
982*4882a593Smuzhiyun if (!cl)
983*4882a593Smuzhiyun goto fe_unregister;
984*4882a593Smuzhiyun pt1->adaps[i]->demod_i2c_client = cl;
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun if (!strncmp(cl->name, TC90522_I2C_DEV_SAT,
987*4882a593Smuzhiyun strlen(TC90522_I2C_DEV_SAT))) {
988*4882a593Smuzhiyun struct qm1d1b0004_config tcfg;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun info = &pt1_configs[i].tuner_info;
991*4882a593Smuzhiyun tcfg = pt1_configs[i].tuner_cfg.qm1d1b0004;
992*4882a593Smuzhiyun tcfg.fe = dcfg.fe;
993*4882a593Smuzhiyun cl = dvb_module_probe("qm1d1b0004",
994*4882a593Smuzhiyun info->type, dcfg.tuner_i2c,
995*4882a593Smuzhiyun info->addr, &tcfg);
996*4882a593Smuzhiyun } else {
997*4882a593Smuzhiyun struct dvb_pll_config tcfg;
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun info = &pt1_configs[i].tuner_info;
1000*4882a593Smuzhiyun tcfg = pt1_configs[i].tuner_cfg.tda6651;
1001*4882a593Smuzhiyun tcfg.fe = dcfg.fe;
1002*4882a593Smuzhiyun cl = dvb_module_probe("dvb_pll",
1003*4882a593Smuzhiyun info->type, dcfg.tuner_i2c,
1004*4882a593Smuzhiyun info->addr, &tcfg);
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun if (!cl)
1007*4882a593Smuzhiyun goto demod_release;
1008*4882a593Smuzhiyun pt1->adaps[i]->tuner_i2c_client = cl;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe);
1011*4882a593Smuzhiyun if (ret < 0)
1012*4882a593Smuzhiyun goto tuner_release;
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun ret = pt1_demod_block_init(pt1);
1016*4882a593Smuzhiyun if (ret < 0)
1017*4882a593Smuzhiyun goto fe_unregister;
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun return 0;
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun tuner_release:
1022*4882a593Smuzhiyun dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
1023*4882a593Smuzhiyun demod_release:
1024*4882a593Smuzhiyun dvb_module_release(pt1->adaps[i]->demod_i2c_client);
1025*4882a593Smuzhiyun fe_unregister:
1026*4882a593Smuzhiyun dev_warn(&pt1->pdev->dev, "failed to init FE(%d).\n", i);
1027*4882a593Smuzhiyun i--;
1028*4882a593Smuzhiyun for (; i >= 0; i--) {
1029*4882a593Smuzhiyun dvb_unregister_frontend(pt1->adaps[i]->fe);
1030*4882a593Smuzhiyun dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
1031*4882a593Smuzhiyun dvb_module_release(pt1->adaps[i]->demod_i2c_client);
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun return ret;
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun
pt1_i2c_emit(struct pt1 * pt1,int addr,int busy,int read_enable,int clock,int data,int next_addr)1036*4882a593Smuzhiyun static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
1037*4882a593Smuzhiyun int clock, int data, int next_addr)
1038*4882a593Smuzhiyun {
1039*4882a593Smuzhiyun pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
1040*4882a593Smuzhiyun !clock << 11 | !data << 10 | next_addr);
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun
pt1_i2c_write_bit(struct pt1 * pt1,int addr,int * addrp,int data)1043*4882a593Smuzhiyun static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
1044*4882a593Smuzhiyun {
1045*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
1046*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
1047*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
1048*4882a593Smuzhiyun *addrp = addr + 3;
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun
pt1_i2c_read_bit(struct pt1 * pt1,int addr,int * addrp)1051*4882a593Smuzhiyun static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
1052*4882a593Smuzhiyun {
1053*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
1054*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
1055*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
1056*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
1057*4882a593Smuzhiyun *addrp = addr + 4;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
pt1_i2c_write_byte(struct pt1 * pt1,int addr,int * addrp,int data)1060*4882a593Smuzhiyun static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun int i;
1063*4882a593Smuzhiyun for (i = 0; i < 8; i++)
1064*4882a593Smuzhiyun pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
1065*4882a593Smuzhiyun pt1_i2c_write_bit(pt1, addr, &addr, 1);
1066*4882a593Smuzhiyun *addrp = addr;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun
pt1_i2c_read_byte(struct pt1 * pt1,int addr,int * addrp,int last)1069*4882a593Smuzhiyun static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
1070*4882a593Smuzhiyun {
1071*4882a593Smuzhiyun int i;
1072*4882a593Smuzhiyun for (i = 0; i < 8; i++)
1073*4882a593Smuzhiyun pt1_i2c_read_bit(pt1, addr, &addr);
1074*4882a593Smuzhiyun pt1_i2c_write_bit(pt1, addr, &addr, last);
1075*4882a593Smuzhiyun *addrp = addr;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun
pt1_i2c_prepare(struct pt1 * pt1,int addr,int * addrp)1078*4882a593Smuzhiyun static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
1079*4882a593Smuzhiyun {
1080*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
1081*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
1082*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
1083*4882a593Smuzhiyun *addrp = addr + 3;
1084*4882a593Smuzhiyun }
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun static void
pt1_i2c_write_msg(struct pt1 * pt1,int addr,int * addrp,struct i2c_msg * msg)1087*4882a593Smuzhiyun pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
1088*4882a593Smuzhiyun {
1089*4882a593Smuzhiyun int i;
1090*4882a593Smuzhiyun pt1_i2c_prepare(pt1, addr, &addr);
1091*4882a593Smuzhiyun pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
1092*4882a593Smuzhiyun for (i = 0; i < msg->len; i++)
1093*4882a593Smuzhiyun pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
1094*4882a593Smuzhiyun *addrp = addr;
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun static void
pt1_i2c_read_msg(struct pt1 * pt1,int addr,int * addrp,struct i2c_msg * msg)1098*4882a593Smuzhiyun pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun int i;
1101*4882a593Smuzhiyun pt1_i2c_prepare(pt1, addr, &addr);
1102*4882a593Smuzhiyun pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
1103*4882a593Smuzhiyun for (i = 0; i < msg->len; i++)
1104*4882a593Smuzhiyun pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
1105*4882a593Smuzhiyun *addrp = addr;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun
pt1_i2c_end(struct pt1 * pt1,int addr)1108*4882a593Smuzhiyun static int pt1_i2c_end(struct pt1 *pt1, int addr)
1109*4882a593Smuzhiyun {
1110*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
1111*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
1112*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun pt1_write_reg(pt1, 0, 0x00000004);
1115*4882a593Smuzhiyun do {
1116*4882a593Smuzhiyun if (signal_pending(current))
1117*4882a593Smuzhiyun return -EINTR;
1118*4882a593Smuzhiyun usleep_range(1000, 2000);
1119*4882a593Smuzhiyun } while (pt1_read_reg(pt1, 0) & 0x00000080);
1120*4882a593Smuzhiyun return 0;
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun
pt1_i2c_begin(struct pt1 * pt1,int * addrp)1123*4882a593Smuzhiyun static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
1124*4882a593Smuzhiyun {
1125*4882a593Smuzhiyun int addr;
1126*4882a593Smuzhiyun addr = 0;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
1129*4882a593Smuzhiyun addr = addr + 1;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun if (!pt1->i2c_running) {
1132*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
1133*4882a593Smuzhiyun pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
1134*4882a593Smuzhiyun addr = addr + 2;
1135*4882a593Smuzhiyun pt1->i2c_running = 1;
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun *addrp = addr;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun
pt1_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1140*4882a593Smuzhiyun static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1141*4882a593Smuzhiyun {
1142*4882a593Smuzhiyun struct pt1 *pt1;
1143*4882a593Smuzhiyun int i;
1144*4882a593Smuzhiyun struct i2c_msg *msg, *next_msg;
1145*4882a593Smuzhiyun int addr, ret;
1146*4882a593Smuzhiyun u16 len;
1147*4882a593Smuzhiyun u32 word;
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun pt1 = i2c_get_adapdata(adap);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun for (i = 0; i < num; i++) {
1152*4882a593Smuzhiyun msg = &msgs[i];
1153*4882a593Smuzhiyun if (msg->flags & I2C_M_RD)
1154*4882a593Smuzhiyun return -ENOTSUPP;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun if (i + 1 < num)
1157*4882a593Smuzhiyun next_msg = &msgs[i + 1];
1158*4882a593Smuzhiyun else
1159*4882a593Smuzhiyun next_msg = NULL;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun if (next_msg && next_msg->flags & I2C_M_RD) {
1162*4882a593Smuzhiyun i++;
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun len = next_msg->len;
1165*4882a593Smuzhiyun if (len > 4)
1166*4882a593Smuzhiyun return -ENOTSUPP;
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun pt1_i2c_begin(pt1, &addr);
1169*4882a593Smuzhiyun pt1_i2c_write_msg(pt1, addr, &addr, msg);
1170*4882a593Smuzhiyun pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
1171*4882a593Smuzhiyun ret = pt1_i2c_end(pt1, addr);
1172*4882a593Smuzhiyun if (ret < 0)
1173*4882a593Smuzhiyun return ret;
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun word = pt1_read_reg(pt1, 2);
1176*4882a593Smuzhiyun while (len--) {
1177*4882a593Smuzhiyun next_msg->buf[len] = word;
1178*4882a593Smuzhiyun word >>= 8;
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun } else {
1181*4882a593Smuzhiyun pt1_i2c_begin(pt1, &addr);
1182*4882a593Smuzhiyun pt1_i2c_write_msg(pt1, addr, &addr, msg);
1183*4882a593Smuzhiyun ret = pt1_i2c_end(pt1, addr);
1184*4882a593Smuzhiyun if (ret < 0)
1185*4882a593Smuzhiyun return ret;
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun return num;
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
pt1_i2c_func(struct i2c_adapter * adap)1192*4882a593Smuzhiyun static u32 pt1_i2c_func(struct i2c_adapter *adap)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun return I2C_FUNC_I2C;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun static const struct i2c_algorithm pt1_i2c_algo = {
1198*4882a593Smuzhiyun .master_xfer = pt1_i2c_xfer,
1199*4882a593Smuzhiyun .functionality = pt1_i2c_func,
1200*4882a593Smuzhiyun };
1201*4882a593Smuzhiyun
pt1_i2c_wait(struct pt1 * pt1)1202*4882a593Smuzhiyun static void pt1_i2c_wait(struct pt1 *pt1)
1203*4882a593Smuzhiyun {
1204*4882a593Smuzhiyun int i;
1205*4882a593Smuzhiyun for (i = 0; i < 128; i++)
1206*4882a593Smuzhiyun pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun
pt1_i2c_init(struct pt1 * pt1)1209*4882a593Smuzhiyun static void pt1_i2c_init(struct pt1 *pt1)
1210*4882a593Smuzhiyun {
1211*4882a593Smuzhiyun int i;
1212*4882a593Smuzhiyun for (i = 0; i < 1024; i++)
1213*4882a593Smuzhiyun pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
1217*4882a593Smuzhiyun
pt1_suspend(struct device * dev)1218*4882a593Smuzhiyun static int pt1_suspend(struct device *dev)
1219*4882a593Smuzhiyun {
1220*4882a593Smuzhiyun struct pt1 *pt1 = dev_get_drvdata(dev);
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun pt1_init_streams(pt1);
1223*4882a593Smuzhiyun pt1_disable_ram(pt1);
1224*4882a593Smuzhiyun pt1->power = 0;
1225*4882a593Smuzhiyun pt1->reset = 1;
1226*4882a593Smuzhiyun pt1_update_power(pt1);
1227*4882a593Smuzhiyun return 0;
1228*4882a593Smuzhiyun }
1229*4882a593Smuzhiyun
pt1_resume(struct device * dev)1230*4882a593Smuzhiyun static int pt1_resume(struct device *dev)
1231*4882a593Smuzhiyun {
1232*4882a593Smuzhiyun struct pt1 *pt1 = dev_get_drvdata(dev);
1233*4882a593Smuzhiyun int ret;
1234*4882a593Smuzhiyun int i;
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun pt1->power = 0;
1237*4882a593Smuzhiyun pt1->reset = 1;
1238*4882a593Smuzhiyun pt1_update_power(pt1);
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun pt1_i2c_init(pt1);
1241*4882a593Smuzhiyun pt1_i2c_wait(pt1);
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun ret = pt1_sync(pt1);
1244*4882a593Smuzhiyun if (ret < 0)
1245*4882a593Smuzhiyun goto resume_err;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun pt1_identify(pt1);
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun ret = pt1_unlock(pt1);
1250*4882a593Smuzhiyun if (ret < 0)
1251*4882a593Smuzhiyun goto resume_err;
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun ret = pt1_reset_pci(pt1);
1254*4882a593Smuzhiyun if (ret < 0)
1255*4882a593Smuzhiyun goto resume_err;
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun ret = pt1_reset_ram(pt1);
1258*4882a593Smuzhiyun if (ret < 0)
1259*4882a593Smuzhiyun goto resume_err;
1260*4882a593Smuzhiyun
1261*4882a593Smuzhiyun ret = pt1_enable_ram(pt1);
1262*4882a593Smuzhiyun if (ret < 0)
1263*4882a593Smuzhiyun goto resume_err;
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun pt1_init_streams(pt1);
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun pt1->power = 1;
1268*4882a593Smuzhiyun pt1_update_power(pt1);
1269*4882a593Smuzhiyun msleep(20);
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun pt1->reset = 0;
1272*4882a593Smuzhiyun pt1_update_power(pt1);
1273*4882a593Smuzhiyun usleep_range(1000, 2000);
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun ret = pt1_demod_block_init(pt1);
1276*4882a593Smuzhiyun if (ret < 0)
1277*4882a593Smuzhiyun goto resume_err;
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++)
1280*4882a593Smuzhiyun dvb_frontend_reinitialise(pt1->adaps[i]->fe);
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun pt1_init_table_count(pt1);
1283*4882a593Smuzhiyun for (i = 0; i < pt1_nr_tables; i++) {
1284*4882a593Smuzhiyun int j;
1285*4882a593Smuzhiyun
1286*4882a593Smuzhiyun for (j = 0; j < PT1_NR_BUFS; j++)
1287*4882a593Smuzhiyun pt1->tables[i].bufs[j].page->upackets[PT1_NR_UPACKETS-1]
1288*4882a593Smuzhiyun = 0;
1289*4882a593Smuzhiyun pt1_increment_table_count(pt1);
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun pt1_register_tables(pt1, pt1->tables[0].addr >> PT1_PAGE_SHIFT);
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun pt1->table_index = 0;
1294*4882a593Smuzhiyun pt1->buf_index = 0;
1295*4882a593Smuzhiyun for (i = 0; i < PT1_NR_ADAPS; i++) {
1296*4882a593Smuzhiyun pt1->adaps[i]->upacket_count = 0;
1297*4882a593Smuzhiyun pt1->adaps[i]->packet_count = 0;
1298*4882a593Smuzhiyun pt1->adaps[i]->st_count = -1;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun return 0;
1302*4882a593Smuzhiyun
1303*4882a593Smuzhiyun resume_err:
1304*4882a593Smuzhiyun dev_info(&pt1->pdev->dev, "failed to resume PT1/PT2.");
1305*4882a593Smuzhiyun return 0; /* resume anyway */
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1309*4882a593Smuzhiyun
pt1_remove(struct pci_dev * pdev)1310*4882a593Smuzhiyun static void pt1_remove(struct pci_dev *pdev)
1311*4882a593Smuzhiyun {
1312*4882a593Smuzhiyun struct pt1 *pt1;
1313*4882a593Smuzhiyun void __iomem *regs;
1314*4882a593Smuzhiyun
1315*4882a593Smuzhiyun pt1 = pci_get_drvdata(pdev);
1316*4882a593Smuzhiyun regs = pt1->regs;
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun if (pt1->kthread)
1319*4882a593Smuzhiyun kthread_stop(pt1->kthread);
1320*4882a593Smuzhiyun pt1_cleanup_tables(pt1);
1321*4882a593Smuzhiyun pt1_cleanup_frontends(pt1);
1322*4882a593Smuzhiyun pt1_disable_ram(pt1);
1323*4882a593Smuzhiyun pt1->power = 0;
1324*4882a593Smuzhiyun pt1->reset = 1;
1325*4882a593Smuzhiyun pt1_update_power(pt1);
1326*4882a593Smuzhiyun pt1_cleanup_adapters(pt1);
1327*4882a593Smuzhiyun i2c_del_adapter(&pt1->i2c_adap);
1328*4882a593Smuzhiyun kfree(pt1);
1329*4882a593Smuzhiyun pci_iounmap(pdev, regs);
1330*4882a593Smuzhiyun pci_release_regions(pdev);
1331*4882a593Smuzhiyun pci_disable_device(pdev);
1332*4882a593Smuzhiyun }
1333*4882a593Smuzhiyun
pt1_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1334*4882a593Smuzhiyun static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1335*4882a593Smuzhiyun {
1336*4882a593Smuzhiyun int ret;
1337*4882a593Smuzhiyun void __iomem *regs;
1338*4882a593Smuzhiyun struct pt1 *pt1;
1339*4882a593Smuzhiyun struct i2c_adapter *i2c_adap;
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun ret = pci_enable_device(pdev);
1342*4882a593Smuzhiyun if (ret < 0)
1343*4882a593Smuzhiyun goto err;
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1346*4882a593Smuzhiyun if (ret < 0)
1347*4882a593Smuzhiyun goto err_pci_disable_device;
1348*4882a593Smuzhiyun
1349*4882a593Smuzhiyun pci_set_master(pdev);
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun ret = pci_request_regions(pdev, DRIVER_NAME);
1352*4882a593Smuzhiyun if (ret < 0)
1353*4882a593Smuzhiyun goto err_pci_disable_device;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun regs = pci_iomap(pdev, 0, 0);
1356*4882a593Smuzhiyun if (!regs) {
1357*4882a593Smuzhiyun ret = -EIO;
1358*4882a593Smuzhiyun goto err_pci_release_regions;
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
1362*4882a593Smuzhiyun if (!pt1) {
1363*4882a593Smuzhiyun ret = -ENOMEM;
1364*4882a593Smuzhiyun goto err_pci_iounmap;
1365*4882a593Smuzhiyun }
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun mutex_init(&pt1->lock);
1368*4882a593Smuzhiyun pt1->pdev = pdev;
1369*4882a593Smuzhiyun pt1->regs = regs;
1370*4882a593Smuzhiyun pt1->fe_clk = (pdev->device == 0x211a) ?
1371*4882a593Smuzhiyun PT1_FE_CLK_20MHZ : PT1_FE_CLK_25MHZ;
1372*4882a593Smuzhiyun pci_set_drvdata(pdev, pt1);
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun ret = pt1_init_adapters(pt1);
1375*4882a593Smuzhiyun if (ret < 0)
1376*4882a593Smuzhiyun goto err_kfree;
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun mutex_init(&pt1->lock);
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun pt1->power = 0;
1381*4882a593Smuzhiyun pt1->reset = 1;
1382*4882a593Smuzhiyun pt1_update_power(pt1);
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun i2c_adap = &pt1->i2c_adap;
1385*4882a593Smuzhiyun i2c_adap->algo = &pt1_i2c_algo;
1386*4882a593Smuzhiyun i2c_adap->algo_data = NULL;
1387*4882a593Smuzhiyun i2c_adap->dev.parent = &pdev->dev;
1388*4882a593Smuzhiyun strscpy(i2c_adap->name, DRIVER_NAME, sizeof(i2c_adap->name));
1389*4882a593Smuzhiyun i2c_set_adapdata(i2c_adap, pt1);
1390*4882a593Smuzhiyun ret = i2c_add_adapter(i2c_adap);
1391*4882a593Smuzhiyun if (ret < 0)
1392*4882a593Smuzhiyun goto err_pt1_cleanup_adapters;
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun pt1_i2c_init(pt1);
1395*4882a593Smuzhiyun pt1_i2c_wait(pt1);
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun ret = pt1_sync(pt1);
1398*4882a593Smuzhiyun if (ret < 0)
1399*4882a593Smuzhiyun goto err_i2c_del_adapter;
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun pt1_identify(pt1);
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun ret = pt1_unlock(pt1);
1404*4882a593Smuzhiyun if (ret < 0)
1405*4882a593Smuzhiyun goto err_i2c_del_adapter;
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun ret = pt1_reset_pci(pt1);
1408*4882a593Smuzhiyun if (ret < 0)
1409*4882a593Smuzhiyun goto err_i2c_del_adapter;
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun ret = pt1_reset_ram(pt1);
1412*4882a593Smuzhiyun if (ret < 0)
1413*4882a593Smuzhiyun goto err_i2c_del_adapter;
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun ret = pt1_enable_ram(pt1);
1416*4882a593Smuzhiyun if (ret < 0)
1417*4882a593Smuzhiyun goto err_i2c_del_adapter;
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun pt1_init_streams(pt1);
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun pt1->power = 1;
1422*4882a593Smuzhiyun pt1_update_power(pt1);
1423*4882a593Smuzhiyun msleep(20);
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun pt1->reset = 0;
1426*4882a593Smuzhiyun pt1_update_power(pt1);
1427*4882a593Smuzhiyun usleep_range(1000, 2000);
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun ret = pt1_init_frontends(pt1);
1430*4882a593Smuzhiyun if (ret < 0)
1431*4882a593Smuzhiyun goto err_pt1_disable_ram;
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun ret = pt1_init_tables(pt1);
1434*4882a593Smuzhiyun if (ret < 0)
1435*4882a593Smuzhiyun goto err_pt1_cleanup_frontends;
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun return 0;
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun err_pt1_cleanup_frontends:
1440*4882a593Smuzhiyun pt1_cleanup_frontends(pt1);
1441*4882a593Smuzhiyun err_pt1_disable_ram:
1442*4882a593Smuzhiyun pt1_disable_ram(pt1);
1443*4882a593Smuzhiyun pt1->power = 0;
1444*4882a593Smuzhiyun pt1->reset = 1;
1445*4882a593Smuzhiyun pt1_update_power(pt1);
1446*4882a593Smuzhiyun err_i2c_del_adapter:
1447*4882a593Smuzhiyun i2c_del_adapter(i2c_adap);
1448*4882a593Smuzhiyun err_pt1_cleanup_adapters:
1449*4882a593Smuzhiyun pt1_cleanup_adapters(pt1);
1450*4882a593Smuzhiyun err_kfree:
1451*4882a593Smuzhiyun kfree(pt1);
1452*4882a593Smuzhiyun err_pci_iounmap:
1453*4882a593Smuzhiyun pci_iounmap(pdev, regs);
1454*4882a593Smuzhiyun err_pci_release_regions:
1455*4882a593Smuzhiyun pci_release_regions(pdev);
1456*4882a593Smuzhiyun err_pci_disable_device:
1457*4882a593Smuzhiyun pci_disable_device(pdev);
1458*4882a593Smuzhiyun err:
1459*4882a593Smuzhiyun return ret;
1460*4882a593Smuzhiyun
1461*4882a593Smuzhiyun }
1462*4882a593Smuzhiyun
1463*4882a593Smuzhiyun static const struct pci_device_id pt1_id_table[] = {
1464*4882a593Smuzhiyun { PCI_DEVICE(0x10ee, 0x211a) },
1465*4882a593Smuzhiyun { PCI_DEVICE(0x10ee, 0x222a) },
1466*4882a593Smuzhiyun { },
1467*4882a593Smuzhiyun };
1468*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pt1_id_table);
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(pt1_pm_ops, pt1_suspend, pt1_resume);
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun static struct pci_driver pt1_driver = {
1473*4882a593Smuzhiyun .name = DRIVER_NAME,
1474*4882a593Smuzhiyun .probe = pt1_probe,
1475*4882a593Smuzhiyun .remove = pt1_remove,
1476*4882a593Smuzhiyun .id_table = pt1_id_table,
1477*4882a593Smuzhiyun .driver.pm = &pt1_pm_ops,
1478*4882a593Smuzhiyun };
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun module_pci_driver(pt1_driver);
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
1483*4882a593Smuzhiyun MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
1484*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1485