xref: /OK3568_Linux_fs/kernel/drivers/media/pci/mantis/mantis_uart.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun 	Mantis PCI bridge driver
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun 	Copyright (C) Manu Abraham (abraham.manu@gmail.com)
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/spinlock.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/signal.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/pci.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <media/dmxdev.h>
19*4882a593Smuzhiyun #include <media/dvbdev.h>
20*4882a593Smuzhiyun #include <media/dvb_demux.h>
21*4882a593Smuzhiyun #include <media/dvb_frontend.h>
22*4882a593Smuzhiyun #include <media/dvb_net.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "mantis_common.h"
25*4882a593Smuzhiyun #include "mantis_reg.h"
26*4882a593Smuzhiyun #include "mantis_uart.h"
27*4882a593Smuzhiyun #include "mantis_input.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct mantis_uart_params {
30*4882a593Smuzhiyun 	enum mantis_baud	baud_rate;
31*4882a593Smuzhiyun 	enum mantis_parity	parity;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static struct {
35*4882a593Smuzhiyun 	char string[7];
36*4882a593Smuzhiyun } rates[5] = {
37*4882a593Smuzhiyun 	{ "9600" },
38*4882a593Smuzhiyun 	{ "19200" },
39*4882a593Smuzhiyun 	{ "38400" },
40*4882a593Smuzhiyun 	{ "57600" },
41*4882a593Smuzhiyun 	{ "115200" }
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun static struct {
45*4882a593Smuzhiyun 	char string[5];
46*4882a593Smuzhiyun } parity[3] = {
47*4882a593Smuzhiyun 	{ "NONE" },
48*4882a593Smuzhiyun 	{ "ODD" },
49*4882a593Smuzhiyun 	{ "EVEN" }
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
mantis_uart_read(struct mantis_pci * mantis)52*4882a593Smuzhiyun static void mantis_uart_read(struct mantis_pci *mantis)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	struct mantis_hwconfig *config = mantis->hwconfig;
55*4882a593Smuzhiyun 	int i, scancode = 0, err = 0;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* get data */
58*4882a593Smuzhiyun 	dprintk(MANTIS_DEBUG, 1, "UART Reading ...");
59*4882a593Smuzhiyun 	for (i = 0; i < (config->bytes + 1); i++) {
60*4882a593Smuzhiyun 		int data = mmread(MANTIS_UART_RXD);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 		dprintk(MANTIS_DEBUG, 0, " <%02x>", data);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 		scancode = (scancode << 8) | (data & 0x3f);
65*4882a593Smuzhiyun 		err |= data;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 		if (data & (1 << 7))
68*4882a593Smuzhiyun 			dprintk(MANTIS_ERROR, 1, "UART framing error");
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 		if (data & (1 << 6))
71*4882a593Smuzhiyun 			dprintk(MANTIS_ERROR, 1, "UART parity error");
72*4882a593Smuzhiyun 	}
73*4882a593Smuzhiyun 	dprintk(MANTIS_DEBUG, 0, "\n");
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	if ((err & 0xC0) == 0)
76*4882a593Smuzhiyun 		mantis_input_process(mantis, scancode);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
mantis_uart_work(struct work_struct * work)79*4882a593Smuzhiyun static void mantis_uart_work(struct work_struct *work)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	struct mantis_pci *mantis = container_of(work, struct mantis_pci, uart_work);
82*4882a593Smuzhiyun 	u32 stat;
83*4882a593Smuzhiyun 	unsigned long timeout;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	stat = mmread(MANTIS_UART_STAT);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	if (stat & MANTIS_UART_RXFIFO_FULL)
88*4882a593Smuzhiyun 		dprintk(MANTIS_ERROR, 1, "RX Fifo FULL");
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/*
91*4882a593Smuzhiyun 	 * MANTIS_UART_RXFIFO_DATA is only set if at least
92*4882a593Smuzhiyun 	 * config->bytes + 1 bytes are in the FIFO.
93*4882a593Smuzhiyun 	 */
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* FIXME: is 10ms good enough ? */
96*4882a593Smuzhiyun 	timeout = jiffies +  msecs_to_jiffies(10);
97*4882a593Smuzhiyun 	while (stat & MANTIS_UART_RXFIFO_DATA) {
98*4882a593Smuzhiyun 		mantis_uart_read(mantis);
99*4882a593Smuzhiyun 		stat = mmread(MANTIS_UART_STAT);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 		if (!time_is_after_jiffies(timeout))
102*4882a593Smuzhiyun 			break;
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* re-enable UART (RX) interrupt */
106*4882a593Smuzhiyun 	mantis_unmask_ints(mantis, MANTIS_INT_IRQ1);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
mantis_uart_setup(struct mantis_pci * mantis,struct mantis_uart_params * params)109*4882a593Smuzhiyun static int mantis_uart_setup(struct mantis_pci *mantis,
110*4882a593Smuzhiyun 			     struct mantis_uart_params *params)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	u32 reg;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	mmwrite((mmread(MANTIS_UART_CTL) | (params->parity & 0x3)), MANTIS_UART_CTL);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	reg = mmread(MANTIS_UART_BAUD);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	switch (params->baud_rate) {
119*4882a593Smuzhiyun 	case MANTIS_BAUD_9600:
120*4882a593Smuzhiyun 		reg |= 0xd8;
121*4882a593Smuzhiyun 		break;
122*4882a593Smuzhiyun 	case MANTIS_BAUD_19200:
123*4882a593Smuzhiyun 		reg |= 0x6c;
124*4882a593Smuzhiyun 		break;
125*4882a593Smuzhiyun 	case MANTIS_BAUD_38400:
126*4882a593Smuzhiyun 		reg |= 0x36;
127*4882a593Smuzhiyun 		break;
128*4882a593Smuzhiyun 	case MANTIS_BAUD_57600:
129*4882a593Smuzhiyun 		reg |= 0x23;
130*4882a593Smuzhiyun 		break;
131*4882a593Smuzhiyun 	case MANTIS_BAUD_115200:
132*4882a593Smuzhiyun 		reg |= 0x11;
133*4882a593Smuzhiyun 		break;
134*4882a593Smuzhiyun 	default:
135*4882a593Smuzhiyun 		return -EINVAL;
136*4882a593Smuzhiyun 	}
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	mmwrite(reg, MANTIS_UART_BAUD);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
mantis_uart_init(struct mantis_pci * mantis)143*4882a593Smuzhiyun int mantis_uart_init(struct mantis_pci *mantis)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct mantis_hwconfig *config = mantis->hwconfig;
146*4882a593Smuzhiyun 	struct mantis_uart_params params;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* default parity: */
149*4882a593Smuzhiyun 	params.baud_rate = config->baud_rate;
150*4882a593Smuzhiyun 	params.parity = config->parity;
151*4882a593Smuzhiyun 	dprintk(MANTIS_INFO, 1, "Initializing UART @ %sbps parity:%s",
152*4882a593Smuzhiyun 		rates[params.baud_rate].string,
153*4882a593Smuzhiyun 		parity[params.parity].string);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	INIT_WORK(&mantis->uart_work, mantis_uart_work);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* disable interrupt */
158*4882a593Smuzhiyun 	mmwrite(mmread(MANTIS_UART_CTL) & 0xffef, MANTIS_UART_CTL);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	mantis_uart_setup(mantis, &params);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	/* default 1 byte */
163*4882a593Smuzhiyun 	mmwrite((mmread(MANTIS_UART_BAUD) | (config->bytes << 8)), MANTIS_UART_BAUD);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	/* flush buffer */
166*4882a593Smuzhiyun 	mmwrite((mmread(MANTIS_UART_CTL) | MANTIS_UART_RXFLUSH), MANTIS_UART_CTL);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* enable interrupt */
169*4882a593Smuzhiyun 	mmwrite(mmread(MANTIS_UART_CTL) | MANTIS_UART_RXINT, MANTIS_UART_CTL);
170*4882a593Smuzhiyun 	mantis_unmask_ints(mantis, MANTIS_INT_IRQ1);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	schedule_work(&mantis->uart_work);
173*4882a593Smuzhiyun 	dprintk(MANTIS_DEBUG, 1, "UART successfully initialized");
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mantis_uart_init);
178*4882a593Smuzhiyun 
mantis_uart_exit(struct mantis_pci * mantis)179*4882a593Smuzhiyun void mantis_uart_exit(struct mantis_pci *mantis)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	/* disable interrupt */
182*4882a593Smuzhiyun 	mantis_mask_ints(mantis, MANTIS_INT_IRQ1);
183*4882a593Smuzhiyun 	mmwrite(mmread(MANTIS_UART_CTL) & 0xffef, MANTIS_UART_CTL);
184*4882a593Smuzhiyun 	flush_work(&mantis->uart_work);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mantis_uart_exit);
187