1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun Mantis PCI bridge driver
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun Copyright (C) Manu Abraham (abraham.manu@gmail.com)
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/signal.h>
11*4882a593Smuzhiyun #include <linux/sched.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <media/dmxdev.h>
17*4882a593Smuzhiyun #include <media/dvbdev.h>
18*4882a593Smuzhiyun #include <media/dvb_demux.h>
19*4882a593Smuzhiyun #include <media/dvb_frontend.h>
20*4882a593Smuzhiyun #include <media/dvb_net.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include "mantis_common.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "mantis_hif.h"
25*4882a593Smuzhiyun #include "mantis_link.h" /* temporary due to physical layer stuff */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "mantis_reg.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
mantis_hif_sbuf_opdone_wait(struct mantis_ca * ca)30*4882a593Smuzhiyun static int mantis_hif_sbuf_opdone_wait(struct mantis_ca *ca)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
33*4882a593Smuzhiyun int rc = 0;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun if (wait_event_timeout(ca->hif_opdone_wq,
36*4882a593Smuzhiyun ca->hif_event & MANTIS_SBUF_OPDONE,
37*4882a593Smuzhiyun msecs_to_jiffies(500)) == -ERESTARTSYS) {
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Smart buffer operation timeout !", mantis->num);
40*4882a593Smuzhiyun rc = -EREMOTEIO;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Smart Buffer Operation complete");
43*4882a593Smuzhiyun ca->hif_event &= ~MANTIS_SBUF_OPDONE;
44*4882a593Smuzhiyun return rc;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
mantis_hif_write_wait(struct mantis_ca * ca)47*4882a593Smuzhiyun static int mantis_hif_write_wait(struct mantis_ca *ca)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
50*4882a593Smuzhiyun u32 opdone = 0, timeout = 0;
51*4882a593Smuzhiyun int rc = 0;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (wait_event_timeout(ca->hif_write_wq,
54*4882a593Smuzhiyun mantis->gpif_status & MANTIS_GPIF_WRACK,
55*4882a593Smuzhiyun msecs_to_jiffies(500)) == -ERESTARTSYS) {
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write ACK timed out !", mantis->num);
58*4882a593Smuzhiyun rc = -EREMOTEIO;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Write Acknowledged");
61*4882a593Smuzhiyun mantis->gpif_status &= ~MANTIS_GPIF_WRACK;
62*4882a593Smuzhiyun while (!opdone) {
63*4882a593Smuzhiyun opdone = (mmread(MANTIS_GPIF_STATUS) & MANTIS_SBUF_OPDONE);
64*4882a593Smuzhiyun udelay(500);
65*4882a593Smuzhiyun timeout++;
66*4882a593Smuzhiyun if (timeout > 100) {
67*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): Write operation timed out!", mantis->num);
68*4882a593Smuzhiyun rc = -ETIMEDOUT;
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "HIF Write success");
73*4882a593Smuzhiyun return rc;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun
mantis_hif_read_mem(struct mantis_ca * ca,u32 addr)77*4882a593Smuzhiyun int mantis_hif_read_mem(struct mantis_ca *ca, u32 addr)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
80*4882a593Smuzhiyun u32 hif_addr = 0, data, count = 4;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Read", mantis->num);
83*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
84*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
85*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
86*4882a593Smuzhiyun hif_addr |= MANTIS_HIF_STATUS;
87*4882a593Smuzhiyun hif_addr |= addr;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
90*4882a593Smuzhiyun mmwrite(count, MANTIS_GPIF_BRBYTES);
91*4882a593Smuzhiyun udelay(20);
92*4882a593Smuzhiyun mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
95*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): GPIF Smart Buffer operation failed", mantis->num);
96*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
97*4882a593Smuzhiyun return -EREMOTEIO;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun data = mmread(MANTIS_GPIF_DIN);
100*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
101*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Mem Read: 0x%02x", data);
102*4882a593Smuzhiyun return (data >> 24) & 0xff;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
mantis_hif_write_mem(struct mantis_ca * ca,u32 addr,u8 data)105*4882a593Smuzhiyun int mantis_hif_write_mem(struct mantis_ca *ca, u32 addr, u8 data)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct mantis_slot *slot = ca->slot;
108*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
109*4882a593Smuzhiyun u32 hif_addr = 0;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF Mem Write", mantis->num);
112*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
113*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
114*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
115*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAIOM;
116*4882a593Smuzhiyun hif_addr |= MANTIS_HIF_STATUS;
117*4882a593Smuzhiyun hif_addr |= addr;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun mmwrite(slot->slave_cfg, MANTIS_GPIF_CFGSLA); /* Slot0 alone for now */
120*4882a593Smuzhiyun mmwrite(hif_addr, MANTIS_GPIF_ADDR);
121*4882a593Smuzhiyun mmwrite(data, MANTIS_GPIF_DOUT);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (mantis_hif_write_wait(ca) != 0) {
124*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
125*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
126*4882a593Smuzhiyun return -EREMOTEIO;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Mem Write: (0x%02x to 0x%02x)", data, addr);
129*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
mantis_hif_read_iom(struct mantis_ca * ca,u32 addr)134*4882a593Smuzhiyun int mantis_hif_read_iom(struct mantis_ca *ca, u32 addr)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
137*4882a593Smuzhiyun u32 data, hif_addr = 0;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Read", mantis->num);
140*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
141*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
142*4882a593Smuzhiyun hif_addr |= MANTIS_GPIF_PCMCIAIOM;
143*4882a593Smuzhiyun hif_addr |= MANTIS_HIF_STATUS;
144*4882a593Smuzhiyun hif_addr |= addr;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun mmwrite(hif_addr, MANTIS_GPIF_BRADDR);
147*4882a593Smuzhiyun mmwrite(1, MANTIS_GPIF_BRBYTES);
148*4882a593Smuzhiyun udelay(20);
149*4882a593Smuzhiyun mmwrite(hif_addr | MANTIS_GPIF_HIFRDWRN, MANTIS_GPIF_ADDR);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun if (mantis_hif_sbuf_opdone_wait(ca) != 0) {
152*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
153*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
154*4882a593Smuzhiyun return -EREMOTEIO;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun data = mmread(MANTIS_GPIF_DIN);
157*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "I/O Read: 0x%02x", data);
158*4882a593Smuzhiyun udelay(50);
159*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun return (u8) data;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
mantis_hif_write_iom(struct mantis_ca * ca,u32 addr,u8 data)164*4882a593Smuzhiyun int mantis_hif_write_iom(struct mantis_ca *ca, u32 addr, u8 data)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
167*4882a593Smuzhiyun u32 hif_addr = 0;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "Adapter(%d) Slot(0): Request HIF I/O Write", mantis->num);
170*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
171*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_PCMCIAREG;
172*4882a593Smuzhiyun hif_addr &= ~MANTIS_GPIF_HIFRDWRN;
173*4882a593Smuzhiyun hif_addr |= MANTIS_GPIF_PCMCIAIOM;
174*4882a593Smuzhiyun hif_addr |= MANTIS_HIF_STATUS;
175*4882a593Smuzhiyun hif_addr |= addr;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun mmwrite(hif_addr, MANTIS_GPIF_ADDR);
178*4882a593Smuzhiyun mmwrite(data, MANTIS_GPIF_DOUT);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun if (mantis_hif_write_wait(ca) != 0) {
181*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Slot(0): HIF Smart Buffer operation failed", mantis->num);
182*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
183*4882a593Smuzhiyun return -EREMOTEIO;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun dprintk(MANTIS_DEBUG, 1, "I/O Write: (0x%02x to 0x%02x)", data, addr);
186*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
187*4882a593Smuzhiyun udelay(50);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
mantis_hif_init(struct mantis_ca * ca)192*4882a593Smuzhiyun int mantis_hif_init(struct mantis_ca *ca)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct mantis_slot *slot = ca->slot;
195*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
196*4882a593Smuzhiyun u32 irqcfg;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun slot[0].slave_cfg = 0x70773028;
199*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Initializing Mantis Host Interface", mantis->num);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
202*4882a593Smuzhiyun irqcfg = mmread(MANTIS_GPIF_IRQCFG);
203*4882a593Smuzhiyun irqcfg = MANTIS_MASK_BRRDY |
204*4882a593Smuzhiyun MANTIS_MASK_WRACK |
205*4882a593Smuzhiyun MANTIS_MASK_EXTIRQ |
206*4882a593Smuzhiyun MANTIS_MASK_WSTO |
207*4882a593Smuzhiyun MANTIS_MASK_OTHERR |
208*4882a593Smuzhiyun MANTIS_MASK_OVFLW;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
211*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun return 0;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
mantis_hif_exit(struct mantis_ca * ca)216*4882a593Smuzhiyun void mantis_hif_exit(struct mantis_ca *ca)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct mantis_pci *mantis = ca->ca_priv;
219*4882a593Smuzhiyun u32 irqcfg;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun dprintk(MANTIS_ERROR, 1, "Adapter(%d) Exiting Mantis Host Interface", mantis->num);
222*4882a593Smuzhiyun mutex_lock(&ca->ca_lock);
223*4882a593Smuzhiyun irqcfg = mmread(MANTIS_GPIF_IRQCFG);
224*4882a593Smuzhiyun irqcfg &= ~MANTIS_MASK_BRRDY;
225*4882a593Smuzhiyun mmwrite(irqcfg, MANTIS_GPIF_IRQCFG);
226*4882a593Smuzhiyun mutex_unlock(&ca->ca_lock);
227*4882a593Smuzhiyun }
228