xref: /OK3568_Linux_fs/kernel/drivers/media/pci/ivtv/ivtv-yuv.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun     yuv support
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun     Copyright (C) 2007  Ian Armstrong <ian@iarmst.demon.co.uk>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "ivtv-driver.h"
10*4882a593Smuzhiyun #include "ivtv-udma.h"
11*4882a593Smuzhiyun #include "ivtv-yuv.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /* YUV buffer offsets */
14*4882a593Smuzhiyun const u32 yuv_offset[IVTV_YUV_BUFFERS] = {
15*4882a593Smuzhiyun 	0x001a8600,
16*4882a593Smuzhiyun 	0x00240400,
17*4882a593Smuzhiyun 	0x002d8200,
18*4882a593Smuzhiyun 	0x00370000,
19*4882a593Smuzhiyun 	0x00029000,
20*4882a593Smuzhiyun 	0x000C0E00,
21*4882a593Smuzhiyun 	0x006B0400,
22*4882a593Smuzhiyun 	0x00748200
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun 
ivtv_yuv_prep_user_dma(struct ivtv * itv,struct ivtv_user_dma * dma,struct ivtv_dma_frame * args)25*4882a593Smuzhiyun static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
26*4882a593Smuzhiyun 				  struct ivtv_dma_frame *args)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	struct ivtv_dma_page_info y_dma;
29*4882a593Smuzhiyun 	struct ivtv_dma_page_info uv_dma;
30*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
31*4882a593Smuzhiyun 	u8 frame = yi->draw_frame;
32*4882a593Smuzhiyun 	struct yuv_frame_info *f = &yi->new_frame_info[frame];
33*4882a593Smuzhiyun 	int y_pages, uv_pages;
34*4882a593Smuzhiyun 	unsigned long y_buffer_offset, uv_buffer_offset;
35*4882a593Smuzhiyun 	int y_decode_height, uv_decode_height, y_size;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	y_buffer_offset = IVTV_DECODER_OFFSET + yuv_offset[frame];
38*4882a593Smuzhiyun 	uv_buffer_offset = y_buffer_offset + IVTV_YUV_BUFFER_UV_OFFSET;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	y_decode_height = uv_decode_height = f->src_h + f->src_y;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	if (f->offset_y)
43*4882a593Smuzhiyun 		y_buffer_offset += 720 * 16;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	if (y_decode_height & 15)
46*4882a593Smuzhiyun 		y_decode_height = (y_decode_height + 16) & ~15;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	if (uv_decode_height & 31)
49*4882a593Smuzhiyun 		uv_decode_height = (uv_decode_height + 32) & ~31;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	y_size = 720 * y_decode_height;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	/* Still in USE */
54*4882a593Smuzhiyun 	if (dma->SG_length || dma->page_count) {
55*4882a593Smuzhiyun 		IVTV_DEBUG_WARN
56*4882a593Smuzhiyun 		    ("prep_user_dma: SG_length %d page_count %d still full?\n",
57*4882a593Smuzhiyun 		     dma->SG_length, dma->page_count);
58*4882a593Smuzhiyun 		return -EBUSY;
59*4882a593Smuzhiyun 	}
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	ivtv_udma_get_page_info (&y_dma, (unsigned long)args->y_source, 720 * y_decode_height);
62*4882a593Smuzhiyun 	ivtv_udma_get_page_info (&uv_dma, (unsigned long)args->uv_source, 360 * uv_decode_height);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	/* Pin user pages for DMA Xfer */
65*4882a593Smuzhiyun 	y_pages = pin_user_pages_unlocked(y_dma.uaddr,
66*4882a593Smuzhiyun 			y_dma.page_count, &dma->map[0], FOLL_FORCE);
67*4882a593Smuzhiyun 	uv_pages = 0; /* silence gcc. value is set and consumed only if: */
68*4882a593Smuzhiyun 	if (y_pages == y_dma.page_count) {
69*4882a593Smuzhiyun 		uv_pages = pin_user_pages_unlocked(uv_dma.uaddr,
70*4882a593Smuzhiyun 				uv_dma.page_count, &dma->map[y_pages],
71*4882a593Smuzhiyun 				FOLL_FORCE);
72*4882a593Smuzhiyun 	}
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	if (y_pages != y_dma.page_count || uv_pages != uv_dma.page_count) {
75*4882a593Smuzhiyun 		int rc = -EFAULT;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 		if (y_pages == y_dma.page_count) {
78*4882a593Smuzhiyun 			IVTV_DEBUG_WARN
79*4882a593Smuzhiyun 				("failed to map uv user pages, returned %d expecting %d\n",
80*4882a593Smuzhiyun 				 uv_pages, uv_dma.page_count);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 			if (uv_pages >= 0) {
83*4882a593Smuzhiyun 				unpin_user_pages(&dma->map[y_pages], uv_pages);
84*4882a593Smuzhiyun 				rc = -EFAULT;
85*4882a593Smuzhiyun 			} else {
86*4882a593Smuzhiyun 				rc = uv_pages;
87*4882a593Smuzhiyun 			}
88*4882a593Smuzhiyun 		} else {
89*4882a593Smuzhiyun 			IVTV_DEBUG_WARN
90*4882a593Smuzhiyun 				("failed to map y user pages, returned %d expecting %d\n",
91*4882a593Smuzhiyun 				 y_pages, y_dma.page_count);
92*4882a593Smuzhiyun 		}
93*4882a593Smuzhiyun 		if (y_pages >= 0) {
94*4882a593Smuzhiyun 			unpin_user_pages(dma->map, y_pages);
95*4882a593Smuzhiyun 			/*
96*4882a593Smuzhiyun 			 * Inherit the -EFAULT from rc's
97*4882a593Smuzhiyun 			 * initialization, but allow it to be
98*4882a593Smuzhiyun 			 * overridden by uv_pages above if it was an
99*4882a593Smuzhiyun 			 * actual errno.
100*4882a593Smuzhiyun 			 */
101*4882a593Smuzhiyun 		} else {
102*4882a593Smuzhiyun 			rc = y_pages;
103*4882a593Smuzhiyun 		}
104*4882a593Smuzhiyun 		return rc;
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	dma->page_count = y_pages + uv_pages;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	/* Fill & map SG List */
110*4882a593Smuzhiyun 	if (ivtv_udma_fill_sg_list (dma, &uv_dma, ivtv_udma_fill_sg_list (dma, &y_dma, 0)) < 0) {
111*4882a593Smuzhiyun 		IVTV_DEBUG_WARN("could not allocate bounce buffers for highmem userspace buffers\n");
112*4882a593Smuzhiyun 		unpin_user_pages(dma->map, dma->page_count);
113*4882a593Smuzhiyun 		dma->page_count = 0;
114*4882a593Smuzhiyun 		return -ENOMEM;
115*4882a593Smuzhiyun 	}
116*4882a593Smuzhiyun 	dma->SG_length = pci_map_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* Fill SG Array with new values */
119*4882a593Smuzhiyun 	ivtv_udma_fill_sg_array(dma, y_buffer_offset, uv_buffer_offset, y_size);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/* If we've offset the y plane, ensure top area is blanked */
122*4882a593Smuzhiyun 	if (f->offset_y && yi->blanking_dmaptr) {
123*4882a593Smuzhiyun 		dma->SGarray[dma->SG_length].size = cpu_to_le32(720*16);
124*4882a593Smuzhiyun 		dma->SGarray[dma->SG_length].src = cpu_to_le32(yi->blanking_dmaptr);
125*4882a593Smuzhiyun 		dma->SGarray[dma->SG_length].dst = cpu_to_le32(IVTV_DECODER_OFFSET + yuv_offset[frame]);
126*4882a593Smuzhiyun 		dma->SG_length++;
127*4882a593Smuzhiyun 	}
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/* Tag SG Array with Interrupt Bit */
130*4882a593Smuzhiyun 	dma->SGarray[dma->SG_length - 1].size |= cpu_to_le32(0x80000000);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	ivtv_udma_sync_for_device(itv);
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun /* We rely on a table held in the firmware - Quick check. */
ivtv_yuv_filter_check(struct ivtv * itv)137*4882a593Smuzhiyun int ivtv_yuv_filter_check(struct ivtv *itv)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	int i, y, uv;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	for (i = 0, y = 16, uv = 4; i < 16; i++, y += 24, uv += 12) {
142*4882a593Smuzhiyun 		if ((read_dec(IVTV_YUV_HORIZONTAL_FILTER_OFFSET + y) != i << 16) ||
143*4882a593Smuzhiyun 		    (read_dec(IVTV_YUV_VERTICAL_FILTER_OFFSET + uv) != i << 16)) {
144*4882a593Smuzhiyun 			IVTV_WARN ("YUV filter table not found in firmware.\n");
145*4882a593Smuzhiyun 			return -1;
146*4882a593Smuzhiyun 		}
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 	return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
ivtv_yuv_filter(struct ivtv * itv,int h_filter,int v_filter_1,int v_filter_2)151*4882a593Smuzhiyun static void ivtv_yuv_filter(struct ivtv *itv, int h_filter, int v_filter_1, int v_filter_2)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	u32 i, line;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	/* If any filter is -1, then don't update it */
156*4882a593Smuzhiyun 	if (h_filter > -1) {
157*4882a593Smuzhiyun 		if (h_filter > 4)
158*4882a593Smuzhiyun 			h_filter = 4;
159*4882a593Smuzhiyun 		i = IVTV_YUV_HORIZONTAL_FILTER_OFFSET + (h_filter * 384);
160*4882a593Smuzhiyun 		for (line = 0; line < 16; line++) {
161*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02804);
162*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x0281c);
163*4882a593Smuzhiyun 			i += 4;
164*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02808);
165*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02820);
166*4882a593Smuzhiyun 			i += 4;
167*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x0280c);
168*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02824);
169*4882a593Smuzhiyun 			i += 4;
170*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02810);
171*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02828);
172*4882a593Smuzhiyun 			i += 4;
173*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02814);
174*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x0282c);
175*4882a593Smuzhiyun 			i += 8;
176*4882a593Smuzhiyun 			write_reg(0, 0x02818);
177*4882a593Smuzhiyun 			write_reg(0, 0x02830);
178*4882a593Smuzhiyun 		}
179*4882a593Smuzhiyun 		IVTV_DEBUG_YUV("h_filter -> %d\n", h_filter);
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	if (v_filter_1 > -1) {
183*4882a593Smuzhiyun 		if (v_filter_1 > 4)
184*4882a593Smuzhiyun 			v_filter_1 = 4;
185*4882a593Smuzhiyun 		i = IVTV_YUV_VERTICAL_FILTER_OFFSET + (v_filter_1 * 192);
186*4882a593Smuzhiyun 		for (line = 0; line < 16; line++) {
187*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02900);
188*4882a593Smuzhiyun 			i += 4;
189*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02904);
190*4882a593Smuzhiyun 			i += 8;
191*4882a593Smuzhiyun 			write_reg(0, 0x02908);
192*4882a593Smuzhiyun 		}
193*4882a593Smuzhiyun 		IVTV_DEBUG_YUV("v_filter_1 -> %d\n", v_filter_1);
194*4882a593Smuzhiyun 	}
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	if (v_filter_2 > -1) {
197*4882a593Smuzhiyun 		if (v_filter_2 > 4)
198*4882a593Smuzhiyun 			v_filter_2 = 4;
199*4882a593Smuzhiyun 		i = IVTV_YUV_VERTICAL_FILTER_OFFSET + (v_filter_2 * 192);
200*4882a593Smuzhiyun 		for (line = 0; line < 16; line++) {
201*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x0290c);
202*4882a593Smuzhiyun 			i += 4;
203*4882a593Smuzhiyun 			write_reg(read_dec(i), 0x02910);
204*4882a593Smuzhiyun 			i += 8;
205*4882a593Smuzhiyun 			write_reg(0, 0x02914);
206*4882a593Smuzhiyun 		}
207*4882a593Smuzhiyun 		IVTV_DEBUG_YUV("v_filter_2 -> %d\n", v_filter_2);
208*4882a593Smuzhiyun 	}
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
ivtv_yuv_handle_horizontal(struct ivtv * itv,struct yuv_frame_info * f)211*4882a593Smuzhiyun static void ivtv_yuv_handle_horizontal(struct ivtv *itv, struct yuv_frame_info *f)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
214*4882a593Smuzhiyun 	u32 reg_2834, reg_2838, reg_283c;
215*4882a593Smuzhiyun 	u32 reg_2844, reg_2854, reg_285c;
216*4882a593Smuzhiyun 	u32 reg_2864, reg_2874, reg_2890;
217*4882a593Smuzhiyun 	u32 reg_2870, reg_2870_base, reg_2870_offset;
218*4882a593Smuzhiyun 	int x_cutoff;
219*4882a593Smuzhiyun 	int h_filter;
220*4882a593Smuzhiyun 	u32 master_width;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	IVTV_DEBUG_WARN
223*4882a593Smuzhiyun 	    ("Adjust to width %d src_w %d dst_w %d src_x %d dst_x %d\n",
224*4882a593Smuzhiyun 	     f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* How wide is the src image */
227*4882a593Smuzhiyun 	x_cutoff = f->src_w + f->src_x;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	/* Set the display width */
230*4882a593Smuzhiyun 	reg_2834 = f->dst_w;
231*4882a593Smuzhiyun 	reg_2838 = reg_2834;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	/* Set the display position */
234*4882a593Smuzhiyun 	reg_2890 = f->dst_x;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	/* Index into the image horizontally */
237*4882a593Smuzhiyun 	reg_2870 = 0;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	/* 2870 is normally fudged to align video coords with osd coords.
240*4882a593Smuzhiyun 	   If running full screen, it causes an unwanted left shift
241*4882a593Smuzhiyun 	   Remove the fudge if we almost fill the screen.
242*4882a593Smuzhiyun 	   Gradually adjust the offset to avoid the video 'snapping'
243*4882a593Smuzhiyun 	   left/right if it gets dragged through this region.
244*4882a593Smuzhiyun 	   Only do this if osd is full width. */
245*4882a593Smuzhiyun 	if (f->vis_w == 720) {
246*4882a593Smuzhiyun 		if ((f->tru_x - f->pan_x > -1) && (f->tru_x - f->pan_x <= 40) && (f->dst_w >= 680))
247*4882a593Smuzhiyun 			reg_2870 = 10 - (f->tru_x - f->pan_x) / 4;
248*4882a593Smuzhiyun 		else if ((f->tru_x - f->pan_x < 0) && (f->tru_x - f->pan_x >= -20) && (f->dst_w >= 660))
249*4882a593Smuzhiyun 			reg_2870 = (10 + (f->tru_x - f->pan_x) / 2);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 		if (f->dst_w >= f->src_w)
252*4882a593Smuzhiyun 			reg_2870 = reg_2870 << 16 | reg_2870;
253*4882a593Smuzhiyun 		else
254*4882a593Smuzhiyun 			reg_2870 = ((reg_2870 & ~1) << 15) | (reg_2870 & ~1);
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	if (f->dst_w < f->src_w)
258*4882a593Smuzhiyun 		reg_2870 = 0x000d000e - reg_2870;
259*4882a593Smuzhiyun 	else
260*4882a593Smuzhiyun 		reg_2870 = 0x0012000e - reg_2870;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* We're also using 2870 to shift the image left (src_x & negative dst_x) */
263*4882a593Smuzhiyun 	reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	if (f->dst_w >= f->src_w) {
266*4882a593Smuzhiyun 		x_cutoff &= ~1;
267*4882a593Smuzhiyun 		master_width = (f->src_w * 0x00200000) / (f->dst_w);
268*4882a593Smuzhiyun 		if (master_width * f->dst_w != f->src_w * 0x00200000)
269*4882a593Smuzhiyun 			master_width++;
270*4882a593Smuzhiyun 		reg_2834 = (reg_2834 << 16) | x_cutoff;
271*4882a593Smuzhiyun 		reg_2838 = (reg_2838 << 16) | x_cutoff;
272*4882a593Smuzhiyun 		reg_283c = master_width >> 2;
273*4882a593Smuzhiyun 		reg_2844 = master_width >> 2;
274*4882a593Smuzhiyun 		reg_2854 = master_width;
275*4882a593Smuzhiyun 		reg_285c = master_width >> 1;
276*4882a593Smuzhiyun 		reg_2864 = master_width >> 1;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 		/* We also need to factor in the scaling
279*4882a593Smuzhiyun 		   (src_w - dst_w) / (src_w / 4) */
280*4882a593Smuzhiyun 		if (f->dst_w > f->src_w)
281*4882a593Smuzhiyun 			reg_2870_base = ((f->dst_w - f->src_w)<<16) / (f->src_w <<14);
282*4882a593Smuzhiyun 		else
283*4882a593Smuzhiyun 			reg_2870_base = 0;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 		reg_2870 += (((reg_2870_offset << 14) & 0xFFFF0000) | reg_2870_offset >> 2) + (reg_2870_base << 17 | reg_2870_base);
286*4882a593Smuzhiyun 		reg_2874 = 0;
287*4882a593Smuzhiyun 	} else if (f->dst_w < f->src_w / 2) {
288*4882a593Smuzhiyun 		master_width = (f->src_w * 0x00080000) / f->dst_w;
289*4882a593Smuzhiyun 		if (master_width * f->dst_w != f->src_w * 0x00080000)
290*4882a593Smuzhiyun 			master_width++;
291*4882a593Smuzhiyun 		reg_2834 = (reg_2834 << 16) | x_cutoff;
292*4882a593Smuzhiyun 		reg_2838 = (reg_2838 << 16) | x_cutoff;
293*4882a593Smuzhiyun 		reg_283c = master_width >> 2;
294*4882a593Smuzhiyun 		reg_2844 = master_width >> 1;
295*4882a593Smuzhiyun 		reg_2854 = master_width;
296*4882a593Smuzhiyun 		reg_285c = master_width >> 1;
297*4882a593Smuzhiyun 		reg_2864 = master_width >> 1;
298*4882a593Smuzhiyun 		reg_2870 += ((reg_2870_offset << 15) & 0xFFFF0000) | reg_2870_offset;
299*4882a593Smuzhiyun 		reg_2870 += (5 - (((f->src_w + f->src_w / 2) - 1) / f->dst_w)) << 16;
300*4882a593Smuzhiyun 		reg_2874 = 0x00000012;
301*4882a593Smuzhiyun 	} else {
302*4882a593Smuzhiyun 		master_width = (f->src_w * 0x00100000) / f->dst_w;
303*4882a593Smuzhiyun 		if (master_width * f->dst_w != f->src_w * 0x00100000)
304*4882a593Smuzhiyun 			master_width++;
305*4882a593Smuzhiyun 		reg_2834 = (reg_2834 << 16) | x_cutoff;
306*4882a593Smuzhiyun 		reg_2838 = (reg_2838 << 16) | x_cutoff;
307*4882a593Smuzhiyun 		reg_283c = master_width >> 2;
308*4882a593Smuzhiyun 		reg_2844 = master_width >> 1;
309*4882a593Smuzhiyun 		reg_2854 = master_width;
310*4882a593Smuzhiyun 		reg_285c = master_width >> 1;
311*4882a593Smuzhiyun 		reg_2864 = master_width >> 1;
312*4882a593Smuzhiyun 		reg_2870 += ((reg_2870_offset << 14) & 0xFFFF0000) | reg_2870_offset >> 1;
313*4882a593Smuzhiyun 		reg_2870 += (5 - (((f->src_w * 3) - 1) / f->dst_w)) << 16;
314*4882a593Smuzhiyun 		reg_2874 = 0x00000001;
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/* Select the horizontal filter */
318*4882a593Smuzhiyun 	if (f->src_w == f->dst_w) {
319*4882a593Smuzhiyun 		/* An exact size match uses filter 0 */
320*4882a593Smuzhiyun 		h_filter = 0;
321*4882a593Smuzhiyun 	} else {
322*4882a593Smuzhiyun 		/* Figure out which filter to use */
323*4882a593Smuzhiyun 		h_filter = ((f->src_w << 16) / f->dst_w) >> 15;
324*4882a593Smuzhiyun 		h_filter = (h_filter >> 1) + (h_filter & 1);
325*4882a593Smuzhiyun 		/* Only an exact size match can use filter 0 */
326*4882a593Smuzhiyun 		h_filter += !h_filter;
327*4882a593Smuzhiyun 	}
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	write_reg(reg_2834, 0x02834);
330*4882a593Smuzhiyun 	write_reg(reg_2838, 0x02838);
331*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2834 %08x->%08x 0x2838 %08x->%08x\n",
332*4882a593Smuzhiyun 		       yi->reg_2834, reg_2834, yi->reg_2838, reg_2838);
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	write_reg(reg_283c, 0x0283c);
335*4882a593Smuzhiyun 	write_reg(reg_2844, 0x02844);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x283c %08x->%08x 0x2844 %08x->%08x\n",
338*4882a593Smuzhiyun 		       yi->reg_283c, reg_283c, yi->reg_2844, reg_2844);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	write_reg(0x00080514, 0x02840);
341*4882a593Smuzhiyun 	write_reg(0x00100514, 0x02848);
342*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2840 %08x->%08x 0x2848 %08x->%08x\n",
343*4882a593Smuzhiyun 		       yi->reg_2840, 0x00080514, yi->reg_2848, 0x00100514);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	write_reg(reg_2854, 0x02854);
346*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2854 %08x->%08x \n",
347*4882a593Smuzhiyun 		       yi->reg_2854, reg_2854);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	write_reg(reg_285c, 0x0285c);
350*4882a593Smuzhiyun 	write_reg(reg_2864, 0x02864);
351*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x285c %08x->%08x 0x2864 %08x->%08x\n",
352*4882a593Smuzhiyun 		       yi->reg_285c, reg_285c, yi->reg_2864, reg_2864);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	write_reg(reg_2874, 0x02874);
355*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2874 %08x->%08x\n",
356*4882a593Smuzhiyun 		       yi->reg_2874, reg_2874);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	write_reg(reg_2870, 0x02870);
359*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2870 %08x->%08x\n",
360*4882a593Smuzhiyun 		       yi->reg_2870, reg_2870);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	write_reg(reg_2890, 0x02890);
363*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2890 %08x->%08x\n",
364*4882a593Smuzhiyun 		       yi->reg_2890, reg_2890);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	/* Only update the filter if we really need to */
367*4882a593Smuzhiyun 	if (h_filter != yi->h_filter) {
368*4882a593Smuzhiyun 		ivtv_yuv_filter(itv, h_filter, -1, -1);
369*4882a593Smuzhiyun 		yi->h_filter = h_filter;
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
ivtv_yuv_handle_vertical(struct ivtv * itv,struct yuv_frame_info * f)373*4882a593Smuzhiyun static void ivtv_yuv_handle_vertical(struct ivtv *itv, struct yuv_frame_info *f)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
376*4882a593Smuzhiyun 	u32 master_height;
377*4882a593Smuzhiyun 	u32 reg_2918, reg_291c, reg_2920, reg_2928;
378*4882a593Smuzhiyun 	u32 reg_2930, reg_2934, reg_293c;
379*4882a593Smuzhiyun 	u32 reg_2940, reg_2944, reg_294c;
380*4882a593Smuzhiyun 	u32 reg_2950, reg_2954, reg_2958, reg_295c;
381*4882a593Smuzhiyun 	u32 reg_2960, reg_2964, reg_2968, reg_296c;
382*4882a593Smuzhiyun 	u32 reg_289c;
383*4882a593Smuzhiyun 	u32 src_major_y, src_minor_y;
384*4882a593Smuzhiyun 	u32 src_major_uv, src_minor_uv;
385*4882a593Smuzhiyun 	u32 reg_2964_base, reg_2968_base;
386*4882a593Smuzhiyun 	int v_filter_1, v_filter_2;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	IVTV_DEBUG_WARN
389*4882a593Smuzhiyun 	    ("Adjust to height %d src_h %d dst_h %d src_y %d dst_y %d\n",
390*4882a593Smuzhiyun 	     f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	/* What scaling mode is being used... */
393*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Scaling mode Y: %s\n",
394*4882a593Smuzhiyun 		       f->interlaced_y ? "Interlaced" : "Progressive");
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Scaling mode UV: %s\n",
397*4882a593Smuzhiyun 		       f->interlaced_uv ? "Interlaced" : "Progressive");
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	/* What is the source video being treated as... */
400*4882a593Smuzhiyun 	IVTV_DEBUG_WARN("Source video: %s\n",
401*4882a593Smuzhiyun 			f->interlaced ? "Interlaced" : "Progressive");
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	/* We offset into the image using two different index methods, so split
404*4882a593Smuzhiyun 	   the y source coord into two parts. */
405*4882a593Smuzhiyun 	if (f->src_y < 8) {
406*4882a593Smuzhiyun 		src_minor_uv = f->src_y;
407*4882a593Smuzhiyun 		src_major_uv = 0;
408*4882a593Smuzhiyun 	} else {
409*4882a593Smuzhiyun 		src_minor_uv = 8;
410*4882a593Smuzhiyun 		src_major_uv = f->src_y - 8;
411*4882a593Smuzhiyun 	}
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	src_minor_y = src_minor_uv;
414*4882a593Smuzhiyun 	src_major_y = src_major_uv;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	if (f->offset_y)
417*4882a593Smuzhiyun 		src_minor_y += 16;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	if (f->interlaced_y)
420*4882a593Smuzhiyun 		reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y);
421*4882a593Smuzhiyun 	else
422*4882a593Smuzhiyun 		reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	if (f->interlaced_uv)
425*4882a593Smuzhiyun 		reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1);
426*4882a593Smuzhiyun 	else
427*4882a593Smuzhiyun 		reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv);
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14;
430*4882a593Smuzhiyun 	reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) {
433*4882a593Smuzhiyun 		master_height = (f->src_h * 0x00400000) / f->dst_h;
434*4882a593Smuzhiyun 		if ((f->src_h * 0x00400000) - (master_height * f->dst_h) >= f->dst_h / 2)
435*4882a593Smuzhiyun 			master_height++;
436*4882a593Smuzhiyun 		reg_2920 = master_height >> 2;
437*4882a593Smuzhiyun 		reg_2928 = master_height >> 3;
438*4882a593Smuzhiyun 		reg_2930 = master_height;
439*4882a593Smuzhiyun 		reg_2940 = master_height >> 1;
440*4882a593Smuzhiyun 		reg_2964_base >>= 3;
441*4882a593Smuzhiyun 		reg_2968_base >>= 3;
442*4882a593Smuzhiyun 		reg_296c = 0x00000000;
443*4882a593Smuzhiyun 	} else if (f->dst_h >= f->src_h) {
444*4882a593Smuzhiyun 		master_height = (f->src_h * 0x00400000) / f->dst_h;
445*4882a593Smuzhiyun 		master_height = (master_height >> 1) + (master_height & 1);
446*4882a593Smuzhiyun 		reg_2920 = master_height >> 2;
447*4882a593Smuzhiyun 		reg_2928 = master_height >> 2;
448*4882a593Smuzhiyun 		reg_2930 = master_height;
449*4882a593Smuzhiyun 		reg_2940 = master_height >> 1;
450*4882a593Smuzhiyun 		reg_296c = 0x00000000;
451*4882a593Smuzhiyun 		if (f->interlaced_y) {
452*4882a593Smuzhiyun 			reg_2964_base >>= 3;
453*4882a593Smuzhiyun 		} else {
454*4882a593Smuzhiyun 			reg_296c++;
455*4882a593Smuzhiyun 			reg_2964_base >>= 2;
456*4882a593Smuzhiyun 		}
457*4882a593Smuzhiyun 		if (f->interlaced_uv)
458*4882a593Smuzhiyun 			reg_2928 >>= 1;
459*4882a593Smuzhiyun 		reg_2968_base >>= 3;
460*4882a593Smuzhiyun 	} else if (f->dst_h >= f->src_h / 2) {
461*4882a593Smuzhiyun 		master_height = (f->src_h * 0x00200000) / f->dst_h;
462*4882a593Smuzhiyun 		master_height = (master_height >> 1) + (master_height & 1);
463*4882a593Smuzhiyun 		reg_2920 = master_height >> 2;
464*4882a593Smuzhiyun 		reg_2928 = master_height >> 2;
465*4882a593Smuzhiyun 		reg_2930 = master_height;
466*4882a593Smuzhiyun 		reg_2940 = master_height;
467*4882a593Smuzhiyun 		reg_296c = 0x00000101;
468*4882a593Smuzhiyun 		if (f->interlaced_y) {
469*4882a593Smuzhiyun 			reg_2964_base >>= 2;
470*4882a593Smuzhiyun 		} else {
471*4882a593Smuzhiyun 			reg_296c++;
472*4882a593Smuzhiyun 			reg_2964_base >>= 1;
473*4882a593Smuzhiyun 		}
474*4882a593Smuzhiyun 		if (f->interlaced_uv)
475*4882a593Smuzhiyun 			reg_2928 >>= 1;
476*4882a593Smuzhiyun 		reg_2968_base >>= 2;
477*4882a593Smuzhiyun 	} else {
478*4882a593Smuzhiyun 		master_height = (f->src_h * 0x00100000) / f->dst_h;
479*4882a593Smuzhiyun 		master_height = (master_height >> 1) + (master_height & 1);
480*4882a593Smuzhiyun 		reg_2920 = master_height >> 2;
481*4882a593Smuzhiyun 		reg_2928 = master_height >> 2;
482*4882a593Smuzhiyun 		reg_2930 = master_height;
483*4882a593Smuzhiyun 		reg_2940 = master_height;
484*4882a593Smuzhiyun 		reg_2964_base >>= 1;
485*4882a593Smuzhiyun 		reg_2968_base >>= 2;
486*4882a593Smuzhiyun 		reg_296c = 0x00000102;
487*4882a593Smuzhiyun 	}
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	/* FIXME These registers change depending on scaled / unscaled output
490*4882a593Smuzhiyun 	   We really need to work out what they should be */
491*4882a593Smuzhiyun 	if (f->src_h == f->dst_h) {
492*4882a593Smuzhiyun 		reg_2934 = 0x00020000;
493*4882a593Smuzhiyun 		reg_293c = 0x00100000;
494*4882a593Smuzhiyun 		reg_2944 = 0x00040000;
495*4882a593Smuzhiyun 		reg_294c = 0x000b0000;
496*4882a593Smuzhiyun 	} else {
497*4882a593Smuzhiyun 		reg_2934 = 0x00000FF0;
498*4882a593Smuzhiyun 		reg_293c = 0x00000FF0;
499*4882a593Smuzhiyun 		reg_2944 = 0x00000FF0;
500*4882a593Smuzhiyun 		reg_294c = 0x00000FF0;
501*4882a593Smuzhiyun 	}
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	/* The first line to be displayed */
504*4882a593Smuzhiyun 	reg_2950 = 0x00010000 + src_major_y;
505*4882a593Smuzhiyun 	if (f->interlaced_y)
506*4882a593Smuzhiyun 		reg_2950 += 0x00010000;
507*4882a593Smuzhiyun 	reg_2954 = reg_2950 + 1;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	reg_2958 = 0x00010000 + (src_major_y >> 1);
510*4882a593Smuzhiyun 	if (f->interlaced_uv)
511*4882a593Smuzhiyun 		reg_2958 += 0x00010000;
512*4882a593Smuzhiyun 	reg_295c = reg_2958 + 1;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	if (yi->decode_height == 480)
515*4882a593Smuzhiyun 		reg_289c = 0x011e0017;
516*4882a593Smuzhiyun 	else
517*4882a593Smuzhiyun 		reg_289c = 0x01500017;
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	if (f->dst_y < 0)
520*4882a593Smuzhiyun 		reg_289c = (reg_289c - ((f->dst_y & ~1)<<15))-(f->dst_y >>1);
521*4882a593Smuzhiyun 	else
522*4882a593Smuzhiyun 		reg_289c = (reg_289c + ((f->dst_y & ~1)<<15))+(f->dst_y >>1);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	/* How much of the source to decode.
525*4882a593Smuzhiyun 	   Take into account the source offset */
526*4882a593Smuzhiyun 	reg_2960 = ((src_minor_y + f->src_h + src_major_y) - 1) |
527*4882a593Smuzhiyun 		(((src_minor_uv + f->src_h + src_major_uv - 1) & ~1) << 15);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	/* Calculate correct value for register 2964 */
530*4882a593Smuzhiyun 	if (f->src_h == f->dst_h) {
531*4882a593Smuzhiyun 		reg_2964 = 1;
532*4882a593Smuzhiyun 	} else {
533*4882a593Smuzhiyun 		reg_2964 = 2 + ((f->dst_h << 1) / f->src_h);
534*4882a593Smuzhiyun 		reg_2964 = (reg_2964 >> 1) + (reg_2964 & 1);
535*4882a593Smuzhiyun 	}
536*4882a593Smuzhiyun 	reg_2968 = (reg_2964 << 16) + reg_2964 + (reg_2964 >> 1);
537*4882a593Smuzhiyun 	reg_2964 = (reg_2964 << 16) + reg_2964 + (reg_2964 * 46 / 94);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	/* Okay, we've wasted time working out the correct value,
540*4882a593Smuzhiyun 	   but if we use it, it fouls the the window alignment.
541*4882a593Smuzhiyun 	   Fudge it to what we want... */
542*4882a593Smuzhiyun 	reg_2964 = 0x00010001 + ((reg_2964 & 0x0000FFFF) - (reg_2964 >> 16));
543*4882a593Smuzhiyun 	reg_2968 = 0x00010001 + ((reg_2968 & 0x0000FFFF) - (reg_2968 >> 16));
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	/* Deviate further from what it should be. I find the flicker headache
546*4882a593Smuzhiyun 	   inducing so try to reduce it slightly. Leave 2968 as-is otherwise
547*4882a593Smuzhiyun 	   colours foul. */
548*4882a593Smuzhiyun 	if ((reg_2964 != 0x00010001) && (f->dst_h / 2 <= f->src_h))
549*4882a593Smuzhiyun 		reg_2964 = (reg_2964 & 0xFFFF0000) + ((reg_2964 & 0x0000FFFF) / 2);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	if (!f->interlaced_y)
552*4882a593Smuzhiyun 		reg_2964 -= 0x00010001;
553*4882a593Smuzhiyun 	if (!f->interlaced_uv)
554*4882a593Smuzhiyun 		reg_2968 -= 0x00010001;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	reg_2964 += ((reg_2964_base << 16) | reg_2964_base);
557*4882a593Smuzhiyun 	reg_2968 += ((reg_2968_base << 16) | reg_2968_base);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	/* Select the vertical filter */
560*4882a593Smuzhiyun 	if (f->src_h == f->dst_h) {
561*4882a593Smuzhiyun 		/* An exact size match uses filter 0/1 */
562*4882a593Smuzhiyun 		v_filter_1 = 0;
563*4882a593Smuzhiyun 		v_filter_2 = 1;
564*4882a593Smuzhiyun 	} else {
565*4882a593Smuzhiyun 		/* Figure out which filter to use */
566*4882a593Smuzhiyun 		v_filter_1 = ((f->src_h << 16) / f->dst_h) >> 15;
567*4882a593Smuzhiyun 		v_filter_1 = (v_filter_1 >> 1) + (v_filter_1 & 1);
568*4882a593Smuzhiyun 		/* Only an exact size match can use filter 0 */
569*4882a593Smuzhiyun 		v_filter_1 += !v_filter_1;
570*4882a593Smuzhiyun 		v_filter_2 = v_filter_1;
571*4882a593Smuzhiyun 	}
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	write_reg(reg_2934, 0x02934);
574*4882a593Smuzhiyun 	write_reg(reg_293c, 0x0293c);
575*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2934 %08x->%08x 0x293c %08x->%08x\n",
576*4882a593Smuzhiyun 		       yi->reg_2934, reg_2934, yi->reg_293c, reg_293c);
577*4882a593Smuzhiyun 	write_reg(reg_2944, 0x02944);
578*4882a593Smuzhiyun 	write_reg(reg_294c, 0x0294c);
579*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2944 %08x->%08x 0x294c %08x->%08x\n",
580*4882a593Smuzhiyun 		       yi->reg_2944, reg_2944, yi->reg_294c, reg_294c);
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	/* Ensure 2970 is 0 (does it ever change ?) */
583*4882a593Smuzhiyun /*	write_reg(0,0x02970); */
584*4882a593Smuzhiyun /*	IVTV_DEBUG_YUV("Update reg 0x2970 %08x->%08x\n", yi->reg_2970, 0); */
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	write_reg(reg_2930, 0x02938);
587*4882a593Smuzhiyun 	write_reg(reg_2930, 0x02930);
588*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2930 %08x->%08x 0x2938 %08x->%08x\n",
589*4882a593Smuzhiyun 		       yi->reg_2930, reg_2930, yi->reg_2938, reg_2930);
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	write_reg(reg_2928, 0x02928);
592*4882a593Smuzhiyun 	write_reg(reg_2928 + 0x514, 0x0292C);
593*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2928 %08x->%08x 0x292c %08x->%08x\n",
594*4882a593Smuzhiyun 		       yi->reg_2928, reg_2928, yi->reg_292c, reg_2928 + 0x514);
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	write_reg(reg_2920, 0x02920);
597*4882a593Smuzhiyun 	write_reg(reg_2920 + 0x514, 0x02924);
598*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2920 %08x->%08x 0x2924 %08x->%08x\n",
599*4882a593Smuzhiyun 		       yi->reg_2920, reg_2920, yi->reg_2924, reg_2920 + 0x514);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	write_reg(reg_2918, 0x02918);
602*4882a593Smuzhiyun 	write_reg(reg_291c, 0x0291C);
603*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2918 %08x->%08x 0x291C %08x->%08x\n",
604*4882a593Smuzhiyun 		       yi->reg_2918, reg_2918, yi->reg_291c, reg_291c);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	write_reg(reg_296c, 0x0296c);
607*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x296c %08x->%08x\n",
608*4882a593Smuzhiyun 		       yi->reg_296c, reg_296c);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	write_reg(reg_2940, 0x02948);
611*4882a593Smuzhiyun 	write_reg(reg_2940, 0x02940);
612*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2940 %08x->%08x 0x2948 %08x->%08x\n",
613*4882a593Smuzhiyun 		       yi->reg_2940, reg_2940, yi->reg_2948, reg_2940);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	write_reg(reg_2950, 0x02950);
616*4882a593Smuzhiyun 	write_reg(reg_2954, 0x02954);
617*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2950 %08x->%08x 0x2954 %08x->%08x\n",
618*4882a593Smuzhiyun 		       yi->reg_2950, reg_2950, yi->reg_2954, reg_2954);
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	write_reg(reg_2958, 0x02958);
621*4882a593Smuzhiyun 	write_reg(reg_295c, 0x0295C);
622*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2958 %08x->%08x 0x295C %08x->%08x\n",
623*4882a593Smuzhiyun 		       yi->reg_2958, reg_2958, yi->reg_295c, reg_295c);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	write_reg(reg_2960, 0x02960);
626*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2960 %08x->%08x \n",
627*4882a593Smuzhiyun 		       yi->reg_2960, reg_2960);
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	write_reg(reg_2964, 0x02964);
630*4882a593Smuzhiyun 	write_reg(reg_2968, 0x02968);
631*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x2964 %08x->%08x 0x2968 %08x->%08x\n",
632*4882a593Smuzhiyun 		       yi->reg_2964, reg_2964, yi->reg_2968, reg_2968);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	write_reg(reg_289c, 0x0289c);
635*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update reg 0x289c %08x->%08x\n",
636*4882a593Smuzhiyun 		       yi->reg_289c, reg_289c);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	/* Only update filter 1 if we really need to */
639*4882a593Smuzhiyun 	if (v_filter_1 != yi->v_filter_1) {
640*4882a593Smuzhiyun 		ivtv_yuv_filter(itv, -1, v_filter_1, -1);
641*4882a593Smuzhiyun 		yi->v_filter_1 = v_filter_1;
642*4882a593Smuzhiyun 	}
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	/* Only update filter 2 if we really need to */
645*4882a593Smuzhiyun 	if (v_filter_2 != yi->v_filter_2) {
646*4882a593Smuzhiyun 		ivtv_yuv_filter(itv, -1, -1, v_filter_2);
647*4882a593Smuzhiyun 		yi->v_filter_2 = v_filter_2;
648*4882a593Smuzhiyun 	}
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun /* Modify the supplied coordinate information to fit the visible osd area */
ivtv_yuv_window_setup(struct ivtv * itv,struct yuv_frame_info * f)652*4882a593Smuzhiyun static u32 ivtv_yuv_window_setup(struct ivtv *itv, struct yuv_frame_info *f)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun 	struct yuv_frame_info *of = &itv->yuv_info.old_frame_info;
655*4882a593Smuzhiyun 	int osd_crop;
656*4882a593Smuzhiyun 	u32 osd_scale;
657*4882a593Smuzhiyun 	u32 yuv_update = 0;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	/* Sorry, but no negative coords for src */
660*4882a593Smuzhiyun 	if (f->src_x < 0)
661*4882a593Smuzhiyun 		f->src_x = 0;
662*4882a593Smuzhiyun 	if (f->src_y < 0)
663*4882a593Smuzhiyun 		f->src_y = 0;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	/* Can only reduce width down to 1/4 original size */
666*4882a593Smuzhiyun 	if ((osd_crop = f->src_w - 4 * f->dst_w) > 0) {
667*4882a593Smuzhiyun 		f->src_x += osd_crop / 2;
668*4882a593Smuzhiyun 		f->src_w = (f->src_w - osd_crop) & ~3;
669*4882a593Smuzhiyun 		f->dst_w = f->src_w / 4;
670*4882a593Smuzhiyun 		f->dst_w += f->dst_w & 1;
671*4882a593Smuzhiyun 	}
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	/* Can only reduce height down to 1/4 original size */
674*4882a593Smuzhiyun 	if (f->src_h / f->dst_h >= 2) {
675*4882a593Smuzhiyun 		/* Overflow may be because we're running progressive,
676*4882a593Smuzhiyun 		   so force mode switch */
677*4882a593Smuzhiyun 		f->interlaced_y = 1;
678*4882a593Smuzhiyun 		/* Make sure we're still within limits for interlace */
679*4882a593Smuzhiyun 		if ((osd_crop = f->src_h - 4 * f->dst_h) > 0) {
680*4882a593Smuzhiyun 			/* If we reach here we'll have to force the height. */
681*4882a593Smuzhiyun 			f->src_y += osd_crop / 2;
682*4882a593Smuzhiyun 			f->src_h = (f->src_h - osd_crop) & ~3;
683*4882a593Smuzhiyun 			f->dst_h = f->src_h / 4;
684*4882a593Smuzhiyun 			f->dst_h += f->dst_h & 1;
685*4882a593Smuzhiyun 		}
686*4882a593Smuzhiyun 	}
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	/* If there's nothing to safe to display, we may as well stop now */
689*4882a593Smuzhiyun 	if ((int)f->dst_w <= 2 || (int)f->dst_h <= 2 ||
690*4882a593Smuzhiyun 	    (int)f->src_w <= 2 || (int)f->src_h <= 2) {
691*4882a593Smuzhiyun 		return IVTV_YUV_UPDATE_INVALID;
692*4882a593Smuzhiyun 	}
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	/* Ensure video remains inside OSD area */
695*4882a593Smuzhiyun 	osd_scale = (f->src_h << 16) / f->dst_h;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if ((osd_crop = f->pan_y - f->dst_y) > 0) {
698*4882a593Smuzhiyun 		/* Falls off the upper edge - crop */
699*4882a593Smuzhiyun 		f->src_y += (osd_scale * osd_crop) >> 16;
700*4882a593Smuzhiyun 		f->src_h -= (osd_scale * osd_crop) >> 16;
701*4882a593Smuzhiyun 		f->dst_h -= osd_crop;
702*4882a593Smuzhiyun 		f->dst_y = 0;
703*4882a593Smuzhiyun 	} else {
704*4882a593Smuzhiyun 		f->dst_y -= f->pan_y;
705*4882a593Smuzhiyun 	}
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	if ((osd_crop = f->dst_h + f->dst_y - f->vis_h) > 0) {
708*4882a593Smuzhiyun 		/* Falls off the lower edge - crop */
709*4882a593Smuzhiyun 		f->dst_h -= osd_crop;
710*4882a593Smuzhiyun 		f->src_h -= (osd_scale * osd_crop) >> 16;
711*4882a593Smuzhiyun 	}
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	osd_scale = (f->src_w << 16) / f->dst_w;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	if ((osd_crop = f->pan_x - f->dst_x) > 0) {
716*4882a593Smuzhiyun 		/* Fall off the left edge - crop */
717*4882a593Smuzhiyun 		f->src_x += (osd_scale * osd_crop) >> 16;
718*4882a593Smuzhiyun 		f->src_w -= (osd_scale * osd_crop) >> 16;
719*4882a593Smuzhiyun 		f->dst_w -= osd_crop;
720*4882a593Smuzhiyun 		f->dst_x = 0;
721*4882a593Smuzhiyun 	} else {
722*4882a593Smuzhiyun 		f->dst_x -= f->pan_x;
723*4882a593Smuzhiyun 	}
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	if ((osd_crop = f->dst_w + f->dst_x - f->vis_w) > 0) {
726*4882a593Smuzhiyun 		/* Falls off the right edge - crop */
727*4882a593Smuzhiyun 		f->dst_w -= osd_crop;
728*4882a593Smuzhiyun 		f->src_w -= (osd_scale * osd_crop) >> 16;
729*4882a593Smuzhiyun 	}
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	if (itv->yuv_info.track_osd) {
732*4882a593Smuzhiyun 		/* The OSD can be moved. Track to it */
733*4882a593Smuzhiyun 		f->dst_x += itv->yuv_info.osd_x_offset;
734*4882a593Smuzhiyun 		f->dst_y += itv->yuv_info.osd_y_offset;
735*4882a593Smuzhiyun 	}
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	/* Width & height for both src & dst must be even.
738*4882a593Smuzhiyun 	   Same for coordinates. */
739*4882a593Smuzhiyun 	f->dst_w &= ~1;
740*4882a593Smuzhiyun 	f->dst_x &= ~1;
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	f->src_w += f->src_x & 1;
743*4882a593Smuzhiyun 	f->src_x &= ~1;
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	f->src_w &= ~1;
746*4882a593Smuzhiyun 	f->dst_w &= ~1;
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	f->dst_h &= ~1;
749*4882a593Smuzhiyun 	f->dst_y &= ~1;
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	f->src_h += f->src_y & 1;
752*4882a593Smuzhiyun 	f->src_y &= ~1;
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun 	f->src_h &= ~1;
755*4882a593Smuzhiyun 	f->dst_h &= ~1;
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	/* Due to rounding, we may have reduced the output size to <1/4 of
758*4882a593Smuzhiyun 	   the source. Check again, but this time just resize. Don't change
759*4882a593Smuzhiyun 	   source coordinates */
760*4882a593Smuzhiyun 	if (f->dst_w < f->src_w / 4) {
761*4882a593Smuzhiyun 		f->src_w &= ~3;
762*4882a593Smuzhiyun 		f->dst_w = f->src_w / 4;
763*4882a593Smuzhiyun 		f->dst_w += f->dst_w & 1;
764*4882a593Smuzhiyun 	}
765*4882a593Smuzhiyun 	if (f->dst_h < f->src_h / 4) {
766*4882a593Smuzhiyun 		f->src_h &= ~3;
767*4882a593Smuzhiyun 		f->dst_h = f->src_h / 4;
768*4882a593Smuzhiyun 		f->dst_h += f->dst_h & 1;
769*4882a593Smuzhiyun 	}
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 	/* Check again. If there's nothing to safe to display, stop now */
772*4882a593Smuzhiyun 	if ((int)f->dst_w <= 2 || (int)f->dst_h <= 2 ||
773*4882a593Smuzhiyun 	    (int)f->src_w <= 2 || (int)f->src_h <= 2) {
774*4882a593Smuzhiyun 		return IVTV_YUV_UPDATE_INVALID;
775*4882a593Smuzhiyun 	}
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 	/* Both x offset & width are linked, so they have to be done together */
778*4882a593Smuzhiyun 	if ((of->dst_w != f->dst_w) || (of->src_w != f->src_w) ||
779*4882a593Smuzhiyun 	    (of->dst_x != f->dst_x) || (of->src_x != f->src_x) ||
780*4882a593Smuzhiyun 	    (of->pan_x != f->pan_x) || (of->vis_w != f->vis_w)) {
781*4882a593Smuzhiyun 		yuv_update |= IVTV_YUV_UPDATE_HORIZONTAL;
782*4882a593Smuzhiyun 	}
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	if ((of->src_h != f->src_h) || (of->dst_h != f->dst_h) ||
785*4882a593Smuzhiyun 	    (of->dst_y != f->dst_y) || (of->src_y != f->src_y) ||
786*4882a593Smuzhiyun 	    (of->pan_y != f->pan_y) || (of->vis_h != f->vis_h) ||
787*4882a593Smuzhiyun 	    (of->lace_mode != f->lace_mode) ||
788*4882a593Smuzhiyun 	    (of->interlaced_y != f->interlaced_y) ||
789*4882a593Smuzhiyun 	    (of->interlaced_uv != f->interlaced_uv)) {
790*4882a593Smuzhiyun 		yuv_update |= IVTV_YUV_UPDATE_VERTICAL;
791*4882a593Smuzhiyun 	}
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	return yuv_update;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun /* Update the scaling register to the requested value */
ivtv_yuv_work_handler(struct ivtv * itv)797*4882a593Smuzhiyun void ivtv_yuv_work_handler(struct ivtv *itv)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
800*4882a593Smuzhiyun 	struct yuv_frame_info f;
801*4882a593Smuzhiyun 	int frame = yi->update_frame;
802*4882a593Smuzhiyun 	u32 yuv_update;
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("Update yuv registers for frame %d\n", frame);
805*4882a593Smuzhiyun 	f = yi->new_frame_info[frame];
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	if (yi->track_osd) {
808*4882a593Smuzhiyun 		/* Snapshot the osd pan info */
809*4882a593Smuzhiyun 		f.pan_x = yi->osd_x_pan;
810*4882a593Smuzhiyun 		f.pan_y = yi->osd_y_pan;
811*4882a593Smuzhiyun 		f.vis_w = yi->osd_vis_w;
812*4882a593Smuzhiyun 		f.vis_h = yi->osd_vis_h;
813*4882a593Smuzhiyun 	} else {
814*4882a593Smuzhiyun 		/* Not tracking the osd, so assume full screen */
815*4882a593Smuzhiyun 		f.pan_x = 0;
816*4882a593Smuzhiyun 		f.pan_y = 0;
817*4882a593Smuzhiyun 		f.vis_w = 720;
818*4882a593Smuzhiyun 		f.vis_h = yi->decode_height;
819*4882a593Smuzhiyun 	}
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	/* Calculate the display window coordinates. Exit if nothing left */
822*4882a593Smuzhiyun 	if (!(yuv_update = ivtv_yuv_window_setup(itv, &f)))
823*4882a593Smuzhiyun 		return;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	if (yuv_update & IVTV_YUV_UPDATE_INVALID) {
826*4882a593Smuzhiyun 		write_reg(0x01008080, 0x2898);
827*4882a593Smuzhiyun 	} else if (yuv_update) {
828*4882a593Smuzhiyun 		write_reg(0x00108080, 0x2898);
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 		if (yuv_update & IVTV_YUV_UPDATE_HORIZONTAL)
831*4882a593Smuzhiyun 			ivtv_yuv_handle_horizontal(itv, &f);
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 		if (yuv_update & IVTV_YUV_UPDATE_VERTICAL)
834*4882a593Smuzhiyun 			ivtv_yuv_handle_vertical(itv, &f);
835*4882a593Smuzhiyun 	}
836*4882a593Smuzhiyun 	yi->old_frame_info = f;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun 
ivtv_yuv_init(struct ivtv * itv)839*4882a593Smuzhiyun static void ivtv_yuv_init(struct ivtv *itv)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("ivtv_yuv_init\n");
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	/* Take a snapshot of the current register settings */
846*4882a593Smuzhiyun 	yi->reg_2834 = read_reg(0x02834);
847*4882a593Smuzhiyun 	yi->reg_2838 = read_reg(0x02838);
848*4882a593Smuzhiyun 	yi->reg_283c = read_reg(0x0283c);
849*4882a593Smuzhiyun 	yi->reg_2840 = read_reg(0x02840);
850*4882a593Smuzhiyun 	yi->reg_2844 = read_reg(0x02844);
851*4882a593Smuzhiyun 	yi->reg_2848 = read_reg(0x02848);
852*4882a593Smuzhiyun 	yi->reg_2854 = read_reg(0x02854);
853*4882a593Smuzhiyun 	yi->reg_285c = read_reg(0x0285c);
854*4882a593Smuzhiyun 	yi->reg_2864 = read_reg(0x02864);
855*4882a593Smuzhiyun 	yi->reg_2870 = read_reg(0x02870);
856*4882a593Smuzhiyun 	yi->reg_2874 = read_reg(0x02874);
857*4882a593Smuzhiyun 	yi->reg_2898 = read_reg(0x02898);
858*4882a593Smuzhiyun 	yi->reg_2890 = read_reg(0x02890);
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	yi->reg_289c = read_reg(0x0289c);
861*4882a593Smuzhiyun 	yi->reg_2918 = read_reg(0x02918);
862*4882a593Smuzhiyun 	yi->reg_291c = read_reg(0x0291c);
863*4882a593Smuzhiyun 	yi->reg_2920 = read_reg(0x02920);
864*4882a593Smuzhiyun 	yi->reg_2924 = read_reg(0x02924);
865*4882a593Smuzhiyun 	yi->reg_2928 = read_reg(0x02928);
866*4882a593Smuzhiyun 	yi->reg_292c = read_reg(0x0292c);
867*4882a593Smuzhiyun 	yi->reg_2930 = read_reg(0x02930);
868*4882a593Smuzhiyun 	yi->reg_2934 = read_reg(0x02934);
869*4882a593Smuzhiyun 	yi->reg_2938 = read_reg(0x02938);
870*4882a593Smuzhiyun 	yi->reg_293c = read_reg(0x0293c);
871*4882a593Smuzhiyun 	yi->reg_2940 = read_reg(0x02940);
872*4882a593Smuzhiyun 	yi->reg_2944 = read_reg(0x02944);
873*4882a593Smuzhiyun 	yi->reg_2948 = read_reg(0x02948);
874*4882a593Smuzhiyun 	yi->reg_294c = read_reg(0x0294c);
875*4882a593Smuzhiyun 	yi->reg_2950 = read_reg(0x02950);
876*4882a593Smuzhiyun 	yi->reg_2954 = read_reg(0x02954);
877*4882a593Smuzhiyun 	yi->reg_2958 = read_reg(0x02958);
878*4882a593Smuzhiyun 	yi->reg_295c = read_reg(0x0295c);
879*4882a593Smuzhiyun 	yi->reg_2960 = read_reg(0x02960);
880*4882a593Smuzhiyun 	yi->reg_2964 = read_reg(0x02964);
881*4882a593Smuzhiyun 	yi->reg_2968 = read_reg(0x02968);
882*4882a593Smuzhiyun 	yi->reg_296c = read_reg(0x0296c);
883*4882a593Smuzhiyun 	yi->reg_2970 = read_reg(0x02970);
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun 	yi->v_filter_1 = -1;
886*4882a593Smuzhiyun 	yi->v_filter_2 = -1;
887*4882a593Smuzhiyun 	yi->h_filter = -1;
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	/* Set some valid size info */
890*4882a593Smuzhiyun 	yi->osd_x_offset = read_reg(0x02a04) & 0x00000FFF;
891*4882a593Smuzhiyun 	yi->osd_y_offset = (read_reg(0x02a04) >> 16) & 0x00000FFF;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	/* Bit 2 of reg 2878 indicates current decoder output format
894*4882a593Smuzhiyun 	   0 : NTSC    1 : PAL */
895*4882a593Smuzhiyun 	if (read_reg(0x2878) & 4)
896*4882a593Smuzhiyun 		yi->decode_height = 576;
897*4882a593Smuzhiyun 	else
898*4882a593Smuzhiyun 		yi->decode_height = 480;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	if (!itv->osd_info) {
901*4882a593Smuzhiyun 		yi->osd_vis_w = 720 - yi->osd_x_offset;
902*4882a593Smuzhiyun 		yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
903*4882a593Smuzhiyun 	} else {
904*4882a593Smuzhiyun 		/* If no visible size set, assume full size */
905*4882a593Smuzhiyun 		if (!yi->osd_vis_w)
906*4882a593Smuzhiyun 			yi->osd_vis_w = 720 - yi->osd_x_offset;
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 		if (!yi->osd_vis_h) {
909*4882a593Smuzhiyun 			yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
910*4882a593Smuzhiyun 		} else if (yi->osd_vis_h + yi->osd_y_offset > yi->decode_height) {
911*4882a593Smuzhiyun 			/* If output video standard has changed, requested height may
912*4882a593Smuzhiyun 			   not be legal */
913*4882a593Smuzhiyun 			IVTV_DEBUG_WARN("Clipping yuv output - fb size (%d) exceeds video standard limit (%d)\n",
914*4882a593Smuzhiyun 					yi->osd_vis_h + yi->osd_y_offset,
915*4882a593Smuzhiyun 					yi->decode_height);
916*4882a593Smuzhiyun 			yi->osd_vis_h = yi->decode_height - yi->osd_y_offset;
917*4882a593Smuzhiyun 		}
918*4882a593Smuzhiyun 	}
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	/* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */
921*4882a593Smuzhiyun 	yi->blanking_ptr = kzalloc(720 * 16, GFP_ATOMIC|__GFP_NOWARN);
922*4882a593Smuzhiyun 	if (yi->blanking_ptr) {
923*4882a593Smuzhiyun 		yi->blanking_dmaptr = pci_map_single(itv->pdev, yi->blanking_ptr, 720*16, PCI_DMA_TODEVICE);
924*4882a593Smuzhiyun 	} else {
925*4882a593Smuzhiyun 		yi->blanking_dmaptr = 0;
926*4882a593Smuzhiyun 		IVTV_DEBUG_WARN("Failed to allocate yuv blanking buffer\n");
927*4882a593Smuzhiyun 	}
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	/* Enable YUV decoder output */
930*4882a593Smuzhiyun 	write_reg_sync(0x01, IVTV_REG_VDM);
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 	set_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);
933*4882a593Smuzhiyun 	atomic_set(&yi->next_dma_frame, 0);
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun /* Get next available yuv buffer on PVR350 */
ivtv_yuv_next_free(struct ivtv * itv)937*4882a593Smuzhiyun static void ivtv_yuv_next_free(struct ivtv *itv)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun 	int draw, display;
940*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 	if (atomic_read(&yi->next_dma_frame) == -1)
943*4882a593Smuzhiyun 		ivtv_yuv_init(itv);
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	draw = atomic_read(&yi->next_fill_frame);
946*4882a593Smuzhiyun 	display = atomic_read(&yi->next_dma_frame);
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun 	if (display > draw)
949*4882a593Smuzhiyun 		display -= IVTV_YUV_BUFFERS;
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 	if (draw - display >= yi->max_frames_buffered)
952*4882a593Smuzhiyun 		draw = (u8)(draw - 1) % IVTV_YUV_BUFFERS;
953*4882a593Smuzhiyun 	else
954*4882a593Smuzhiyun 		yi->new_frame_info[draw].update = 0;
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	yi->draw_frame = draw;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun /* Set up frame according to ivtv_dma_frame parameters */
ivtv_yuv_setup_frame(struct ivtv * itv,struct ivtv_dma_frame * args)960*4882a593Smuzhiyun static void ivtv_yuv_setup_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
963*4882a593Smuzhiyun 	u8 frame = yi->draw_frame;
964*4882a593Smuzhiyun 	u8 last_frame = (u8)(frame - 1) % IVTV_YUV_BUFFERS;
965*4882a593Smuzhiyun 	struct yuv_frame_info *nf = &yi->new_frame_info[frame];
966*4882a593Smuzhiyun 	struct yuv_frame_info *of = &yi->new_frame_info[last_frame];
967*4882a593Smuzhiyun 	int lace_threshold = yi->lace_threshold;
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	/* Preserve old update flag in case we're overwriting a queued frame */
970*4882a593Smuzhiyun 	int update = nf->update;
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun 	/* Take a snapshot of the yuv coordinate information */
973*4882a593Smuzhiyun 	nf->src_x = args->src.left;
974*4882a593Smuzhiyun 	nf->src_y = args->src.top;
975*4882a593Smuzhiyun 	nf->src_w = args->src.width;
976*4882a593Smuzhiyun 	nf->src_h = args->src.height;
977*4882a593Smuzhiyun 	nf->dst_x = args->dst.left;
978*4882a593Smuzhiyun 	nf->dst_y = args->dst.top;
979*4882a593Smuzhiyun 	nf->dst_w = args->dst.width;
980*4882a593Smuzhiyun 	nf->dst_h = args->dst.height;
981*4882a593Smuzhiyun 	nf->tru_x = args->dst.left;
982*4882a593Smuzhiyun 	nf->tru_w = args->src_width;
983*4882a593Smuzhiyun 	nf->tru_h = args->src_height;
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	/* Are we going to offset the Y plane */
986*4882a593Smuzhiyun 	nf->offset_y = (nf->tru_h + nf->src_x < 512 - 16) ? 1 : 0;
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun 	nf->update = 0;
989*4882a593Smuzhiyun 	nf->interlaced_y = 0;
990*4882a593Smuzhiyun 	nf->interlaced_uv = 0;
991*4882a593Smuzhiyun 	nf->delay = 0;
992*4882a593Smuzhiyun 	nf->sync_field = 0;
993*4882a593Smuzhiyun 	nf->lace_mode = yi->lace_mode & IVTV_YUV_MODE_MASK;
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	if (lace_threshold < 0)
996*4882a593Smuzhiyun 		lace_threshold = yi->decode_height - 1;
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	/* Work out the lace settings */
999*4882a593Smuzhiyun 	switch (nf->lace_mode) {
1000*4882a593Smuzhiyun 	case IVTV_YUV_MODE_PROGRESSIVE: /* Progressive mode */
1001*4882a593Smuzhiyun 		nf->interlaced = 0;
1002*4882a593Smuzhiyun 		if (nf->tru_h < 512 || (nf->tru_h > 576 && nf->tru_h < 1021))
1003*4882a593Smuzhiyun 			nf->interlaced_y = 0;
1004*4882a593Smuzhiyun 		else
1005*4882a593Smuzhiyun 			nf->interlaced_y = 1;
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 		if (nf->tru_h < 1021 && (nf->dst_h >= nf->src_h / 2))
1008*4882a593Smuzhiyun 			nf->interlaced_uv = 0;
1009*4882a593Smuzhiyun 		else
1010*4882a593Smuzhiyun 			nf->interlaced_uv = 1;
1011*4882a593Smuzhiyun 		break;
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	case IVTV_YUV_MODE_AUTO:
1014*4882a593Smuzhiyun 		if (nf->tru_h <= lace_threshold || nf->tru_h > 576 || nf->tru_w > 720) {
1015*4882a593Smuzhiyun 			nf->interlaced = 0;
1016*4882a593Smuzhiyun 			if ((nf->tru_h < 512) ||
1017*4882a593Smuzhiyun 			    (nf->tru_h > 576 && nf->tru_h < 1021) ||
1018*4882a593Smuzhiyun 			    (nf->tru_w > 720 && nf->tru_h < 1021))
1019*4882a593Smuzhiyun 				nf->interlaced_y = 0;
1020*4882a593Smuzhiyun 			else
1021*4882a593Smuzhiyun 				nf->interlaced_y = 1;
1022*4882a593Smuzhiyun 			if (nf->tru_h < 1021 && (nf->dst_h >= nf->src_h / 2))
1023*4882a593Smuzhiyun 				nf->interlaced_uv = 0;
1024*4882a593Smuzhiyun 			else
1025*4882a593Smuzhiyun 				nf->interlaced_uv = 1;
1026*4882a593Smuzhiyun 		} else {
1027*4882a593Smuzhiyun 			nf->interlaced = 1;
1028*4882a593Smuzhiyun 			nf->interlaced_y = 1;
1029*4882a593Smuzhiyun 			nf->interlaced_uv = 1;
1030*4882a593Smuzhiyun 		}
1031*4882a593Smuzhiyun 		break;
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 	case IVTV_YUV_MODE_INTERLACED: /* Interlace mode */
1034*4882a593Smuzhiyun 	default:
1035*4882a593Smuzhiyun 		nf->interlaced = 1;
1036*4882a593Smuzhiyun 		nf->interlaced_y = 1;
1037*4882a593Smuzhiyun 		nf->interlaced_uv = 1;
1038*4882a593Smuzhiyun 		break;
1039*4882a593Smuzhiyun 	}
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	if (memcmp(&yi->old_frame_info_args, nf, sizeof(*nf))) {
1042*4882a593Smuzhiyun 		yi->old_frame_info_args = *nf;
1043*4882a593Smuzhiyun 		nf->update = 1;
1044*4882a593Smuzhiyun 		IVTV_DEBUG_YUV("Requesting reg update for frame %d\n", frame);
1045*4882a593Smuzhiyun 	}
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	nf->update |= update;
1048*4882a593Smuzhiyun 	nf->sync_field = yi->lace_sync_field;
1049*4882a593Smuzhiyun 	nf->delay = nf->sync_field != of->sync_field;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun /* Frame is complete & ready for display */
ivtv_yuv_frame_complete(struct ivtv * itv)1053*4882a593Smuzhiyun void ivtv_yuv_frame_complete(struct ivtv *itv)
1054*4882a593Smuzhiyun {
1055*4882a593Smuzhiyun 	atomic_set(&itv->yuv_info.next_fill_frame,
1056*4882a593Smuzhiyun 			(itv->yuv_info.draw_frame + 1) % IVTV_YUV_BUFFERS);
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun 
ivtv_yuv_udma_frame(struct ivtv * itv,struct ivtv_dma_frame * args)1059*4882a593Smuzhiyun static int ivtv_yuv_udma_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
1060*4882a593Smuzhiyun {
1061*4882a593Smuzhiyun 	DEFINE_WAIT(wait);
1062*4882a593Smuzhiyun 	int rc = 0;
1063*4882a593Smuzhiyun 	int got_sig = 0;
1064*4882a593Smuzhiyun 	/* DMA the frame */
1065*4882a593Smuzhiyun 	mutex_lock(&itv->udma.lock);
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	if ((rc = ivtv_yuv_prep_user_dma(itv, &itv->udma, args)) != 0) {
1068*4882a593Smuzhiyun 		mutex_unlock(&itv->udma.lock);
1069*4882a593Smuzhiyun 		return rc;
1070*4882a593Smuzhiyun 	}
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	ivtv_udma_prepare(itv);
1073*4882a593Smuzhiyun 	prepare_to_wait(&itv->dma_waitq, &wait, TASK_INTERRUPTIBLE);
1074*4882a593Smuzhiyun 	/* if no UDMA is pending and no UDMA is in progress, then the DMA
1075*4882a593Smuzhiyun 	   is finished */
1076*4882a593Smuzhiyun 	while (test_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags) ||
1077*4882a593Smuzhiyun 	       test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
1078*4882a593Smuzhiyun 		/* don't interrupt if the DMA is in progress but break off
1079*4882a593Smuzhiyun 		   a still pending DMA. */
1080*4882a593Smuzhiyun 		got_sig = signal_pending(current);
1081*4882a593Smuzhiyun 		if (got_sig && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags))
1082*4882a593Smuzhiyun 			break;
1083*4882a593Smuzhiyun 		got_sig = 0;
1084*4882a593Smuzhiyun 		schedule();
1085*4882a593Smuzhiyun 	}
1086*4882a593Smuzhiyun 	finish_wait(&itv->dma_waitq, &wait);
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	/* Unmap Last DMA Xfer */
1089*4882a593Smuzhiyun 	ivtv_udma_unmap(itv);
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	if (got_sig) {
1092*4882a593Smuzhiyun 		IVTV_DEBUG_INFO("User stopped YUV UDMA\n");
1093*4882a593Smuzhiyun 		mutex_unlock(&itv->udma.lock);
1094*4882a593Smuzhiyun 		return -EINTR;
1095*4882a593Smuzhiyun 	}
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	ivtv_yuv_frame_complete(itv);
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	mutex_unlock(&itv->udma.lock);
1100*4882a593Smuzhiyun 	return rc;
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun /* Setup frame according to V4L2 parameters */
ivtv_yuv_setup_stream_frame(struct ivtv * itv)1104*4882a593Smuzhiyun void ivtv_yuv_setup_stream_frame(struct ivtv *itv)
1105*4882a593Smuzhiyun {
1106*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
1107*4882a593Smuzhiyun 	struct ivtv_dma_frame dma_args;
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 	ivtv_yuv_next_free(itv);
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	/* Copy V4L2 parameters to an ivtv_dma_frame struct... */
1112*4882a593Smuzhiyun 	dma_args.y_source = NULL;
1113*4882a593Smuzhiyun 	dma_args.uv_source = NULL;
1114*4882a593Smuzhiyun 	dma_args.src.left = 0;
1115*4882a593Smuzhiyun 	dma_args.src.top = 0;
1116*4882a593Smuzhiyun 	dma_args.src.width = yi->v4l2_src_w;
1117*4882a593Smuzhiyun 	dma_args.src.height = yi->v4l2_src_h;
1118*4882a593Smuzhiyun 	dma_args.dst = yi->main_rect;
1119*4882a593Smuzhiyun 	dma_args.src_width = yi->v4l2_src_w;
1120*4882a593Smuzhiyun 	dma_args.src_height = yi->v4l2_src_h;
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	/* ... and use the same setup routine as ivtv_yuv_prep_frame */
1123*4882a593Smuzhiyun 	ivtv_yuv_setup_frame(itv, &dma_args);
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	if (!itv->dma_data_req_offset)
1126*4882a593Smuzhiyun 		itv->dma_data_req_offset = yuv_offset[yi->draw_frame];
1127*4882a593Smuzhiyun }
1128*4882a593Smuzhiyun 
1129*4882a593Smuzhiyun /* Attempt to dma a frame from a user buffer */
ivtv_yuv_udma_stream_frame(struct ivtv * itv,void __user * src)1130*4882a593Smuzhiyun int ivtv_yuv_udma_stream_frame(struct ivtv *itv, void __user *src)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
1133*4882a593Smuzhiyun 	struct ivtv_dma_frame dma_args;
1134*4882a593Smuzhiyun 	int res;
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 	ivtv_yuv_setup_stream_frame(itv);
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	/* We only need to supply source addresses for this */
1139*4882a593Smuzhiyun 	dma_args.y_source = src;
1140*4882a593Smuzhiyun 	dma_args.uv_source = src + 720 * ((yi->v4l2_src_h + 31) & ~31);
1141*4882a593Smuzhiyun 	/* Wait for frame DMA. Note that serialize_lock is locked,
1142*4882a593Smuzhiyun 	   so to allow other processes to access the driver while
1143*4882a593Smuzhiyun 	   we are waiting unlock first and later lock again. */
1144*4882a593Smuzhiyun 	mutex_unlock(&itv->serialize_lock);
1145*4882a593Smuzhiyun 	res = ivtv_yuv_udma_frame(itv, &dma_args);
1146*4882a593Smuzhiyun 	mutex_lock(&itv->serialize_lock);
1147*4882a593Smuzhiyun 	return res;
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun /* IVTV_IOC_DMA_FRAME ioctl handler */
ivtv_yuv_prep_frame(struct ivtv * itv,struct ivtv_dma_frame * args)1151*4882a593Smuzhiyun int ivtv_yuv_prep_frame(struct ivtv *itv, struct ivtv_dma_frame *args)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun 	int res;
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun /*	IVTV_DEBUG_INFO("yuv_prep_frame\n"); */
1156*4882a593Smuzhiyun 	ivtv_yuv_next_free(itv);
1157*4882a593Smuzhiyun 	ivtv_yuv_setup_frame(itv, args);
1158*4882a593Smuzhiyun 	/* Wait for frame DMA. Note that serialize_lock is locked,
1159*4882a593Smuzhiyun 	   so to allow other processes to access the driver while
1160*4882a593Smuzhiyun 	   we are waiting unlock first and later lock again. */
1161*4882a593Smuzhiyun 	mutex_unlock(&itv->serialize_lock);
1162*4882a593Smuzhiyun 	res = ivtv_yuv_udma_frame(itv, args);
1163*4882a593Smuzhiyun 	mutex_lock(&itv->serialize_lock);
1164*4882a593Smuzhiyun 	return res;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun 
ivtv_yuv_close(struct ivtv * itv)1167*4882a593Smuzhiyun void ivtv_yuv_close(struct ivtv *itv)
1168*4882a593Smuzhiyun {
1169*4882a593Smuzhiyun 	struct yuv_playback_info *yi = &itv->yuv_info;
1170*4882a593Smuzhiyun 	int h_filter, v_filter_1, v_filter_2;
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	IVTV_DEBUG_YUV("ivtv_yuv_close\n");
1173*4882a593Smuzhiyun 	mutex_unlock(&itv->serialize_lock);
1174*4882a593Smuzhiyun 	ivtv_waitq(&itv->vsync_waitq);
1175*4882a593Smuzhiyun 	mutex_lock(&itv->serialize_lock);
1176*4882a593Smuzhiyun 
1177*4882a593Smuzhiyun 	yi->running = 0;
1178*4882a593Smuzhiyun 	atomic_set(&yi->next_dma_frame, -1);
1179*4882a593Smuzhiyun 	atomic_set(&yi->next_fill_frame, 0);
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	/* Reset registers we have changed so mpeg playback works */
1182*4882a593Smuzhiyun 
1183*4882a593Smuzhiyun 	/* If we fully restore this register, the display may remain active.
1184*4882a593Smuzhiyun 	   Restore, but set one bit to blank the video. Firmware will always
1185*4882a593Smuzhiyun 	   clear this bit when needed, so not a problem. */
1186*4882a593Smuzhiyun 	write_reg(yi->reg_2898 | 0x01000000, 0x2898);
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun 	write_reg(yi->reg_2834, 0x02834);
1189*4882a593Smuzhiyun 	write_reg(yi->reg_2838, 0x02838);
1190*4882a593Smuzhiyun 	write_reg(yi->reg_283c, 0x0283c);
1191*4882a593Smuzhiyun 	write_reg(yi->reg_2840, 0x02840);
1192*4882a593Smuzhiyun 	write_reg(yi->reg_2844, 0x02844);
1193*4882a593Smuzhiyun 	write_reg(yi->reg_2848, 0x02848);
1194*4882a593Smuzhiyun 	write_reg(yi->reg_2854, 0x02854);
1195*4882a593Smuzhiyun 	write_reg(yi->reg_285c, 0x0285c);
1196*4882a593Smuzhiyun 	write_reg(yi->reg_2864, 0x02864);
1197*4882a593Smuzhiyun 	write_reg(yi->reg_2870, 0x02870);
1198*4882a593Smuzhiyun 	write_reg(yi->reg_2874, 0x02874);
1199*4882a593Smuzhiyun 	write_reg(yi->reg_2890, 0x02890);
1200*4882a593Smuzhiyun 	write_reg(yi->reg_289c, 0x0289c);
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	write_reg(yi->reg_2918, 0x02918);
1203*4882a593Smuzhiyun 	write_reg(yi->reg_291c, 0x0291c);
1204*4882a593Smuzhiyun 	write_reg(yi->reg_2920, 0x02920);
1205*4882a593Smuzhiyun 	write_reg(yi->reg_2924, 0x02924);
1206*4882a593Smuzhiyun 	write_reg(yi->reg_2928, 0x02928);
1207*4882a593Smuzhiyun 	write_reg(yi->reg_292c, 0x0292c);
1208*4882a593Smuzhiyun 	write_reg(yi->reg_2930, 0x02930);
1209*4882a593Smuzhiyun 	write_reg(yi->reg_2934, 0x02934);
1210*4882a593Smuzhiyun 	write_reg(yi->reg_2938, 0x02938);
1211*4882a593Smuzhiyun 	write_reg(yi->reg_293c, 0x0293c);
1212*4882a593Smuzhiyun 	write_reg(yi->reg_2940, 0x02940);
1213*4882a593Smuzhiyun 	write_reg(yi->reg_2944, 0x02944);
1214*4882a593Smuzhiyun 	write_reg(yi->reg_2948, 0x02948);
1215*4882a593Smuzhiyun 	write_reg(yi->reg_294c, 0x0294c);
1216*4882a593Smuzhiyun 	write_reg(yi->reg_2950, 0x02950);
1217*4882a593Smuzhiyun 	write_reg(yi->reg_2954, 0x02954);
1218*4882a593Smuzhiyun 	write_reg(yi->reg_2958, 0x02958);
1219*4882a593Smuzhiyun 	write_reg(yi->reg_295c, 0x0295c);
1220*4882a593Smuzhiyun 	write_reg(yi->reg_2960, 0x02960);
1221*4882a593Smuzhiyun 	write_reg(yi->reg_2964, 0x02964);
1222*4882a593Smuzhiyun 	write_reg(yi->reg_2968, 0x02968);
1223*4882a593Smuzhiyun 	write_reg(yi->reg_296c, 0x0296c);
1224*4882a593Smuzhiyun 	write_reg(yi->reg_2970, 0x02970);
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	/* Prepare to restore filters */
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 	/* First the horizontal filter */
1229*4882a593Smuzhiyun 	if ((yi->reg_2834 & 0x0000FFFF) == (yi->reg_2834 >> 16)) {
1230*4882a593Smuzhiyun 		/* An exact size match uses filter 0 */
1231*4882a593Smuzhiyun 		h_filter = 0;
1232*4882a593Smuzhiyun 	} else {
1233*4882a593Smuzhiyun 		/* Figure out which filter to use */
1234*4882a593Smuzhiyun 		h_filter = ((yi->reg_2834 << 16) / (yi->reg_2834 >> 16)) >> 15;
1235*4882a593Smuzhiyun 		h_filter = (h_filter >> 1) + (h_filter & 1);
1236*4882a593Smuzhiyun 		/* Only an exact size match can use filter 0. */
1237*4882a593Smuzhiyun 		h_filter += !h_filter;
1238*4882a593Smuzhiyun 	}
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	/* Now the vertical filter */
1241*4882a593Smuzhiyun 	if ((yi->reg_2918 & 0x0000FFFF) == (yi->reg_2918 >> 16)) {
1242*4882a593Smuzhiyun 		/* An exact size match uses filter 0/1 */
1243*4882a593Smuzhiyun 		v_filter_1 = 0;
1244*4882a593Smuzhiyun 		v_filter_2 = 1;
1245*4882a593Smuzhiyun 	} else {
1246*4882a593Smuzhiyun 		/* Figure out which filter to use */
1247*4882a593Smuzhiyun 		v_filter_1 = ((yi->reg_2918 << 16) / (yi->reg_2918 >> 16)) >> 15;
1248*4882a593Smuzhiyun 		v_filter_1 = (v_filter_1 >> 1) + (v_filter_1 & 1);
1249*4882a593Smuzhiyun 		/* Only an exact size match can use filter 0 */
1250*4882a593Smuzhiyun 		v_filter_1 += !v_filter_1;
1251*4882a593Smuzhiyun 		v_filter_2 = v_filter_1;
1252*4882a593Smuzhiyun 	}
1253*4882a593Smuzhiyun 
1254*4882a593Smuzhiyun 	/* Now restore the filters */
1255*4882a593Smuzhiyun 	ivtv_yuv_filter(itv, h_filter, v_filter_1, v_filter_2);
1256*4882a593Smuzhiyun 
1257*4882a593Smuzhiyun 	/* and clear a few registers */
1258*4882a593Smuzhiyun 	write_reg(0, 0x02814);
1259*4882a593Smuzhiyun 	write_reg(0, 0x0282c);
1260*4882a593Smuzhiyun 	write_reg(0, 0x02904);
1261*4882a593Smuzhiyun 	write_reg(0, 0x02910);
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	/* Release the blanking buffer */
1264*4882a593Smuzhiyun 	if (yi->blanking_ptr) {
1265*4882a593Smuzhiyun 		kfree(yi->blanking_ptr);
1266*4882a593Smuzhiyun 		yi->blanking_ptr = NULL;
1267*4882a593Smuzhiyun 		pci_unmap_single(itv->pdev, yi->blanking_dmaptr, 720*16, PCI_DMA_TODEVICE);
1268*4882a593Smuzhiyun 	}
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	/* Invalidate the old dimension information */
1271*4882a593Smuzhiyun 	yi->old_frame_info.src_w = 0;
1272*4882a593Smuzhiyun 	yi->old_frame_info.src_h = 0;
1273*4882a593Smuzhiyun 	yi->old_frame_info_args.src_w = 0;
1274*4882a593Smuzhiyun 	yi->old_frame_info_args.src_h = 0;
1275*4882a593Smuzhiyun 
1276*4882a593Smuzhiyun 	/* All done. */
1277*4882a593Smuzhiyun 	clear_bit(IVTV_F_I_DECODING_YUV, &itv->i_flags);
1278*4882a593Smuzhiyun }
1279