1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun User DMA
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
6*4882a593Smuzhiyun Copyright (C) 2004 Chris Kennedy <c@groovy.org>
7*4882a593Smuzhiyun Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ivtv-driver.h"
12*4882a593Smuzhiyun #include "ivtv-udma.h"
13*4882a593Smuzhiyun
ivtv_udma_get_page_info(struct ivtv_dma_page_info * dma_page,unsigned long first,unsigned long size)14*4882a593Smuzhiyun void ivtv_udma_get_page_info(struct ivtv_dma_page_info *dma_page, unsigned long first, unsigned long size)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun dma_page->uaddr = first & PAGE_MASK;
17*4882a593Smuzhiyun dma_page->offset = first & ~PAGE_MASK;
18*4882a593Smuzhiyun dma_page->tail = 1 + ((first+size-1) & ~PAGE_MASK);
19*4882a593Smuzhiyun dma_page->first = (first & PAGE_MASK) >> PAGE_SHIFT;
20*4882a593Smuzhiyun dma_page->last = ((first+size-1) & PAGE_MASK) >> PAGE_SHIFT;
21*4882a593Smuzhiyun dma_page->page_count = dma_page->last - dma_page->first + 1;
22*4882a593Smuzhiyun if (dma_page->page_count == 1) dma_page->tail -= dma_page->offset;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
ivtv_udma_fill_sg_list(struct ivtv_user_dma * dma,struct ivtv_dma_page_info * dma_page,int map_offset)25*4882a593Smuzhiyun int ivtv_udma_fill_sg_list (struct ivtv_user_dma *dma, struct ivtv_dma_page_info *dma_page, int map_offset)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun int i, offset;
28*4882a593Smuzhiyun unsigned long flags;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (map_offset < 0)
31*4882a593Smuzhiyun return map_offset;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun offset = dma_page->offset;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Fill SG Array with new values */
36*4882a593Smuzhiyun for (i = 0; i < dma_page->page_count; i++) {
37*4882a593Smuzhiyun unsigned int len = (i == dma_page->page_count - 1) ?
38*4882a593Smuzhiyun dma_page->tail : PAGE_SIZE - offset;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (PageHighMem(dma->map[map_offset])) {
41*4882a593Smuzhiyun void *src;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (dma->bouncemap[map_offset] == NULL)
44*4882a593Smuzhiyun dma->bouncemap[map_offset] = alloc_page(GFP_KERNEL);
45*4882a593Smuzhiyun if (dma->bouncemap[map_offset] == NULL)
46*4882a593Smuzhiyun return -1;
47*4882a593Smuzhiyun local_irq_save(flags);
48*4882a593Smuzhiyun src = kmap_atomic(dma->map[map_offset]) + offset;
49*4882a593Smuzhiyun memcpy(page_address(dma->bouncemap[map_offset]) + offset, src, len);
50*4882a593Smuzhiyun kunmap_atomic(src);
51*4882a593Smuzhiyun local_irq_restore(flags);
52*4882a593Smuzhiyun sg_set_page(&dma->SGlist[map_offset], dma->bouncemap[map_offset], len, offset);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun else {
55*4882a593Smuzhiyun sg_set_page(&dma->SGlist[map_offset], dma->map[map_offset], len, offset);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun offset = 0;
58*4882a593Smuzhiyun map_offset++;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun return map_offset;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
ivtv_udma_fill_sg_array(struct ivtv_user_dma * dma,u32 buffer_offset,u32 buffer_offset_2,u32 split)63*4882a593Smuzhiyun void ivtv_udma_fill_sg_array (struct ivtv_user_dma *dma, u32 buffer_offset, u32 buffer_offset_2, u32 split) {
64*4882a593Smuzhiyun int i;
65*4882a593Smuzhiyun struct scatterlist *sg;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun for_each_sg(dma->SGlist, sg, dma->SG_length, i) {
68*4882a593Smuzhiyun dma->SGarray[i].size = cpu_to_le32(sg_dma_len(sg));
69*4882a593Smuzhiyun dma->SGarray[i].src = cpu_to_le32(sg_dma_address(sg));
70*4882a593Smuzhiyun dma->SGarray[i].dst = cpu_to_le32(buffer_offset);
71*4882a593Smuzhiyun buffer_offset += sg_dma_len(sg);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun split -= sg_dma_len(sg);
74*4882a593Smuzhiyun if (split == 0)
75*4882a593Smuzhiyun buffer_offset = buffer_offset_2;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* User DMA Buffers */
ivtv_udma_alloc(struct ivtv * itv)80*4882a593Smuzhiyun void ivtv_udma_alloc(struct ivtv *itv)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun if (itv->udma.SG_handle == 0) {
83*4882a593Smuzhiyun /* Map DMA Page Array Buffer */
84*4882a593Smuzhiyun itv->udma.SG_handle = pci_map_single(itv->pdev, itv->udma.SGarray,
85*4882a593Smuzhiyun sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE);
86*4882a593Smuzhiyun ivtv_udma_sync_for_cpu(itv);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
ivtv_udma_setup(struct ivtv * itv,unsigned long ivtv_dest_addr,void __user * userbuf,int size_in_bytes)90*4882a593Smuzhiyun int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
91*4882a593Smuzhiyun void __user *userbuf, int size_in_bytes)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct ivtv_dma_page_info user_dma;
94*4882a593Smuzhiyun struct ivtv_user_dma *dma = &itv->udma;
95*4882a593Smuzhiyun int err;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun IVTV_DEBUG_DMA("ivtv_udma_setup, dst: 0x%08x\n", (unsigned int)ivtv_dest_addr);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Still in USE */
100*4882a593Smuzhiyun if (dma->SG_length || dma->page_count) {
101*4882a593Smuzhiyun IVTV_DEBUG_WARN("ivtv_udma_setup: SG_length %d page_count %d still full?\n",
102*4882a593Smuzhiyun dma->SG_length, dma->page_count);
103*4882a593Smuzhiyun return -EBUSY;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun ivtv_udma_get_page_info(&user_dma, (unsigned long)userbuf, size_in_bytes);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (user_dma.page_count <= 0) {
109*4882a593Smuzhiyun IVTV_DEBUG_WARN("ivtv_udma_setup: Error %d page_count from %d bytes %d offset\n",
110*4882a593Smuzhiyun user_dma.page_count, size_in_bytes, user_dma.offset);
111*4882a593Smuzhiyun return -EINVAL;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Pin user pages for DMA Xfer */
115*4882a593Smuzhiyun err = pin_user_pages_unlocked(user_dma.uaddr, user_dma.page_count,
116*4882a593Smuzhiyun dma->map, FOLL_FORCE);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (user_dma.page_count != err) {
119*4882a593Smuzhiyun IVTV_DEBUG_WARN("failed to map user pages, returned %d instead of %d\n",
120*4882a593Smuzhiyun err, user_dma.page_count);
121*4882a593Smuzhiyun if (err >= 0) {
122*4882a593Smuzhiyun unpin_user_pages(dma->map, err);
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun return err;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun dma->page_count = user_dma.page_count;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* Fill SG List with new values */
131*4882a593Smuzhiyun if (ivtv_udma_fill_sg_list(dma, &user_dma, 0) < 0) {
132*4882a593Smuzhiyun unpin_user_pages(dma->map, dma->page_count);
133*4882a593Smuzhiyun dma->page_count = 0;
134*4882a593Smuzhiyun return -ENOMEM;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Map SG List */
138*4882a593Smuzhiyun dma->SG_length = pci_map_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Fill SG Array with new values */
141*4882a593Smuzhiyun ivtv_udma_fill_sg_array (dma, ivtv_dest_addr, 0, -1);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Tag SG Array with Interrupt Bit */
144*4882a593Smuzhiyun dma->SGarray[dma->SG_length - 1].size |= cpu_to_le32(0x80000000);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun ivtv_udma_sync_for_device(itv);
147*4882a593Smuzhiyun return dma->page_count;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
ivtv_udma_unmap(struct ivtv * itv)150*4882a593Smuzhiyun void ivtv_udma_unmap(struct ivtv *itv)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct ivtv_user_dma *dma = &itv->udma;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun IVTV_DEBUG_INFO("ivtv_unmap_user_dma\n");
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Nothing to free */
157*4882a593Smuzhiyun if (dma->page_count == 0)
158*4882a593Smuzhiyun return;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* Unmap Scatterlist */
161*4882a593Smuzhiyun if (dma->SG_length) {
162*4882a593Smuzhiyun pci_unmap_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE);
163*4882a593Smuzhiyun dma->SG_length = 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun /* sync DMA */
166*4882a593Smuzhiyun ivtv_udma_sync_for_cpu(itv);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun unpin_user_pages(dma->map, dma->page_count);
169*4882a593Smuzhiyun dma->page_count = 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
ivtv_udma_free(struct ivtv * itv)172*4882a593Smuzhiyun void ivtv_udma_free(struct ivtv *itv)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int i;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* Unmap SG Array */
177*4882a593Smuzhiyun if (itv->udma.SG_handle) {
178*4882a593Smuzhiyun pci_unmap_single(itv->pdev, itv->udma.SG_handle,
179*4882a593Smuzhiyun sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* Unmap Scatterlist */
183*4882a593Smuzhiyun if (itv->udma.SG_length) {
184*4882a593Smuzhiyun pci_unmap_sg(itv->pdev, itv->udma.SGlist, itv->udma.page_count, PCI_DMA_TODEVICE);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun for (i = 0; i < IVTV_DMA_SG_OSD_ENT; i++) {
188*4882a593Smuzhiyun if (itv->udma.bouncemap[i])
189*4882a593Smuzhiyun __free_page(itv->udma.bouncemap[i]);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
ivtv_udma_start(struct ivtv * itv)193*4882a593Smuzhiyun void ivtv_udma_start(struct ivtv *itv)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun IVTV_DEBUG_DMA("start UDMA\n");
196*4882a593Smuzhiyun write_reg(itv->udma.SG_handle, IVTV_REG_DECDMAADDR);
197*4882a593Smuzhiyun write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
198*4882a593Smuzhiyun set_bit(IVTV_F_I_DMA, &itv->i_flags);
199*4882a593Smuzhiyun set_bit(IVTV_F_I_UDMA, &itv->i_flags);
200*4882a593Smuzhiyun clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
ivtv_udma_prepare(struct ivtv * itv)203*4882a593Smuzhiyun void ivtv_udma_prepare(struct ivtv *itv)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun unsigned long flags;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun spin_lock_irqsave(&itv->dma_reg_lock, flags);
208*4882a593Smuzhiyun if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
209*4882a593Smuzhiyun ivtv_udma_start(itv);
210*4882a593Smuzhiyun else
211*4882a593Smuzhiyun set_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags);
212*4882a593Smuzhiyun spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
213*4882a593Smuzhiyun }
214