xref: /OK3568_Linux_fs/kernel/drivers/media/pci/ivtv/ivtv-driver.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun     ivtv driver internal defines and structures
3*4882a593Smuzhiyun     Copyright (C) 2003-2004  Kevin Thayer <nufan_wfk at yahoo.com>
4*4882a593Smuzhiyun     Copyright (C) 2004  Chris Kennedy <c@groovy.org>
5*4882a593Smuzhiyun     Copyright (C) 2005-2007  Hans Verkuil <hverkuil@xs4all.nl>
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun     This program is free software; you can redistribute it and/or modify
8*4882a593Smuzhiyun     it under the terms of the GNU General Public License as published by
9*4882a593Smuzhiyun     the Free Software Foundation; either version 2 of the License, or
10*4882a593Smuzhiyun     (at your option) any later version.
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun     This program is distributed in the hope that it will be useful,
13*4882a593Smuzhiyun     but WITHOUT ANY WARRANTY; without even the implied warranty of
14*4882a593Smuzhiyun     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*4882a593Smuzhiyun     GNU General Public License for more details.
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun     You should have received a copy of the GNU General Public License
18*4882a593Smuzhiyun     along with this program; if not, write to the Free Software
19*4882a593Smuzhiyun     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #ifndef IVTV_DRIVER_H
23*4882a593Smuzhiyun #define IVTV_DRIVER_H
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Internal header for ivtv project:
28*4882a593Smuzhiyun  * Driver for the cx23415/6 chip.
29*4882a593Smuzhiyun  * Author: Kevin Thayer (nufan_wfk at yahoo.com)
30*4882a593Smuzhiyun  * License: GPL
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  * -----
33*4882a593Smuzhiyun  * MPG600/MPG160 support by  T.Adachi <tadachi@tadachi-net.com>
34*4882a593Smuzhiyun  *                      and Takeru KOMORIYA<komoriya@paken.org>
35*4882a593Smuzhiyun  *
36*4882a593Smuzhiyun  * AVerMedia M179 GPIO info by Chris Pinkham <cpinkham@bc2va.org>
37*4882a593Smuzhiyun  *                using information provided by Jiun-Kuei Jung @ AVerMedia.
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #include <linux/module.h>
41*4882a593Smuzhiyun #include <linux/init.h>
42*4882a593Smuzhiyun #include <linux/delay.h>
43*4882a593Smuzhiyun #include <linux/sched/signal.h>
44*4882a593Smuzhiyun #include <linux/fs.h>
45*4882a593Smuzhiyun #include <linux/pci.h>
46*4882a593Smuzhiyun #include <linux/interrupt.h>
47*4882a593Smuzhiyun #include <linux/spinlock.h>
48*4882a593Smuzhiyun #include <linux/i2c.h>
49*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h>
50*4882a593Smuzhiyun #include <linux/list.h>
51*4882a593Smuzhiyun #include <linux/unistd.h>
52*4882a593Smuzhiyun #include <linux/pagemap.h>
53*4882a593Smuzhiyun #include <linux/scatterlist.h>
54*4882a593Smuzhiyun #include <linux/kthread.h>
55*4882a593Smuzhiyun #include <linux/mutex.h>
56*4882a593Smuzhiyun #include <linux/slab.h>
57*4882a593Smuzhiyun #include <linux/uaccess.h>
58*4882a593Smuzhiyun #include <asm/byteorder.h>
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #include <linux/dvb/video.h>
61*4882a593Smuzhiyun #include <linux/dvb/audio.h>
62*4882a593Smuzhiyun #include <media/v4l2-common.h>
63*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
64*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
65*4882a593Smuzhiyun #include <media/v4l2-device.h>
66*4882a593Smuzhiyun #include <media/v4l2-fh.h>
67*4882a593Smuzhiyun #include <media/tuner.h>
68*4882a593Smuzhiyun #include <media/drv-intf/cx2341x.h>
69*4882a593Smuzhiyun #include <media/i2c/ir-kbd-i2c.h>
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #include <linux/ivtv.h>
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* Memory layout */
74*4882a593Smuzhiyun #define IVTV_ENCODER_OFFSET	0x00000000
75*4882a593Smuzhiyun #define IVTV_ENCODER_SIZE	0x00800000	/* Total size is 0x01000000, but only first half is used */
76*4882a593Smuzhiyun #define IVTV_DECODER_OFFSET	0x01000000
77*4882a593Smuzhiyun #define IVTV_DECODER_SIZE	0x00800000	/* Total size is 0x01000000, but only first half is used */
78*4882a593Smuzhiyun #define IVTV_REG_OFFSET		0x02000000
79*4882a593Smuzhiyun #define IVTV_REG_SIZE		0x00010000
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* Maximum ivtv driver instances. Some people have a huge number of
82*4882a593Smuzhiyun    capture cards, so set this to a high value. */
83*4882a593Smuzhiyun #define IVTV_MAX_CARDS 32
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define IVTV_ENC_STREAM_TYPE_MPG  0
86*4882a593Smuzhiyun #define IVTV_ENC_STREAM_TYPE_YUV  1
87*4882a593Smuzhiyun #define IVTV_ENC_STREAM_TYPE_VBI  2
88*4882a593Smuzhiyun #define IVTV_ENC_STREAM_TYPE_PCM  3
89*4882a593Smuzhiyun #define IVTV_ENC_STREAM_TYPE_RAD  4
90*4882a593Smuzhiyun #define IVTV_DEC_STREAM_TYPE_MPG  5
91*4882a593Smuzhiyun #define IVTV_DEC_STREAM_TYPE_VBI  6
92*4882a593Smuzhiyun #define IVTV_DEC_STREAM_TYPE_VOUT 7
93*4882a593Smuzhiyun #define IVTV_DEC_STREAM_TYPE_YUV  8
94*4882a593Smuzhiyun #define IVTV_MAX_STREAMS	  9
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define IVTV_DMA_SG_OSD_ENT	(2883584/PAGE_SIZE)	/* sg entities */
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* DMA Registers */
99*4882a593Smuzhiyun #define IVTV_REG_DMAXFER	(0x0000)
100*4882a593Smuzhiyun #define IVTV_REG_DMASTATUS	(0x0004)
101*4882a593Smuzhiyun #define IVTV_REG_DECDMAADDR	(0x0008)
102*4882a593Smuzhiyun #define IVTV_REG_ENCDMAADDR	(0x000c)
103*4882a593Smuzhiyun #define IVTV_REG_DMACONTROL	(0x0010)
104*4882a593Smuzhiyun #define IVTV_REG_IRQSTATUS	(0x0040)
105*4882a593Smuzhiyun #define IVTV_REG_IRQMASK	(0x0048)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Setup Registers */
108*4882a593Smuzhiyun #define IVTV_REG_ENC_SDRAM_REFRESH	(0x07F8)
109*4882a593Smuzhiyun #define IVTV_REG_ENC_SDRAM_PRECHARGE	(0x07FC)
110*4882a593Smuzhiyun #define IVTV_REG_DEC_SDRAM_REFRESH	(0x08F8)
111*4882a593Smuzhiyun #define IVTV_REG_DEC_SDRAM_PRECHARGE	(0x08FC)
112*4882a593Smuzhiyun #define IVTV_REG_VDM			(0x2800)
113*4882a593Smuzhiyun #define IVTV_REG_AO			(0x2D00)
114*4882a593Smuzhiyun #define IVTV_REG_BYTEFLUSH		(0x2D24)
115*4882a593Smuzhiyun #define IVTV_REG_SPU			(0x9050)
116*4882a593Smuzhiyun #define IVTV_REG_HW_BLOCKS		(0x9054)
117*4882a593Smuzhiyun #define IVTV_REG_VPU			(0x9058)
118*4882a593Smuzhiyun #define IVTV_REG_APU			(0xA064)
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* Other registers */
121*4882a593Smuzhiyun #define IVTV_REG_DEC_LINE_FIELD		(0x28C0)
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* debugging */
124*4882a593Smuzhiyun extern int ivtv_debug;
125*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
126*4882a593Smuzhiyun extern int ivtv_fw_debug;
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define IVTV_DBGFLG_WARN    (1 << 0)
130*4882a593Smuzhiyun #define IVTV_DBGFLG_INFO    (1 << 1)
131*4882a593Smuzhiyun #define IVTV_DBGFLG_MB      (1 << 2)
132*4882a593Smuzhiyun #define IVTV_DBGFLG_IOCTL   (1 << 3)
133*4882a593Smuzhiyun #define IVTV_DBGFLG_FILE    (1 << 4)
134*4882a593Smuzhiyun #define IVTV_DBGFLG_DMA     (1 << 5)
135*4882a593Smuzhiyun #define IVTV_DBGFLG_IRQ     (1 << 6)
136*4882a593Smuzhiyun #define IVTV_DBGFLG_DEC     (1 << 7)
137*4882a593Smuzhiyun #define IVTV_DBGFLG_YUV     (1 << 8)
138*4882a593Smuzhiyun #define IVTV_DBGFLG_I2C     (1 << 9)
139*4882a593Smuzhiyun /* Flag to turn on high volume debugging */
140*4882a593Smuzhiyun #define IVTV_DBGFLG_HIGHVOL (1 << 10)
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define IVTV_DEBUG(x, type, fmt, args...) \
143*4882a593Smuzhiyun 	do { \
144*4882a593Smuzhiyun 		if ((x) & ivtv_debug) \
145*4882a593Smuzhiyun 			v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args);	\
146*4882a593Smuzhiyun 	} while (0)
147*4882a593Smuzhiyun #define IVTV_DEBUG_WARN(fmt, args...)  IVTV_DEBUG(IVTV_DBGFLG_WARN,  "warn",  fmt , ## args)
148*4882a593Smuzhiyun #define IVTV_DEBUG_INFO(fmt, args...)  IVTV_DEBUG(IVTV_DBGFLG_INFO,  "info",  fmt , ## args)
149*4882a593Smuzhiyun #define IVTV_DEBUG_MB(fmt, args...)    IVTV_DEBUG(IVTV_DBGFLG_MB,    "mb",    fmt , ## args)
150*4882a593Smuzhiyun #define IVTV_DEBUG_DMA(fmt, args...)   IVTV_DEBUG(IVTV_DBGFLG_DMA,   "dma",   fmt , ## args)
151*4882a593Smuzhiyun #define IVTV_DEBUG_IOCTL(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
152*4882a593Smuzhiyun #define IVTV_DEBUG_FILE(fmt, args...)  IVTV_DEBUG(IVTV_DBGFLG_FILE,  "file",  fmt , ## args)
153*4882a593Smuzhiyun #define IVTV_DEBUG_I2C(fmt, args...)   IVTV_DEBUG(IVTV_DBGFLG_I2C,   "i2c",   fmt , ## args)
154*4882a593Smuzhiyun #define IVTV_DEBUG_IRQ(fmt, args...)   IVTV_DEBUG(IVTV_DBGFLG_IRQ,   "irq",   fmt , ## args)
155*4882a593Smuzhiyun #define IVTV_DEBUG_DEC(fmt, args...)   IVTV_DEBUG(IVTV_DBGFLG_DEC,   "dec",   fmt , ## args)
156*4882a593Smuzhiyun #define IVTV_DEBUG_YUV(fmt, args...)   IVTV_DEBUG(IVTV_DBGFLG_YUV,   "yuv",   fmt , ## args)
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \
159*4882a593Smuzhiyun 	do { \
160*4882a593Smuzhiyun 		if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL))	\
161*4882a593Smuzhiyun 			v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args);	\
162*4882a593Smuzhiyun 	} while (0)
163*4882a593Smuzhiyun #define IVTV_DEBUG_HI_WARN(fmt, args...)  IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN,  "warn",  fmt , ## args)
164*4882a593Smuzhiyun #define IVTV_DEBUG_HI_INFO(fmt, args...)  IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_INFO,  "info",  fmt , ## args)
165*4882a593Smuzhiyun #define IVTV_DEBUG_HI_MB(fmt, args...)    IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_MB,    "mb",    fmt , ## args)
166*4882a593Smuzhiyun #define IVTV_DEBUG_HI_DMA(fmt, args...)   IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DMA,   "dma",   fmt , ## args)
167*4882a593Smuzhiyun #define IVTV_DEBUG_HI_IOCTL(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
168*4882a593Smuzhiyun #define IVTV_DEBUG_HI_FILE(fmt, args...)  IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_FILE,  "file",  fmt , ## args)
169*4882a593Smuzhiyun #define IVTV_DEBUG_HI_I2C(fmt, args...)   IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_I2C,   "i2c",   fmt , ## args)
170*4882a593Smuzhiyun #define IVTV_DEBUG_HI_IRQ(fmt, args...)   IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IRQ,   "irq",   fmt , ## args)
171*4882a593Smuzhiyun #define IVTV_DEBUG_HI_DEC(fmt, args...)   IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DEC,   "dec",   fmt , ## args)
172*4882a593Smuzhiyun #define IVTV_DEBUG_HI_YUV(fmt, args...)   IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_YUV,   "yuv",   fmt , ## args)
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /* Standard kernel messages */
175*4882a593Smuzhiyun #define IVTV_ERR(fmt, args...)      v4l2_err(&itv->v4l2_dev, fmt , ## args)
176*4882a593Smuzhiyun #define IVTV_WARN(fmt, args...)     v4l2_warn(&itv->v4l2_dev, fmt , ## args)
177*4882a593Smuzhiyun #define IVTV_INFO(fmt, args...)     v4l2_info(&itv->v4l2_dev, fmt , ## args)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /* output modes (cx23415 only) */
180*4882a593Smuzhiyun #define OUT_NONE        0
181*4882a593Smuzhiyun #define OUT_MPG         1
182*4882a593Smuzhiyun #define OUT_YUV         2
183*4882a593Smuzhiyun #define OUT_UDMA_YUV    3
184*4882a593Smuzhiyun #define OUT_PASSTHROUGH 4
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #define IVTV_MAX_PGM_INDEX (400)
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun /* Default I2C SCL period in microseconds */
189*4882a593Smuzhiyun #define IVTV_DEFAULT_I2C_CLOCK_PERIOD	20
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun struct ivtv_options {
192*4882a593Smuzhiyun 	int kilobytes[IVTV_MAX_STREAMS];        /* size in kilobytes of each stream */
193*4882a593Smuzhiyun 	int cardtype;				/* force card type on load */
194*4882a593Smuzhiyun 	int tuner;				/* set tuner on load */
195*4882a593Smuzhiyun 	int radio;				/* enable/disable radio */
196*4882a593Smuzhiyun 	int newi2c;				/* new I2C algorithm */
197*4882a593Smuzhiyun 	int i2c_clock_period;			/* period of SCL for I2C bus */
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* ivtv-specific mailbox template */
201*4882a593Smuzhiyun struct ivtv_mailbox {
202*4882a593Smuzhiyun 	u32 flags;
203*4882a593Smuzhiyun 	u32 cmd;
204*4882a593Smuzhiyun 	u32 retval;
205*4882a593Smuzhiyun 	u32 timeout;
206*4882a593Smuzhiyun 	u32 data[CX2341X_MBOX_MAX_DATA];
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun struct ivtv_api_cache {
210*4882a593Smuzhiyun 	unsigned long last_jiffies;		/* when last command was issued */
211*4882a593Smuzhiyun 	u32 data[CX2341X_MBOX_MAX_DATA];	/* last sent api data */
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun struct ivtv_mailbox_data {
215*4882a593Smuzhiyun 	volatile struct ivtv_mailbox __iomem *mbox;
216*4882a593Smuzhiyun 	/* Bits 0-2 are for the encoder mailboxes, 0-1 are for the decoder mailboxes.
217*4882a593Smuzhiyun 	   If the bit is set, then the corresponding mailbox is in use by the driver. */
218*4882a593Smuzhiyun 	unsigned long busy;
219*4882a593Smuzhiyun 	u8 max_mbox;
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /* per-buffer bit flags */
223*4882a593Smuzhiyun #define IVTV_F_B_NEED_BUF_SWAP  (1 << 0)	/* this buffer should be byte swapped */
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /* per-stream, s_flags */
226*4882a593Smuzhiyun #define IVTV_F_S_DMA_PENDING	0	/* this stream has pending DMA */
227*4882a593Smuzhiyun #define IVTV_F_S_DMA_HAS_VBI	1       /* the current DMA request also requests VBI data */
228*4882a593Smuzhiyun #define IVTV_F_S_NEEDS_DATA	2	/* this decoding stream needs more data */
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun #define IVTV_F_S_CLAIMED	3	/* this stream is claimed */
231*4882a593Smuzhiyun #define IVTV_F_S_STREAMING      4	/* the fw is decoding/encoding this stream */
232*4882a593Smuzhiyun #define IVTV_F_S_INTERNAL_USE	5	/* this stream is used internally (sliced VBI processing) */
233*4882a593Smuzhiyun #define IVTV_F_S_PASSTHROUGH	6	/* this stream is in passthrough mode */
234*4882a593Smuzhiyun #define IVTV_F_S_STREAMOFF	7	/* signal end of stream EOS */
235*4882a593Smuzhiyun #define IVTV_F_S_APPL_IO        8	/* this stream is used read/written by an application */
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun #define IVTV_F_S_PIO_PENDING	9	/* this stream has pending PIO */
238*4882a593Smuzhiyun #define IVTV_F_S_PIO_HAS_VBI	1       /* the current PIO request also requests VBI data */
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun /* per-ivtv, i_flags */
241*4882a593Smuzhiyun #define IVTV_F_I_DMA		   0	/* DMA in progress */
242*4882a593Smuzhiyun #define IVTV_F_I_UDMA		   1	/* UDMA in progress */
243*4882a593Smuzhiyun #define IVTV_F_I_UDMA_PENDING	   2	/* UDMA pending */
244*4882a593Smuzhiyun #define IVTV_F_I_SPEED_CHANGE	   3	/* a speed change is in progress */
245*4882a593Smuzhiyun #define IVTV_F_I_EOS		   4	/* end of encoder stream reached */
246*4882a593Smuzhiyun #define IVTV_F_I_RADIO_USER	   5	/* the radio tuner is selected */
247*4882a593Smuzhiyun #define IVTV_F_I_DIG_RST	   6	/* reset digitizer */
248*4882a593Smuzhiyun #define IVTV_F_I_DEC_YUV	   7	/* YUV instead of MPG is being decoded */
249*4882a593Smuzhiyun #define IVTV_F_I_UPDATE_CC	   9	/* CC should be updated */
250*4882a593Smuzhiyun #define IVTV_F_I_UPDATE_WSS	   10	/* WSS should be updated */
251*4882a593Smuzhiyun #define IVTV_F_I_UPDATE_VPS	   11	/* VPS should be updated */
252*4882a593Smuzhiyun #define IVTV_F_I_DECODING_YUV	   12	/* this stream is YUV frame decoding */
253*4882a593Smuzhiyun #define IVTV_F_I_ENC_PAUSED	   13	/* the encoder is paused */
254*4882a593Smuzhiyun #define IVTV_F_I_VALID_DEC_TIMINGS 14	/* last_dec_timing is valid */
255*4882a593Smuzhiyun #define IVTV_F_I_HAVE_WORK	   15	/* used in the interrupt handler: there is work to be done */
256*4882a593Smuzhiyun #define IVTV_F_I_WORK_HANDLER_VBI  16	/* there is work to be done for VBI */
257*4882a593Smuzhiyun #define IVTV_F_I_WORK_HANDLER_YUV  17	/* there is work to be done for YUV */
258*4882a593Smuzhiyun #define IVTV_F_I_WORK_HANDLER_PIO  18	/* there is work to be done for PIO */
259*4882a593Smuzhiyun #define IVTV_F_I_PIO		   19	/* PIO in progress */
260*4882a593Smuzhiyun #define IVTV_F_I_DEC_PAUSED	   20	/* the decoder is paused */
261*4882a593Smuzhiyun #define IVTV_F_I_INITED		   21	/* set after first open */
262*4882a593Smuzhiyun #define IVTV_F_I_FAILED		   22	/* set if first open failed */
263*4882a593Smuzhiyun #define IVTV_F_I_WORK_HANDLER_PCM  23	/* there is work to be done for PCM */
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun /* Event notifications */
266*4882a593Smuzhiyun #define IVTV_F_I_EV_DEC_STOPPED	   28	/* decoder stopped event */
267*4882a593Smuzhiyun #define IVTV_F_I_EV_VSYNC	   29	/* VSYNC event */
268*4882a593Smuzhiyun #define IVTV_F_I_EV_VSYNC_FIELD    30	/* VSYNC event field (0 = first, 1 = second field) */
269*4882a593Smuzhiyun #define IVTV_F_I_EV_VSYNC_ENABLED  31	/* VSYNC event enabled */
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /* Scatter-Gather array element, used in DMA transfers */
272*4882a593Smuzhiyun struct ivtv_sg_element {
273*4882a593Smuzhiyun 	__le32 src;
274*4882a593Smuzhiyun 	__le32 dst;
275*4882a593Smuzhiyun 	__le32 size;
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun struct ivtv_sg_host_element {
279*4882a593Smuzhiyun 	u32 src;
280*4882a593Smuzhiyun 	u32 dst;
281*4882a593Smuzhiyun 	u32 size;
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun struct ivtv_user_dma {
285*4882a593Smuzhiyun 	struct mutex lock;
286*4882a593Smuzhiyun 	int page_count;
287*4882a593Smuzhiyun 	struct page *map[IVTV_DMA_SG_OSD_ENT];
288*4882a593Smuzhiyun 	/* Needed when dealing with highmem userspace buffers */
289*4882a593Smuzhiyun 	struct page *bouncemap[IVTV_DMA_SG_OSD_ENT];
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	/* Base Dev SG Array for cx23415/6 */
292*4882a593Smuzhiyun 	struct ivtv_sg_element SGarray[IVTV_DMA_SG_OSD_ENT];
293*4882a593Smuzhiyun 	dma_addr_t SG_handle;
294*4882a593Smuzhiyun 	int SG_length;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	/* SG List of Buffers */
297*4882a593Smuzhiyun 	struct scatterlist SGlist[IVTV_DMA_SG_OSD_ENT];
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun struct ivtv_dma_page_info {
301*4882a593Smuzhiyun 	unsigned long uaddr;
302*4882a593Smuzhiyun 	unsigned long first;
303*4882a593Smuzhiyun 	unsigned long last;
304*4882a593Smuzhiyun 	unsigned int offset;
305*4882a593Smuzhiyun 	unsigned int tail;
306*4882a593Smuzhiyun 	int page_count;
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun struct ivtv_buffer {
310*4882a593Smuzhiyun 	struct list_head list;
311*4882a593Smuzhiyun 	dma_addr_t dma_handle;
312*4882a593Smuzhiyun 	unsigned short b_flags;
313*4882a593Smuzhiyun 	unsigned short dma_xfer_cnt;
314*4882a593Smuzhiyun 	char *buf;
315*4882a593Smuzhiyun 	u32 bytesused;
316*4882a593Smuzhiyun 	u32 readpos;
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun struct ivtv_queue {
320*4882a593Smuzhiyun 	struct list_head list;          /* the list of buffers in this queue */
321*4882a593Smuzhiyun 	u32 buffers;                    /* number of buffers in this queue */
322*4882a593Smuzhiyun 	u32 length;                     /* total number of bytes of available buffer space */
323*4882a593Smuzhiyun 	u32 bytesused;                  /* total number of bytes used in this queue */
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun struct ivtv;				/* forward reference */
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun struct ivtv_stream {
329*4882a593Smuzhiyun 	/* These first four fields are always set, even if the stream
330*4882a593Smuzhiyun 	   is not actually created. */
331*4882a593Smuzhiyun 	struct video_device vdev;	/* vdev.v4l2_dev is NULL if there is no device */
332*4882a593Smuzhiyun 	struct ivtv *itv;		/* for ease of use */
333*4882a593Smuzhiyun 	const char *name;		/* name of the stream */
334*4882a593Smuzhiyun 	int type;			/* stream type */
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	struct v4l2_fh *fh;		/* pointer to the streaming filehandle */
337*4882a593Smuzhiyun 	spinlock_t qlock;		/* locks access to the queues */
338*4882a593Smuzhiyun 	unsigned long s_flags;		/* status flags, see above */
339*4882a593Smuzhiyun 	int dma;			/* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */
340*4882a593Smuzhiyun 	u32 pending_offset;
341*4882a593Smuzhiyun 	u32 pending_backup;
342*4882a593Smuzhiyun 	u64 pending_pts;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	u32 dma_offset;
345*4882a593Smuzhiyun 	u32 dma_backup;
346*4882a593Smuzhiyun 	u64 dma_pts;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	int subtype;
349*4882a593Smuzhiyun 	wait_queue_head_t waitq;
350*4882a593Smuzhiyun 	u32 dma_last_offset;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	/* Buffer Stats */
353*4882a593Smuzhiyun 	u32 buffers;
354*4882a593Smuzhiyun 	u32 buf_size;
355*4882a593Smuzhiyun 	u32 buffers_stolen;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	/* Buffer Queues */
358*4882a593Smuzhiyun 	struct ivtv_queue q_free;	/* free buffers */
359*4882a593Smuzhiyun 	struct ivtv_queue q_full;	/* full buffers */
360*4882a593Smuzhiyun 	struct ivtv_queue q_io;		/* waiting for I/O */
361*4882a593Smuzhiyun 	struct ivtv_queue q_dma;	/* waiting for DMA */
362*4882a593Smuzhiyun 	struct ivtv_queue q_predma;	/* waiting for DMA */
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	/* DMA xfer counter, buffers belonging to the same DMA
365*4882a593Smuzhiyun 	   xfer will have the same dma_xfer_cnt. */
366*4882a593Smuzhiyun 	u16 dma_xfer_cnt;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	/* Base Dev SG Array for cx23415/6 */
369*4882a593Smuzhiyun 	struct ivtv_sg_host_element *sg_pending;
370*4882a593Smuzhiyun 	struct ivtv_sg_host_element *sg_processing;
371*4882a593Smuzhiyun 	struct ivtv_sg_element *sg_dma;
372*4882a593Smuzhiyun 	dma_addr_t sg_handle;
373*4882a593Smuzhiyun 	int sg_pending_size;
374*4882a593Smuzhiyun 	int sg_processing_size;
375*4882a593Smuzhiyun 	int sg_processed;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	/* SG List of Buffers */
378*4882a593Smuzhiyun 	struct scatterlist *SGlist;
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun struct ivtv_open_id {
382*4882a593Smuzhiyun 	struct v4l2_fh fh;
383*4882a593Smuzhiyun 	int type;                       /* stream type */
384*4882a593Smuzhiyun 	int yuv_frames;                 /* 1: started OUT_UDMA_YUV output mode */
385*4882a593Smuzhiyun 	struct ivtv *itv;
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun 
fh2id(struct v4l2_fh * fh)388*4882a593Smuzhiyun static inline struct ivtv_open_id *fh2id(struct v4l2_fh *fh)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun 	return container_of(fh, struct ivtv_open_id, fh);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun struct yuv_frame_info
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	u32 update;
396*4882a593Smuzhiyun 	s32 src_x;
397*4882a593Smuzhiyun 	s32 src_y;
398*4882a593Smuzhiyun 	u32 src_w;
399*4882a593Smuzhiyun 	u32 src_h;
400*4882a593Smuzhiyun 	s32 dst_x;
401*4882a593Smuzhiyun 	s32 dst_y;
402*4882a593Smuzhiyun 	u32 dst_w;
403*4882a593Smuzhiyun 	u32 dst_h;
404*4882a593Smuzhiyun 	s32 pan_x;
405*4882a593Smuzhiyun 	s32 pan_y;
406*4882a593Smuzhiyun 	u32 vis_w;
407*4882a593Smuzhiyun 	u32 vis_h;
408*4882a593Smuzhiyun 	u32 interlaced_y;
409*4882a593Smuzhiyun 	u32 interlaced_uv;
410*4882a593Smuzhiyun 	s32 tru_x;
411*4882a593Smuzhiyun 	u32 tru_w;
412*4882a593Smuzhiyun 	u32 tru_h;
413*4882a593Smuzhiyun 	u32 offset_y;
414*4882a593Smuzhiyun 	s32 lace_mode;
415*4882a593Smuzhiyun 	u32 sync_field;
416*4882a593Smuzhiyun 	u32 delay;
417*4882a593Smuzhiyun 	u32 interlaced;
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun #define IVTV_YUV_MODE_INTERLACED	0x00
421*4882a593Smuzhiyun #define IVTV_YUV_MODE_PROGRESSIVE	0x01
422*4882a593Smuzhiyun #define IVTV_YUV_MODE_AUTO		0x02
423*4882a593Smuzhiyun #define IVTV_YUV_MODE_MASK		0x03
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun #define IVTV_YUV_SYNC_EVEN		0x00
426*4882a593Smuzhiyun #define IVTV_YUV_SYNC_ODD		0x04
427*4882a593Smuzhiyun #define IVTV_YUV_SYNC_MASK		0x04
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun #define IVTV_YUV_BUFFERS 8
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun struct yuv_playback_info
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	u32 reg_2834;
434*4882a593Smuzhiyun 	u32 reg_2838;
435*4882a593Smuzhiyun 	u32 reg_283c;
436*4882a593Smuzhiyun 	u32 reg_2840;
437*4882a593Smuzhiyun 	u32 reg_2844;
438*4882a593Smuzhiyun 	u32 reg_2848;
439*4882a593Smuzhiyun 	u32 reg_2854;
440*4882a593Smuzhiyun 	u32 reg_285c;
441*4882a593Smuzhiyun 	u32 reg_2864;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	u32 reg_2870;
444*4882a593Smuzhiyun 	u32 reg_2874;
445*4882a593Smuzhiyun 	u32 reg_2890;
446*4882a593Smuzhiyun 	u32 reg_2898;
447*4882a593Smuzhiyun 	u32 reg_289c;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	u32 reg_2918;
450*4882a593Smuzhiyun 	u32 reg_291c;
451*4882a593Smuzhiyun 	u32 reg_2920;
452*4882a593Smuzhiyun 	u32 reg_2924;
453*4882a593Smuzhiyun 	u32 reg_2928;
454*4882a593Smuzhiyun 	u32 reg_292c;
455*4882a593Smuzhiyun 	u32 reg_2930;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	u32 reg_2934;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	u32 reg_2938;
460*4882a593Smuzhiyun 	u32 reg_293c;
461*4882a593Smuzhiyun 	u32 reg_2940;
462*4882a593Smuzhiyun 	u32 reg_2944;
463*4882a593Smuzhiyun 	u32 reg_2948;
464*4882a593Smuzhiyun 	u32 reg_294c;
465*4882a593Smuzhiyun 	u32 reg_2950;
466*4882a593Smuzhiyun 	u32 reg_2954;
467*4882a593Smuzhiyun 	u32 reg_2958;
468*4882a593Smuzhiyun 	u32 reg_295c;
469*4882a593Smuzhiyun 	u32 reg_2960;
470*4882a593Smuzhiyun 	u32 reg_2964;
471*4882a593Smuzhiyun 	u32 reg_2968;
472*4882a593Smuzhiyun 	u32 reg_296c;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	u32 reg_2970;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	int v_filter_1;
477*4882a593Smuzhiyun 	int v_filter_2;
478*4882a593Smuzhiyun 	int h_filter;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	u8 track_osd; /* Should yuv output track the OSD size & position */
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	u32 osd_x_offset;
483*4882a593Smuzhiyun 	u32 osd_y_offset;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	u32 osd_x_pan;
486*4882a593Smuzhiyun 	u32 osd_y_pan;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	u32 osd_vis_w;
489*4882a593Smuzhiyun 	u32 osd_vis_h;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	u32 osd_full_w;
492*4882a593Smuzhiyun 	u32 osd_full_h;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	int decode_height;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	int lace_mode;
497*4882a593Smuzhiyun 	int lace_threshold;
498*4882a593Smuzhiyun 	int lace_sync_field;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	atomic_t next_dma_frame;
501*4882a593Smuzhiyun 	atomic_t next_fill_frame;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	u32 yuv_forced_update;
504*4882a593Smuzhiyun 	int update_frame;
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	u8 fields_lapsed;   /* Counter used when delaying a frame */
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	struct yuv_frame_info new_frame_info[IVTV_YUV_BUFFERS];
509*4882a593Smuzhiyun 	struct yuv_frame_info old_frame_info;
510*4882a593Smuzhiyun 	struct yuv_frame_info old_frame_info_args;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	void *blanking_ptr;
513*4882a593Smuzhiyun 	dma_addr_t blanking_dmaptr;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	int stream_size;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	u8 draw_frame; /* PVR350 buffer to draw into */
518*4882a593Smuzhiyun 	u8 max_frames_buffered; /* Maximum number of frames to buffer */
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	struct v4l2_rect main_rect;
521*4882a593Smuzhiyun 	u32 v4l2_src_w;
522*4882a593Smuzhiyun 	u32 v4l2_src_h;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	u8 running; /* Have any frames been displayed */
525*4882a593Smuzhiyun };
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun #define IVTV_VBI_FRAMES 32
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun /* VBI data */
530*4882a593Smuzhiyun struct vbi_cc {
531*4882a593Smuzhiyun 	u8 odd[2];	/* two-byte payload of odd field */
532*4882a593Smuzhiyun 	u8 even[2];	/* two-byte payload of even field */;
533*4882a593Smuzhiyun };
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun struct vbi_vps {
536*4882a593Smuzhiyun 	u8 data[5];	/* five-byte VPS payload */
537*4882a593Smuzhiyun };
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun struct vbi_info {
540*4882a593Smuzhiyun 	/* VBI general data, does not change during streaming */
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	u32 raw_decoder_line_size;              /* raw VBI line size from digitizer */
543*4882a593Smuzhiyun 	u8 raw_decoder_sav_odd_field;           /* raw VBI Start Active Video digitizer code of odd field */
544*4882a593Smuzhiyun 	u8 raw_decoder_sav_even_field;          /* raw VBI Start Active Video digitizer code of even field */
545*4882a593Smuzhiyun 	u32 sliced_decoder_line_size;           /* sliced VBI line size from digitizer */
546*4882a593Smuzhiyun 	u8 sliced_decoder_sav_odd_field;        /* sliced VBI Start Active Video digitizer code of odd field */
547*4882a593Smuzhiyun 	u8 sliced_decoder_sav_even_field;       /* sliced VBI Start Active Video digitizer code of even field */
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	u32 start[2];				/* start of first VBI line in the odd/even fields */
550*4882a593Smuzhiyun 	u32 count;				/* number of VBI lines per field */
551*4882a593Smuzhiyun 	u32 raw_size;				/* size of raw VBI line from the digitizer */
552*4882a593Smuzhiyun 	u32 sliced_size;			/* size of sliced VBI line from the digitizer */
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	u32 dec_start;				/* start in decoder memory of VBI re-insertion buffers */
555*4882a593Smuzhiyun 	u32 enc_start;				/* start in encoder memory of VBI capture buffers */
556*4882a593Smuzhiyun 	u32 enc_size;				/* size of VBI capture area */
557*4882a593Smuzhiyun 	int fpi;				/* number of VBI frames per interrupt */
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	struct v4l2_format in;			/* current VBI capture format */
560*4882a593Smuzhiyun 	struct v4l2_sliced_vbi_format *sliced_in; /* convenience pointer to sliced struct in vbi.in union */
561*4882a593Smuzhiyun 	int insert_mpeg;			/* if non-zero, then embed VBI data in MPEG stream */
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	/* Raw VBI compatibility hack */
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	u32 frame;				/* frame counter hack needed for backwards compatibility
566*4882a593Smuzhiyun 						   of old VBI software */
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	/* Sliced VBI output data */
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	struct vbi_cc cc_payload[256];		/* sliced VBI CC payload array: it is an array to
571*4882a593Smuzhiyun 						   prevent dropping CC data if they couldn't be
572*4882a593Smuzhiyun 						   processed fast enough */
573*4882a593Smuzhiyun 	int cc_payload_idx;			/* index in cc_payload */
574*4882a593Smuzhiyun 	u8 cc_missing_cnt;			/* counts number of frames without CC for passthrough mode */
575*4882a593Smuzhiyun 	int wss_payload;			/* sliced VBI WSS payload */
576*4882a593Smuzhiyun 	u8 wss_missing_cnt;			/* counts number of frames without WSS for passthrough mode */
577*4882a593Smuzhiyun 	struct vbi_vps vps_payload;		/* sliced VBI VPS payload */
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	/* Sliced VBI capture data */
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	struct v4l2_sliced_vbi_data sliced_data[36];	/* sliced VBI storage for VBI encoder stream */
582*4882a593Smuzhiyun 	struct v4l2_sliced_vbi_data sliced_dec_data[36];/* sliced VBI storage for VBI decoder stream */
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	/* VBI Embedding data */
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	/* Buffer for VBI data inserted into MPEG stream.
587*4882a593Smuzhiyun 	   The first byte is a dummy byte that's never used.
588*4882a593Smuzhiyun 	   The next 16 bytes contain the MPEG header for the VBI data,
589*4882a593Smuzhiyun 	   the remainder is the actual VBI data.
590*4882a593Smuzhiyun 	   The max size accepted by the MPEG VBI reinsertion turns out
591*4882a593Smuzhiyun 	   to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes,
592*4882a593Smuzhiyun 	   where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is
593*4882a593Smuzhiyun 	   a single line header byte and 2 * 18 is the number of VBI lines per frame.
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	   However, it seems that the data must be 1K aligned, so we have to
596*4882a593Smuzhiyun 	   pad the data until the 1 or 2 K boundary.
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	   This pointer array will allocate 2049 bytes to store each VBI frame. */
599*4882a593Smuzhiyun 	u8 *sliced_mpeg_data[IVTV_VBI_FRAMES];
600*4882a593Smuzhiyun 	u32 sliced_mpeg_size[IVTV_VBI_FRAMES];
601*4882a593Smuzhiyun 	struct ivtv_buffer sliced_mpeg_buf;	/* temporary buffer holding data from sliced_mpeg_data */
602*4882a593Smuzhiyun 	u32 inserted_frame;			/* index in sliced_mpeg_size of next sliced data
603*4882a593Smuzhiyun 						   to be inserted in the MPEG stream */
604*4882a593Smuzhiyun };
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun /* forward declaration of struct defined in ivtv-cards.h */
607*4882a593Smuzhiyun struct ivtv_card;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun /* Struct to hold info about ivtv cards */
610*4882a593Smuzhiyun struct ivtv {
611*4882a593Smuzhiyun 	/* General fixed card data */
612*4882a593Smuzhiyun 	struct pci_dev *pdev;		/* PCI device */
613*4882a593Smuzhiyun 	const struct ivtv_card *card;	/* card information */
614*4882a593Smuzhiyun 	const char *card_name;          /* full name of the card */
615*4882a593Smuzhiyun 	const struct ivtv_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
616*4882a593Smuzhiyun 	u8 has_cx23415;			/* 1 if it is a cx23415 based card, 0 for cx23416 */
617*4882a593Smuzhiyun 	u8 pvr150_workaround;           /* 1 if the cx25840 needs to workaround a PVR150 bug */
618*4882a593Smuzhiyun 	u8 nof_inputs;			/* number of video inputs */
619*4882a593Smuzhiyun 	u8 nof_audio_inputs;		/* number of audio inputs */
620*4882a593Smuzhiyun 	u32 v4l2_cap;			/* V4L2 capabilities of card */
621*4882a593Smuzhiyun 	u32 hw_flags;			/* hardware description of the board */
622*4882a593Smuzhiyun 	v4l2_std_id tuner_std;		/* the norm of the card's tuner (fixed) */
623*4882a593Smuzhiyun 	struct v4l2_subdev *sd_video;	/* controlling video decoder subdev */
624*4882a593Smuzhiyun 	struct v4l2_subdev *sd_audio;	/* controlling audio subdev */
625*4882a593Smuzhiyun 	struct v4l2_subdev *sd_muxer;	/* controlling audio muxer subdev */
626*4882a593Smuzhiyun 	resource_size_t base_addr;      /* PCI resource base address */
627*4882a593Smuzhiyun 	volatile void __iomem *enc_mem; /* pointer to mapped encoder memory */
628*4882a593Smuzhiyun 	volatile void __iomem *dec_mem; /* pointer to mapped decoder memory */
629*4882a593Smuzhiyun 	volatile void __iomem *reg_mem; /* pointer to mapped registers */
630*4882a593Smuzhiyun 	struct ivtv_options options;	/* user options */
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	struct v4l2_device v4l2_dev;
633*4882a593Smuzhiyun 	struct cx2341x_handler cxhdl;
634*4882a593Smuzhiyun 	struct {
635*4882a593Smuzhiyun 		/* PTS/Frame count control cluster */
636*4882a593Smuzhiyun 		struct v4l2_ctrl *ctrl_pts;
637*4882a593Smuzhiyun 		struct v4l2_ctrl *ctrl_frame;
638*4882a593Smuzhiyun 	};
639*4882a593Smuzhiyun 	struct {
640*4882a593Smuzhiyun 		/* Audio Playback control cluster */
641*4882a593Smuzhiyun 		struct v4l2_ctrl *ctrl_audio_playback;
642*4882a593Smuzhiyun 		struct v4l2_ctrl *ctrl_audio_multilingual_playback;
643*4882a593Smuzhiyun 	};
644*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl_gpio;
645*4882a593Smuzhiyun 	struct v4l2_subdev sd_gpio;	/* GPIO sub-device */
646*4882a593Smuzhiyun 	u16 instance;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	/* High-level state info */
649*4882a593Smuzhiyun 	unsigned long i_flags;          /* global ivtv flags */
650*4882a593Smuzhiyun 	u8 is_50hz;                     /* 1 if the current capture standard is 50 Hz */
651*4882a593Smuzhiyun 	u8 is_60hz                      /* 1 if the current capture standard is 60 Hz */;
652*4882a593Smuzhiyun 	u8 is_out_50hz                  /* 1 if the current TV output standard is 50 Hz */;
653*4882a593Smuzhiyun 	u8 is_out_60hz                  /* 1 if the current TV output standard is 60 Hz */;
654*4882a593Smuzhiyun 	int output_mode;                /* decoder output mode: NONE, MPG, YUV, UDMA YUV, passthrough */
655*4882a593Smuzhiyun 	u32 audio_input;                /* current audio input */
656*4882a593Smuzhiyun 	u32 active_input;               /* current video input */
657*4882a593Smuzhiyun 	u32 active_output;              /* current video output */
658*4882a593Smuzhiyun 	v4l2_std_id std;                /* current capture TV standard */
659*4882a593Smuzhiyun 	v4l2_std_id std_out;            /* current TV output standard */
660*4882a593Smuzhiyun 	u8 audio_stereo_mode;           /* decoder setting how to handle stereo MPEG audio */
661*4882a593Smuzhiyun 	u8 audio_bilingual_mode;        /* decoder setting how to handle bilingual MPEG audio */
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	/* Locking */
664*4882a593Smuzhiyun 	spinlock_t lock;                /* lock access to this struct */
665*4882a593Smuzhiyun 	struct mutex serialize_lock;    /* mutex used to serialize open/close/start/stop/ioctl operations */
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	/* Streams */
668*4882a593Smuzhiyun 	int stream_buf_size[IVTV_MAX_STREAMS];          /* stream buffer size */
669*4882a593Smuzhiyun 	struct ivtv_stream streams[IVTV_MAX_STREAMS];	/* stream data */
670*4882a593Smuzhiyun 	atomic_t capturing;		/* count number of active capture streams */
671*4882a593Smuzhiyun 	atomic_t decoding;		/* count number of active decoding streams */
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	/* ALSA interface for PCM capture stream */
674*4882a593Smuzhiyun 	struct snd_ivtv_card *alsa;
675*4882a593Smuzhiyun 	void (*pcm_announce_callback)(struct snd_ivtv_card *card, u8 *pcm_data,
676*4882a593Smuzhiyun 				      size_t num_bytes);
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	/* Used for ivtv-alsa module loading */
679*4882a593Smuzhiyun 	struct work_struct request_module_wk;
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	/* Interrupts & DMA */
682*4882a593Smuzhiyun 	u32 irqmask;                    /* active interrupts */
683*4882a593Smuzhiyun 	u32 irq_rr_idx;                 /* round-robin stream index */
684*4882a593Smuzhiyun 	struct kthread_worker irq_worker;		/* kthread worker for PIO/YUV/VBI actions */
685*4882a593Smuzhiyun 	struct task_struct *irq_worker_task;		/* task for irq_worker */
686*4882a593Smuzhiyun 	struct kthread_work irq_work;	/* kthread work entry */
687*4882a593Smuzhiyun 	spinlock_t dma_reg_lock;        /* lock access to DMA engine registers */
688*4882a593Smuzhiyun 	int cur_dma_stream;		/* index of current stream doing DMA (-1 if none) */
689*4882a593Smuzhiyun 	int cur_pio_stream;		/* index of current stream doing PIO (-1 if none) */
690*4882a593Smuzhiyun 	u32 dma_data_req_offset;        /* store offset in decoder memory of current DMA request */
691*4882a593Smuzhiyun 	u32 dma_data_req_size;          /* store size of current DMA request */
692*4882a593Smuzhiyun 	int dma_retries;                /* current DMA retry attempt */
693*4882a593Smuzhiyun 	struct ivtv_user_dma udma;      /* user based DMA for OSD */
694*4882a593Smuzhiyun 	struct timer_list dma_timer;    /* timer used to catch unfinished DMAs */
695*4882a593Smuzhiyun 	u32 last_vsync_field;           /* last seen vsync field */
696*4882a593Smuzhiyun 	wait_queue_head_t dma_waitq;    /* wake up when the current DMA is finished */
697*4882a593Smuzhiyun 	wait_queue_head_t eos_waitq;    /* wake up when EOS arrives */
698*4882a593Smuzhiyun 	wait_queue_head_t event_waitq;  /* wake up when the next decoder event arrives */
699*4882a593Smuzhiyun 	wait_queue_head_t vsync_waitq;  /* wake up when the next decoder vsync arrives */
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	/* Mailbox */
703*4882a593Smuzhiyun 	struct ivtv_mailbox_data enc_mbox;              /* encoder mailboxes */
704*4882a593Smuzhiyun 	struct ivtv_mailbox_data dec_mbox;              /* decoder mailboxes */
705*4882a593Smuzhiyun 	struct ivtv_api_cache api_cache[256];		/* cached API commands */
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	/* I2C */
709*4882a593Smuzhiyun 	struct i2c_adapter i2c_adap;
710*4882a593Smuzhiyun 	struct i2c_algo_bit_data i2c_algo;
711*4882a593Smuzhiyun 	struct i2c_client i2c_client;
712*4882a593Smuzhiyun 	int i2c_state;                  /* i2c bit state */
713*4882a593Smuzhiyun 	struct mutex i2c_bus_lock;      /* lock i2c bus */
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	struct IR_i2c_init_data ir_i2c_init_data;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	/* Program Index information */
718*4882a593Smuzhiyun 	u32 pgm_info_offset;            /* start of pgm info in encoder memory */
719*4882a593Smuzhiyun 	u32 pgm_info_num;               /* number of elements in the pgm cyclic buffer in encoder memory */
720*4882a593Smuzhiyun 	u32 pgm_info_write_idx;         /* last index written by the card that was transferred to pgm_info[] */
721*4882a593Smuzhiyun 	u32 pgm_info_read_idx;          /* last index in pgm_info read by the application */
722*4882a593Smuzhiyun 	struct v4l2_enc_idx_entry pgm_info[IVTV_MAX_PGM_INDEX]; /* filled from the pgm cyclic buffer on the card */
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	/* Miscellaneous */
726*4882a593Smuzhiyun 	u32 open_id;			/* incremented each time an open occurs, is >= 1 */
727*4882a593Smuzhiyun 	int search_pack_header;         /* 1 if ivtv_copy_buf_to_user() is scanning for a pack header (0xba) */
728*4882a593Smuzhiyun 	int speed;                      /* current playback speed setting */
729*4882a593Smuzhiyun 	u8 speed_mute_audio;            /* 1 if audio should be muted when fast forward */
730*4882a593Smuzhiyun 	u64 mpg_data_received;          /* number of bytes received from the MPEG stream */
731*4882a593Smuzhiyun 	u64 vbi_data_inserted;          /* number of VBI bytes inserted into the MPEG stream */
732*4882a593Smuzhiyun 	u32 last_dec_timing[3];         /* cache last retrieved pts/scr/frame values */
733*4882a593Smuzhiyun 	unsigned long dualwatch_jiffies;/* jiffies value of the previous dualwatch check */
734*4882a593Smuzhiyun 	u32 dualwatch_stereo_mode;      /* current detected dualwatch stereo mode */
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	/* VBI state info */
738*4882a593Smuzhiyun 	struct vbi_info vbi;            /* VBI-specific data */
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun 	/* YUV playback */
742*4882a593Smuzhiyun 	struct yuv_playback_info yuv_info;              /* YUV playback data */
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	/* OSD support */
746*4882a593Smuzhiyun 	unsigned long osd_video_pbase;
747*4882a593Smuzhiyun 	int osd_global_alpha_state;     /* 1 = global alpha is on */
748*4882a593Smuzhiyun 	int osd_local_alpha_state;      /* 1 = local alpha is on */
749*4882a593Smuzhiyun 	int osd_chroma_key_state;       /* 1 = chroma-keying is on */
750*4882a593Smuzhiyun 	u8  osd_global_alpha;           /* current global alpha */
751*4882a593Smuzhiyun 	u32 osd_chroma_key;             /* current chroma key */
752*4882a593Smuzhiyun 	struct v4l2_rect osd_rect;      /* current OSD position and size */
753*4882a593Smuzhiyun 	struct v4l2_rect main_rect;     /* current Main window position and size */
754*4882a593Smuzhiyun 	struct osd_info *osd_info;      /* ivtvfb private OSD info */
755*4882a593Smuzhiyun 	void (*ivtvfb_restore)(struct ivtv *itv); /* Used for a warm start */
756*4882a593Smuzhiyun };
757*4882a593Smuzhiyun 
to_ivtv(struct v4l2_device * v4l2_dev)758*4882a593Smuzhiyun static inline struct ivtv *to_ivtv(struct v4l2_device *v4l2_dev)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun 	return container_of(v4l2_dev, struct ivtv, v4l2_dev);
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun /* ivtv extensions to be loaded */
764*4882a593Smuzhiyun extern int (*ivtv_ext_init)(struct ivtv *);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun /* Globals */
767*4882a593Smuzhiyun extern int ivtv_first_minor;
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun /*==============Prototypes==================*/
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun /* Hardware/IRQ */
772*4882a593Smuzhiyun void ivtv_set_irq_mask(struct ivtv *itv, u32 mask);
773*4882a593Smuzhiyun void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun /* try to set output mode, return current mode. */
776*4882a593Smuzhiyun int ivtv_set_output_mode(struct ivtv *itv, int mode);
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun /* return current output stream based on current mode */
779*4882a593Smuzhiyun struct ivtv_stream *ivtv_get_output_stream(struct ivtv *itv);
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun /* Return non-zero if a signal is pending */
782*4882a593Smuzhiyun int ivtv_msleep_timeout(unsigned int msecs, int intr);
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun /* Wait on queue, returns -EINTR if interrupted */
785*4882a593Smuzhiyun int ivtv_waitq(wait_queue_head_t *waitq);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun /* Read Hauppauge eeprom */
788*4882a593Smuzhiyun struct tveeprom; /* forward reference */
789*4882a593Smuzhiyun void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv);
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun /* First-open initialization: load firmware, init cx25840, etc. */
792*4882a593Smuzhiyun int ivtv_init_on_first_open(struct ivtv *itv);
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun /* Test if the current VBI mode is raw (1) or sliced (0) */
ivtv_raw_vbi(const struct ivtv * itv)795*4882a593Smuzhiyun static inline int ivtv_raw_vbi(const struct ivtv *itv)
796*4882a593Smuzhiyun {
797*4882a593Smuzhiyun 	return itv->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun /* This is a PCI post thing, where if the pci register is not read, then
801*4882a593Smuzhiyun    the write doesn't always take effect right away. By reading back the
802*4882a593Smuzhiyun    register any pending PCI writes will be performed (in order), and so
803*4882a593Smuzhiyun    you can be sure that the writes are guaranteed to be done.
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun    Rarely needed, only in some timing sensitive cases.
806*4882a593Smuzhiyun    Apparently if this is not done some motherboards seem
807*4882a593Smuzhiyun    to kill the firmware and get into the broken state until computer is
808*4882a593Smuzhiyun    rebooted. */
809*4882a593Smuzhiyun #define write_sync(val, reg) \
810*4882a593Smuzhiyun 	do { writel(val, reg); readl(reg); } while (0)
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun #define read_reg(reg) readl(itv->reg_mem + (reg))
813*4882a593Smuzhiyun #define write_reg(val, reg) writel(val, itv->reg_mem + (reg))
814*4882a593Smuzhiyun #define write_reg_sync(val, reg) \
815*4882a593Smuzhiyun 	do { write_reg(val, reg); read_reg(reg); } while (0)
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun #define read_enc(addr) readl(itv->enc_mem + (u32)(addr))
818*4882a593Smuzhiyun #define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr))
819*4882a593Smuzhiyun #define write_enc_sync(val, addr) \
820*4882a593Smuzhiyun 	do { write_enc(val, addr); read_enc(addr); } while (0)
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun #define read_dec(addr) readl(itv->dec_mem + (u32)(addr))
823*4882a593Smuzhiyun #define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr))
824*4882a593Smuzhiyun #define write_dec_sync(val, addr) \
825*4882a593Smuzhiyun 	do { write_dec(val, addr); read_dec(addr); } while (0)
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun /* Call the specified callback for all subdevs matching hw (if 0, then
828*4882a593Smuzhiyun    match them all). Ignore any errors. */
829*4882a593Smuzhiyun #define ivtv_call_hw(itv, hw, o, f, args...)				\
830*4882a593Smuzhiyun 	v4l2_device_mask_call_all(&(itv)->v4l2_dev, hw, o, f, ##args)
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun #define ivtv_call_all(itv, o, f, args...) ivtv_call_hw(itv, 0, o, f , ##args)
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun /* Call the specified callback for all subdevs matching hw (if 0, then
835*4882a593Smuzhiyun    match them all). If the callback returns an error other than 0 or
836*4882a593Smuzhiyun    -ENOIOCTLCMD, then return with that error code. */
837*4882a593Smuzhiyun #define ivtv_call_hw_err(itv, hw, o, f, args...)			\
838*4882a593Smuzhiyun 	v4l2_device_mask_call_until_err(&(itv)->v4l2_dev, hw, o, f, ##args)
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun #define ivtv_call_all_err(itv, o, f, args...) ivtv_call_hw_err(itv, 0, o, f , ##args)
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun #endif
843