1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /*************************************************************************** 3*4882a593Smuzhiyun * Copyright (C) 2006-2010 by Marin Mitov * 4*4882a593Smuzhiyun * mitov@issp.bas.bg * 5*4882a593Smuzhiyun * * 6*4882a593Smuzhiyun * * 7*4882a593Smuzhiyun ***************************************************************************/ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* DT3155 header file */ 10*4882a593Smuzhiyun #ifndef _DT3155_H_ 11*4882a593Smuzhiyun #define _DT3155_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/pci.h> 14*4882a593Smuzhiyun #include <linux/interrupt.h> 15*4882a593Smuzhiyun #include <media/v4l2-device.h> 16*4882a593Smuzhiyun #include <media/v4l2-dev.h> 17*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DT3155_NAME "dt3155" 20*4882a593Smuzhiyun #define DT3155_VER_MAJ 2 21*4882a593Smuzhiyun #define DT3155_VER_MIN 0 22*4882a593Smuzhiyun #define DT3155_VER_EXT 0 23*4882a593Smuzhiyun #define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \ 24*4882a593Smuzhiyun __stringify(DT3155_VER_MIN) "." \ 25*4882a593Smuzhiyun __stringify(DT3155_VER_EXT) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* DT3155 Base Register offsets (memory mapped) */ 28*4882a593Smuzhiyun #define EVEN_DMA_START 0x00 29*4882a593Smuzhiyun #define ODD_DMA_START 0x0C 30*4882a593Smuzhiyun #define EVEN_DMA_STRIDE 0x18 31*4882a593Smuzhiyun #define ODD_DMA_STRIDE 0x24 32*4882a593Smuzhiyun #define EVEN_PIXEL_FMT 0x30 33*4882a593Smuzhiyun #define ODD_PIXEL_FMT 0x34 34*4882a593Smuzhiyun #define FIFO_TRIGGER 0x38 35*4882a593Smuzhiyun #define XFER_MODE 0x3C 36*4882a593Smuzhiyun #define CSR1 0x40 37*4882a593Smuzhiyun #define RETRY_WAIT_CNT 0x44 38*4882a593Smuzhiyun #define INT_CSR 0x48 39*4882a593Smuzhiyun #define EVEN_FLD_MASK 0x4C 40*4882a593Smuzhiyun #define ODD_FLD_MASK 0x50 41*4882a593Smuzhiyun #define MASK_LENGTH 0x54 42*4882a593Smuzhiyun #define FIFO_FLAG_CNT 0x58 43*4882a593Smuzhiyun #define IIC_CLK_DUR 0x5C 44*4882a593Smuzhiyun #define IIC_CSR1 0x60 45*4882a593Smuzhiyun #define IIC_CSR2 0x64 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* DT3155 Internal Registers indexes (i2c/IIC mapped) */ 48*4882a593Smuzhiyun #define CSR2 0x10 49*4882a593Smuzhiyun #define EVEN_CSR 0x11 50*4882a593Smuzhiyun #define ODD_CSR 0x12 51*4882a593Smuzhiyun #define CONFIG 0x13 52*4882a593Smuzhiyun #define DT_ID 0x1F 53*4882a593Smuzhiyun #define X_CLIP_START 0x20 54*4882a593Smuzhiyun #define Y_CLIP_START 0x22 55*4882a593Smuzhiyun #define X_CLIP_END 0x24 56*4882a593Smuzhiyun #define Y_CLIP_END 0x26 57*4882a593Smuzhiyun #define AD_ADDR 0x30 58*4882a593Smuzhiyun #define AD_LUT 0x31 59*4882a593Smuzhiyun #define AD_CMD 0x32 60*4882a593Smuzhiyun #define DIG_OUT 0x40 61*4882a593Smuzhiyun #define PM_LUT_ADDR 0x50 62*4882a593Smuzhiyun #define PM_LUT_DATA 0x51 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* AD command register values */ 65*4882a593Smuzhiyun #define AD_CMD_REG 0x00 66*4882a593Smuzhiyun #define AD_POS_REF 0x01 67*4882a593Smuzhiyun #define AD_NEG_REF 0x02 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* CSR1 bit masks */ 70*4882a593Smuzhiyun #define RANGE_EN 0x00008000 71*4882a593Smuzhiyun #define CRPT_DIS 0x00004000 72*4882a593Smuzhiyun #define ADDR_ERR_ODD 0x00000800 73*4882a593Smuzhiyun #define ADDR_ERR_EVEN 0x00000400 74*4882a593Smuzhiyun #define FLD_CRPT_ODD 0x00000200 75*4882a593Smuzhiyun #define FLD_CRPT_EVEN 0x00000100 76*4882a593Smuzhiyun #define FIFO_EN 0x00000080 77*4882a593Smuzhiyun #define SRST 0x00000040 78*4882a593Smuzhiyun #define FLD_DN_ODD 0x00000020 79*4882a593Smuzhiyun #define FLD_DN_EVEN 0x00000010 80*4882a593Smuzhiyun /* These should not be used. 81*4882a593Smuzhiyun * Use CAP_CONT_ODD/EVEN instead 82*4882a593Smuzhiyun #define CAP_SNGL_ODD 0x00000008 83*4882a593Smuzhiyun #define CAP_SNGL_EVEN 0x00000004 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define CAP_CONT_ODD 0x00000002 86*4882a593Smuzhiyun #define CAP_CONT_EVEN 0x00000001 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* INT_CSR bit masks */ 89*4882a593Smuzhiyun #define FLD_START_EN 0x00000400 90*4882a593Smuzhiyun #define FLD_END_ODD_EN 0x00000200 91*4882a593Smuzhiyun #define FLD_END_EVEN_EN 0x00000100 92*4882a593Smuzhiyun #define FLD_START 0x00000004 93*4882a593Smuzhiyun #define FLD_END_ODD 0x00000002 94*4882a593Smuzhiyun #define FLD_END_EVEN 0x00000001 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* IIC_CSR1 bit masks */ 97*4882a593Smuzhiyun #define DIRECT_ABORT 0x00000200 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* IIC_CSR2 bit masks */ 100*4882a593Smuzhiyun #define NEW_CYCLE 0x01000000 101*4882a593Smuzhiyun #define DIR_RD 0x00010000 102*4882a593Smuzhiyun #define IIC_READ 0x01010000 103*4882a593Smuzhiyun #define IIC_WRITE 0x01000000 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* CSR2 bit masks */ 106*4882a593Smuzhiyun #define DISP_PASS 0x40 107*4882a593Smuzhiyun #define BUSY_ODD 0x20 108*4882a593Smuzhiyun #define BUSY_EVEN 0x10 109*4882a593Smuzhiyun #define SYNC_PRESENT 0x08 110*4882a593Smuzhiyun #define VT_50HZ 0x04 111*4882a593Smuzhiyun #define SYNC_SNTL 0x02 112*4882a593Smuzhiyun #define CHROM_FILT 0x01 113*4882a593Smuzhiyun #define VT_60HZ 0x00 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* CSR_EVEN/ODD bit masks */ 116*4882a593Smuzhiyun #define CSR_ERROR 0x04 117*4882a593Smuzhiyun #define CSR_SNGL 0x02 118*4882a593Smuzhiyun #define CSR_DONE 0x01 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* CONFIG bit masks */ 121*4882a593Smuzhiyun #define PM_LUT_PGM 0x80 122*4882a593Smuzhiyun #define PM_LUT_SEL 0x40 123*4882a593Smuzhiyun #define CLIP_EN 0x20 124*4882a593Smuzhiyun #define HSCALE_EN 0x10 125*4882a593Smuzhiyun #define EXT_TRIG_UP 0x0C 126*4882a593Smuzhiyun #define EXT_TRIG_DOWN 0x04 127*4882a593Smuzhiyun #define ACQ_MODE_NEXT 0x02 128*4882a593Smuzhiyun #define ACQ_MODE_ODD 0x01 129*4882a593Smuzhiyun #define ACQ_MODE_EVEN 0x00 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* AD_CMD bit masks */ 132*4882a593Smuzhiyun #define VIDEO_CNL_1 0x00 133*4882a593Smuzhiyun #define VIDEO_CNL_2 0x40 134*4882a593Smuzhiyun #define VIDEO_CNL_3 0x80 135*4882a593Smuzhiyun #define VIDEO_CNL_4 0xC0 136*4882a593Smuzhiyun #define SYNC_CNL_1 0x00 137*4882a593Smuzhiyun #define SYNC_CNL_2 0x10 138*4882a593Smuzhiyun #define SYNC_CNL_3 0x20 139*4882a593Smuzhiyun #define SYNC_CNL_4 0x30 140*4882a593Smuzhiyun #define SYNC_LVL_1 0x00 141*4882a593Smuzhiyun #define SYNC_LVL_2 0x04 142*4882a593Smuzhiyun #define SYNC_LVL_3 0x08 143*4882a593Smuzhiyun #define SYNC_LVL_4 0x0C 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* DT3155 identificator */ 146*4882a593Smuzhiyun #define DT3155_ID 0x20 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* per board private data structure */ 149*4882a593Smuzhiyun /** 150*4882a593Smuzhiyun * struct dt3155_priv - private data structure 151*4882a593Smuzhiyun * 152*4882a593Smuzhiyun * @v4l2_dev: v4l2_device structure 153*4882a593Smuzhiyun * @vdev: video_device structure 154*4882a593Smuzhiyun * @pdev: pointer to pci_dev structure 155*4882a593Smuzhiyun * @vidq: vb2_queue structure 156*4882a593Smuzhiyun * @curr_buf: pointer to curren buffer 157*4882a593Smuzhiyun * @mux: mutex to protect the instance 158*4882a593Smuzhiyun * @dmaq: queue for dma buffers 159*4882a593Smuzhiyun * @lock: spinlock for dma queue 160*4882a593Smuzhiyun * @std: input standard 161*4882a593Smuzhiyun * @width: frame width 162*4882a593Smuzhiyun * @height: frame height 163*4882a593Smuzhiyun * @input: current input 164*4882a593Smuzhiyun * @sequence: frame counter 165*4882a593Smuzhiyun * @stats: statistics structure 166*4882a593Smuzhiyun * @regs: local copy of mmio base register 167*4882a593Smuzhiyun * @csr2: local copy of csr2 register 168*4882a593Smuzhiyun * @config: local copy of config register 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun struct dt3155_priv { 171*4882a593Smuzhiyun struct v4l2_device v4l2_dev; 172*4882a593Smuzhiyun struct video_device vdev; 173*4882a593Smuzhiyun struct pci_dev *pdev; 174*4882a593Smuzhiyun struct vb2_queue vidq; 175*4882a593Smuzhiyun struct vb2_v4l2_buffer *curr_buf; 176*4882a593Smuzhiyun struct mutex mux; 177*4882a593Smuzhiyun struct list_head dmaq; 178*4882a593Smuzhiyun spinlock_t lock; 179*4882a593Smuzhiyun v4l2_std_id std; 180*4882a593Smuzhiyun unsigned width, height; 181*4882a593Smuzhiyun unsigned input; 182*4882a593Smuzhiyun unsigned int sequence; 183*4882a593Smuzhiyun void __iomem *regs; 184*4882a593Smuzhiyun u8 csr2, config; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #endif /* _DT3155_H_ */ 188