xref: /OK3568_Linux_fs/kernel/drivers/media/pci/dm1105/dm1105.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/dma-mapping.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <media/rc-core.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <media/demux.h>
20*4882a593Smuzhiyun #include <media/dmxdev.h>
21*4882a593Smuzhiyun #include <media/dvb_demux.h>
22*4882a593Smuzhiyun #include <media/dvb_frontend.h>
23*4882a593Smuzhiyun #include <media/dvb_net.h>
24*4882a593Smuzhiyun #include <media/dvbdev.h>
25*4882a593Smuzhiyun #include "dvb-pll.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "stv0299.h"
28*4882a593Smuzhiyun #include "stv0288.h"
29*4882a593Smuzhiyun #include "stb6000.h"
30*4882a593Smuzhiyun #include "si21xx.h"
31*4882a593Smuzhiyun #include "cx24116.h"
32*4882a593Smuzhiyun #include "z0194a.h"
33*4882a593Smuzhiyun #include "ts2020.h"
34*4882a593Smuzhiyun #include "ds3000.h"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MODULE_NAME "dm1105"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define UNSET (-1U)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define DM1105_BOARD_NOAUTO			UNSET
41*4882a593Smuzhiyun #define DM1105_BOARD_UNKNOWN			0
42*4882a593Smuzhiyun #define DM1105_BOARD_DVBWORLD_2002		1
43*4882a593Smuzhiyun #define DM1105_BOARD_DVBWORLD_2004		2
44*4882a593Smuzhiyun #define DM1105_BOARD_AXESS_DM05			3
45*4882a593Smuzhiyun #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO	4
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* ----------------------------------------------- */
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun  * PCI ID's
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun #ifndef PCI_VENDOR_ID_TRIGEM
52*4882a593Smuzhiyun #define PCI_VENDOR_ID_TRIGEM	0x109f
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun #ifndef PCI_VENDOR_ID_AXESS
55*4882a593Smuzhiyun #define PCI_VENDOR_ID_AXESS	0x195d
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_DM1105
58*4882a593Smuzhiyun #define PCI_DEVICE_ID_DM1105	0x036f
59*4882a593Smuzhiyun #endif
60*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_DW2002
61*4882a593Smuzhiyun #define PCI_DEVICE_ID_DW2002	0x2002
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_DW2004
64*4882a593Smuzhiyun #define PCI_DEVICE_ID_DW2004	0x2004
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun #ifndef PCI_DEVICE_ID_DM05
67*4882a593Smuzhiyun #define PCI_DEVICE_ID_DM05	0x1105
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun /* ----------------------------------------------- */
70*4882a593Smuzhiyun /* sdmc dm1105 registers */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* TS Control */
73*4882a593Smuzhiyun #define DM1105_TSCTR				0x00
74*4882a593Smuzhiyun #define DM1105_DTALENTH				0x04
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* GPIO Interface */
77*4882a593Smuzhiyun #define DM1105_GPIOVAL				0x08
78*4882a593Smuzhiyun #define DM1105_GPIOCTR				0x0c
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* PID serial number */
81*4882a593Smuzhiyun #define DM1105_PIDN				0x10
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* Odd-even secret key select */
84*4882a593Smuzhiyun #define DM1105_CWSEL				0x14
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /* Host Command Interface */
87*4882a593Smuzhiyun #define DM1105_HOST_CTR				0x18
88*4882a593Smuzhiyun #define DM1105_HOST_AD				0x1c
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* PCI Interface */
91*4882a593Smuzhiyun #define DM1105_CR				0x30
92*4882a593Smuzhiyun #define DM1105_RST				0x34
93*4882a593Smuzhiyun #define DM1105_STADR				0x38
94*4882a593Smuzhiyun #define DM1105_RLEN				0x3c
95*4882a593Smuzhiyun #define DM1105_WRP				0x40
96*4882a593Smuzhiyun #define DM1105_INTCNT				0x44
97*4882a593Smuzhiyun #define DM1105_INTMAK				0x48
98*4882a593Smuzhiyun #define DM1105_INTSTS				0x4c
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* CW Value */
101*4882a593Smuzhiyun #define DM1105_ODD				0x50
102*4882a593Smuzhiyun #define DM1105_EVEN				0x58
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* PID Value */
105*4882a593Smuzhiyun #define DM1105_PID				0x60
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* IR Control */
108*4882a593Smuzhiyun #define DM1105_IRCTR				0x64
109*4882a593Smuzhiyun #define DM1105_IRMODE				0x68
110*4882a593Smuzhiyun #define DM1105_SYSTEMCODE			0x6c
111*4882a593Smuzhiyun #define DM1105_IRCODE				0x70
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* Unknown Values */
114*4882a593Smuzhiyun #define DM1105_ENCRYPT				0x74
115*4882a593Smuzhiyun #define DM1105_VER				0x7c
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* I2C Interface */
118*4882a593Smuzhiyun #define DM1105_I2CCTR				0x80
119*4882a593Smuzhiyun #define DM1105_I2CSTS				0x81
120*4882a593Smuzhiyun #define DM1105_I2CDAT				0x82
121*4882a593Smuzhiyun #define DM1105_I2C_RA				0x83
122*4882a593Smuzhiyun /* ----------------------------------------------- */
123*4882a593Smuzhiyun /* Interrupt Mask Bits */
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #define INTMAK_TSIRQM				0x01
126*4882a593Smuzhiyun #define INTMAK_HIRQM				0x04
127*4882a593Smuzhiyun #define INTMAK_IRM				0x08
128*4882a593Smuzhiyun #define INTMAK_ALLMASK				(INTMAK_TSIRQM | \
129*4882a593Smuzhiyun 						INTMAK_HIRQM | \
130*4882a593Smuzhiyun 						INTMAK_IRM)
131*4882a593Smuzhiyun #define INTMAK_NONEMASK				0x00
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun /* Interrupt Status Bits */
134*4882a593Smuzhiyun #define INTSTS_TSIRQ				0x01
135*4882a593Smuzhiyun #define INTSTS_HIRQ				0x04
136*4882a593Smuzhiyun #define INTSTS_IR				0x08
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /* IR Control Bits */
139*4882a593Smuzhiyun #define DM1105_IR_EN				0x01
140*4882a593Smuzhiyun #define DM1105_SYS_CHK				0x02
141*4882a593Smuzhiyun #define DM1105_REP_FLG				0x08
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun /* EEPROM addr */
144*4882a593Smuzhiyun #define IIC_24C01_addr				0xa0
145*4882a593Smuzhiyun /* Max board count */
146*4882a593Smuzhiyun #define DM1105_MAX				0x04
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define DRIVER_NAME				"dm1105"
149*4882a593Smuzhiyun #define DM1105_I2C_GPIO_NAME			"dm1105-gpio"
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun #define DM1105_DMA_PACKETS			47
152*4882a593Smuzhiyun #define DM1105_DMA_PACKET_LENGTH		(128*4)
153*4882a593Smuzhiyun #define DM1105_DMA_BYTES			(128 * 4 * DM1105_DMA_PACKETS)
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun /*  */
156*4882a593Smuzhiyun #define GPIO08					(1 << 8)
157*4882a593Smuzhiyun #define GPIO13					(1 << 13)
158*4882a593Smuzhiyun #define GPIO14					(1 << 14)
159*4882a593Smuzhiyun #define GPIO15					(1 << 15)
160*4882a593Smuzhiyun #define GPIO16					(1 << 16)
161*4882a593Smuzhiyun #define GPIO17					(1 << 17)
162*4882a593Smuzhiyun #define GPIO_ALL				0x03ffff
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /* GPIO's for LNB power control */
165*4882a593Smuzhiyun #define DM1105_LNB_MASK				(GPIO_ALL & ~(GPIO14 | GPIO13))
166*4882a593Smuzhiyun #define DM1105_LNB_OFF				GPIO17
167*4882a593Smuzhiyun #define DM1105_LNB_13V				(GPIO16 | GPIO08)
168*4882a593Smuzhiyun #define DM1105_LNB_18V				GPIO08
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* GPIO's for LNB power control for Axess DM05 */
171*4882a593Smuzhiyun #define DM05_LNB_MASK				(GPIO_ALL & ~(GPIO14 | GPIO13))
172*4882a593Smuzhiyun #define DM05_LNB_OFF				GPIO17/* actually 13v */
173*4882a593Smuzhiyun #define DM05_LNB_13V				GPIO17
174*4882a593Smuzhiyun #define DM05_LNB_18V				(GPIO17 | GPIO16)
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /* GPIO's for LNB power control for unbranded with I2C on GPIO */
177*4882a593Smuzhiyun #define UNBR_LNB_MASK				(GPIO17 | GPIO16)
178*4882a593Smuzhiyun #define UNBR_LNB_OFF				0
179*4882a593Smuzhiyun #define UNBR_LNB_13V				GPIO17
180*4882a593Smuzhiyun #define UNBR_LNB_18V				(GPIO17 | GPIO16)
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static unsigned int card[]  = {[0 ... 3] = UNSET };
183*4882a593Smuzhiyun module_param_array(card,  int, NULL, 0444);
184*4882a593Smuzhiyun MODULE_PARM_DESC(card, "card type");
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun static int ir_debug;
187*4882a593Smuzhiyun module_param(ir_debug, int, 0644);
188*4882a593Smuzhiyun MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static unsigned int dm1105_devcount;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun struct dm1105_board {
195*4882a593Smuzhiyun 	char	*name;
196*4882a593Smuzhiyun 	struct	{
197*4882a593Smuzhiyun 		u32	mask, off, v13, v18;
198*4882a593Smuzhiyun 	} lnb;
199*4882a593Smuzhiyun 	u32	gpio_scl, gpio_sda;
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun struct dm1105_subid {
203*4882a593Smuzhiyun 	u16     subvendor;
204*4882a593Smuzhiyun 	u16     subdevice;
205*4882a593Smuzhiyun 	u32     card;
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct dm1105_board dm1105_boards[] = {
209*4882a593Smuzhiyun 	[DM1105_BOARD_UNKNOWN] = {
210*4882a593Smuzhiyun 		.name		= "UNKNOWN/GENERIC",
211*4882a593Smuzhiyun 		.lnb = {
212*4882a593Smuzhiyun 			.mask = DM1105_LNB_MASK,
213*4882a593Smuzhiyun 			.off = DM1105_LNB_OFF,
214*4882a593Smuzhiyun 			.v13 = DM1105_LNB_13V,
215*4882a593Smuzhiyun 			.v18 = DM1105_LNB_18V,
216*4882a593Smuzhiyun 		},
217*4882a593Smuzhiyun 	},
218*4882a593Smuzhiyun 	[DM1105_BOARD_DVBWORLD_2002] = {
219*4882a593Smuzhiyun 		.name		= "DVBWorld PCI 2002",
220*4882a593Smuzhiyun 		.lnb = {
221*4882a593Smuzhiyun 			.mask = DM1105_LNB_MASK,
222*4882a593Smuzhiyun 			.off = DM1105_LNB_OFF,
223*4882a593Smuzhiyun 			.v13 = DM1105_LNB_13V,
224*4882a593Smuzhiyun 			.v18 = DM1105_LNB_18V,
225*4882a593Smuzhiyun 		},
226*4882a593Smuzhiyun 	},
227*4882a593Smuzhiyun 	[DM1105_BOARD_DVBWORLD_2004] = {
228*4882a593Smuzhiyun 		.name		= "DVBWorld PCI 2004",
229*4882a593Smuzhiyun 		.lnb = {
230*4882a593Smuzhiyun 			.mask = DM1105_LNB_MASK,
231*4882a593Smuzhiyun 			.off = DM1105_LNB_OFF,
232*4882a593Smuzhiyun 			.v13 = DM1105_LNB_13V,
233*4882a593Smuzhiyun 			.v18 = DM1105_LNB_18V,
234*4882a593Smuzhiyun 		},
235*4882a593Smuzhiyun 	},
236*4882a593Smuzhiyun 	[DM1105_BOARD_AXESS_DM05] = {
237*4882a593Smuzhiyun 		.name		= "Axess/EasyTv DM05",
238*4882a593Smuzhiyun 		.lnb = {
239*4882a593Smuzhiyun 			.mask = DM05_LNB_MASK,
240*4882a593Smuzhiyun 			.off = DM05_LNB_OFF,
241*4882a593Smuzhiyun 			.v13 = DM05_LNB_13V,
242*4882a593Smuzhiyun 			.v18 = DM05_LNB_18V,
243*4882a593Smuzhiyun 		},
244*4882a593Smuzhiyun 	},
245*4882a593Smuzhiyun 	[DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = {
246*4882a593Smuzhiyun 		.name		= "Unbranded DM1105 with i2c on GPIOs",
247*4882a593Smuzhiyun 		.lnb = {
248*4882a593Smuzhiyun 			.mask = UNBR_LNB_MASK,
249*4882a593Smuzhiyun 			.off = UNBR_LNB_OFF,
250*4882a593Smuzhiyun 			.v13 = UNBR_LNB_13V,
251*4882a593Smuzhiyun 			.v18 = UNBR_LNB_18V,
252*4882a593Smuzhiyun 		},
253*4882a593Smuzhiyun 		.gpio_scl	= GPIO14,
254*4882a593Smuzhiyun 		.gpio_sda	= GPIO13,
255*4882a593Smuzhiyun 	},
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun static const struct dm1105_subid dm1105_subids[] = {
259*4882a593Smuzhiyun 	{
260*4882a593Smuzhiyun 		.subvendor = 0x0000,
261*4882a593Smuzhiyun 		.subdevice = 0x2002,
262*4882a593Smuzhiyun 		.card      = DM1105_BOARD_DVBWORLD_2002,
263*4882a593Smuzhiyun 	}, {
264*4882a593Smuzhiyun 		.subvendor = 0x0001,
265*4882a593Smuzhiyun 		.subdevice = 0x2002,
266*4882a593Smuzhiyun 		.card      = DM1105_BOARD_DVBWORLD_2002,
267*4882a593Smuzhiyun 	}, {
268*4882a593Smuzhiyun 		.subvendor = 0x0000,
269*4882a593Smuzhiyun 		.subdevice = 0x2004,
270*4882a593Smuzhiyun 		.card      = DM1105_BOARD_DVBWORLD_2004,
271*4882a593Smuzhiyun 	}, {
272*4882a593Smuzhiyun 		.subvendor = 0x0001,
273*4882a593Smuzhiyun 		.subdevice = 0x2004,
274*4882a593Smuzhiyun 		.card      = DM1105_BOARD_DVBWORLD_2004,
275*4882a593Smuzhiyun 	}, {
276*4882a593Smuzhiyun 		.subvendor = 0x195d,
277*4882a593Smuzhiyun 		.subdevice = 0x1105,
278*4882a593Smuzhiyun 		.card      = DM1105_BOARD_AXESS_DM05,
279*4882a593Smuzhiyun 	},
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun 
dm1105_card_list(struct pci_dev * pci)282*4882a593Smuzhiyun static void dm1105_card_list(struct pci_dev *pci)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	int i;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	if (0 == pci->subsystem_vendor &&
287*4882a593Smuzhiyun 			0 == pci->subsystem_device) {
288*4882a593Smuzhiyun 		printk(KERN_ERR
289*4882a593Smuzhiyun 			"dm1105: Your board has no valid PCI Subsystem ID\n"
290*4882a593Smuzhiyun 			"dm1105: and thus can't be autodetected\n"
291*4882a593Smuzhiyun 			"dm1105: Please pass card=<n> insmod option to\n"
292*4882a593Smuzhiyun 			"dm1105: workaround that.  Redirect complaints to\n"
293*4882a593Smuzhiyun 			"dm1105: the vendor of the TV card.  Best regards,\n"
294*4882a593Smuzhiyun 			"dm1105: -- tux\n");
295*4882a593Smuzhiyun 	} else {
296*4882a593Smuzhiyun 		printk(KERN_ERR
297*4882a593Smuzhiyun 			"dm1105: Your board isn't known (yet) to the driver.\n"
298*4882a593Smuzhiyun 			"dm1105: You can try to pick one of the existing\n"
299*4882a593Smuzhiyun 			"dm1105: card configs via card=<n> insmod option.\n"
300*4882a593Smuzhiyun 			"dm1105: Updating to the latest version might help\n"
301*4882a593Smuzhiyun 			"dm1105: as well.\n");
302*4882a593Smuzhiyun 	}
303*4882a593Smuzhiyun 	printk(KERN_ERR "Here is a list of valid choices for the card=<n> insmod option:\n");
304*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)
305*4882a593Smuzhiyun 		printk(KERN_ERR "dm1105:    card=%d -> %s\n",
306*4882a593Smuzhiyun 				i, dm1105_boards[i].name);
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun /* infrared remote control */
310*4882a593Smuzhiyun struct infrared {
311*4882a593Smuzhiyun 	struct rc_dev		*dev;
312*4882a593Smuzhiyun 	char			input_phys[32];
313*4882a593Smuzhiyun 	struct work_struct	work;
314*4882a593Smuzhiyun 	u32			ir_command;
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun struct dm1105_dev {
318*4882a593Smuzhiyun 	/* pci */
319*4882a593Smuzhiyun 	struct pci_dev *pdev;
320*4882a593Smuzhiyun 	u8 __iomem *io_mem;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	/* ir */
323*4882a593Smuzhiyun 	struct infrared ir;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	/* dvb */
326*4882a593Smuzhiyun 	struct dmx_frontend hw_frontend;
327*4882a593Smuzhiyun 	struct dmx_frontend mem_frontend;
328*4882a593Smuzhiyun 	struct dmxdev dmxdev;
329*4882a593Smuzhiyun 	struct dvb_adapter dvb_adapter;
330*4882a593Smuzhiyun 	struct dvb_demux demux;
331*4882a593Smuzhiyun 	struct dvb_frontend *fe;
332*4882a593Smuzhiyun 	struct dvb_net dvbnet;
333*4882a593Smuzhiyun 	unsigned int full_ts_users;
334*4882a593Smuzhiyun 	unsigned int boardnr;
335*4882a593Smuzhiyun 	int nr;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	/* i2c */
338*4882a593Smuzhiyun 	struct i2c_adapter i2c_adap;
339*4882a593Smuzhiyun 	struct i2c_adapter i2c_bb_adap;
340*4882a593Smuzhiyun 	struct i2c_algo_bit_data i2c_bit;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	/* irq */
343*4882a593Smuzhiyun 	struct work_struct work;
344*4882a593Smuzhiyun 	struct workqueue_struct *wq;
345*4882a593Smuzhiyun 	char wqn[16];
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	/* dma */
348*4882a593Smuzhiyun 	dma_addr_t dma_addr;
349*4882a593Smuzhiyun 	unsigned char *ts_buf;
350*4882a593Smuzhiyun 	u32 wrp;
351*4882a593Smuzhiyun 	u32 nextwrp;
352*4882a593Smuzhiyun 	u32 buffer_size;
353*4882a593Smuzhiyun 	unsigned int	PacketErrorCount;
354*4882a593Smuzhiyun 	unsigned int dmarst;
355*4882a593Smuzhiyun 	spinlock_t lock;
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun #define dm_io_mem(reg)	((unsigned long)(&dev->io_mem[reg]))
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun #define dm_readb(reg)		inb(dm_io_mem(reg))
361*4882a593Smuzhiyun #define dm_writeb(reg, value)	outb((value), (dm_io_mem(reg)))
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun #define dm_readw(reg)		inw(dm_io_mem(reg))
364*4882a593Smuzhiyun #define dm_writew(reg, value)	outw((value), (dm_io_mem(reg)))
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun #define dm_readl(reg)		inl(dm_io_mem(reg))
367*4882a593Smuzhiyun #define dm_writel(reg, value)	outl((value), (dm_io_mem(reg)))
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun #define dm_andorl(reg, mask, value) \
370*4882a593Smuzhiyun 	outl((inl(dm_io_mem(reg)) & ~(mask)) |\
371*4882a593Smuzhiyun 		((value) & (mask)), (dm_io_mem(reg)))
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun #define dm_setl(reg, bit)	dm_andorl((reg), (bit), (bit))
374*4882a593Smuzhiyun #define dm_clearl(reg, bit)	dm_andorl((reg), (bit), 0)
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines,
377*4882a593Smuzhiyun  so we can use only 3 GPIO's from GPIO15 to GPIO17.
378*4882a593Smuzhiyun  Here I don't check whether HOST is enebled as it is not implemented yet.
379*4882a593Smuzhiyun  */
dm1105_gpio_set(struct dm1105_dev * dev,u32 mask)380*4882a593Smuzhiyun static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	if (mask & 0xfffc0000)
383*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	if (mask & 0x0003ffff)
386*4882a593Smuzhiyun 		dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
dm1105_gpio_clear(struct dm1105_dev * dev,u32 mask)390*4882a593Smuzhiyun static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun 	if (mask & 0xfffc0000)
393*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	if (mask & 0x0003ffff)
396*4882a593Smuzhiyun 		dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun 
dm1105_gpio_andor(struct dm1105_dev * dev,u32 mask,u32 val)400*4882a593Smuzhiyun static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun 	if (mask & 0xfffc0000)
403*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	if (mask & 0x0003ffff)
406*4882a593Smuzhiyun 		dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
dm1105_gpio_get(struct dm1105_dev * dev,u32 mask)410*4882a593Smuzhiyun static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun 	if (mask & 0xfffc0000)
413*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	if (mask & 0x0003ffff)
416*4882a593Smuzhiyun 		return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	return 0;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun 
dm1105_gpio_enable(struct dm1105_dev * dev,u32 mask,int asoutput)421*4882a593Smuzhiyun static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun 	if (mask & 0xfffc0000)
424*4882a593Smuzhiyun 		printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	if ((mask & 0x0003ffff) && asoutput)
427*4882a593Smuzhiyun 		dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);
428*4882a593Smuzhiyun 	else if ((mask & 0x0003ffff) && !asoutput)
429*4882a593Smuzhiyun 		dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun 
dm1105_setline(struct dm1105_dev * dev,u32 line,int state)433*4882a593Smuzhiyun static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	if (state)
436*4882a593Smuzhiyun 		dm1105_gpio_enable(dev, line, 0);
437*4882a593Smuzhiyun 	else {
438*4882a593Smuzhiyun 		dm1105_gpio_enable(dev, line, 1);
439*4882a593Smuzhiyun 		dm1105_gpio_clear(dev, line);
440*4882a593Smuzhiyun 	}
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
dm1105_setsda(void * data,int state)443*4882a593Smuzhiyun static void dm1105_setsda(void *data, int state)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	struct dm1105_dev *dev = data;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun 
dm1105_setscl(void * data,int state)450*4882a593Smuzhiyun static void dm1105_setscl(void *data, int state)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct dm1105_dev *dev = data;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun 
dm1105_getsda(void * data)457*4882a593Smuzhiyun static int dm1105_getsda(void *data)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun 	struct dm1105_dev *dev = data;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda)
462*4882a593Smuzhiyun 									? 1 : 0;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
dm1105_getscl(void * data)465*4882a593Smuzhiyun static int dm1105_getscl(void *data)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	struct dm1105_dev *dev = data;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl)
470*4882a593Smuzhiyun 									? 1 : 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
dm1105_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)473*4882a593Smuzhiyun static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
474*4882a593Smuzhiyun 			    struct i2c_msg *msgs, int num)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun 	struct dm1105_dev *dev ;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	int addr, rc, i, j, k, len, byte, data;
479*4882a593Smuzhiyun 	u8 status;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	dev = i2c_adap->algo_data;
482*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
483*4882a593Smuzhiyun 		dm_writeb(DM1105_I2CCTR, 0x00);
484*4882a593Smuzhiyun 		if (msgs[i].flags & I2C_M_RD) {
485*4882a593Smuzhiyun 			/* read bytes */
486*4882a593Smuzhiyun 			addr  = msgs[i].addr << 1;
487*4882a593Smuzhiyun 			addr |= 1;
488*4882a593Smuzhiyun 			dm_writeb(DM1105_I2CDAT, addr);
489*4882a593Smuzhiyun 			for (byte = 0; byte < msgs[i].len; byte++)
490*4882a593Smuzhiyun 				dm_writeb(DM1105_I2CDAT + byte + 1, 0);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
493*4882a593Smuzhiyun 			for (j = 0; j < 55; j++) {
494*4882a593Smuzhiyun 				mdelay(10);
495*4882a593Smuzhiyun 				status = dm_readb(DM1105_I2CSTS);
496*4882a593Smuzhiyun 				if ((status & 0xc0) == 0x40)
497*4882a593Smuzhiyun 					break;
498*4882a593Smuzhiyun 			}
499*4882a593Smuzhiyun 			if (j >= 55)
500*4882a593Smuzhiyun 				return -1;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 			for (byte = 0; byte < msgs[i].len; byte++) {
503*4882a593Smuzhiyun 				rc = dm_readb(DM1105_I2CDAT + byte + 1);
504*4882a593Smuzhiyun 				if (rc < 0)
505*4882a593Smuzhiyun 					goto err;
506*4882a593Smuzhiyun 				msgs[i].buf[byte] = rc;
507*4882a593Smuzhiyun 			}
508*4882a593Smuzhiyun 		} else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
509*4882a593Smuzhiyun 			/* prepared for cx24116 firmware */
510*4882a593Smuzhiyun 			/* Write in small blocks */
511*4882a593Smuzhiyun 			len = msgs[i].len - 1;
512*4882a593Smuzhiyun 			k = 1;
513*4882a593Smuzhiyun 			do {
514*4882a593Smuzhiyun 				dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
515*4882a593Smuzhiyun 				dm_writeb(DM1105_I2CDAT + 1, 0xf7);
516*4882a593Smuzhiyun 				for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
517*4882a593Smuzhiyun 					data = msgs[i].buf[k + byte];
518*4882a593Smuzhiyun 					dm_writeb(DM1105_I2CDAT + byte + 2, data);
519*4882a593Smuzhiyun 				}
520*4882a593Smuzhiyun 				dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
521*4882a593Smuzhiyun 				for (j = 0; j < 25; j++) {
522*4882a593Smuzhiyun 					mdelay(10);
523*4882a593Smuzhiyun 					status = dm_readb(DM1105_I2CSTS);
524*4882a593Smuzhiyun 					if ((status & 0xc0) == 0x40)
525*4882a593Smuzhiyun 						break;
526*4882a593Smuzhiyun 				}
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 				if (j >= 25)
529*4882a593Smuzhiyun 					return -1;
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 				k += 48;
532*4882a593Smuzhiyun 				len -= 48;
533*4882a593Smuzhiyun 			} while (len > 0);
534*4882a593Smuzhiyun 		} else {
535*4882a593Smuzhiyun 			/* write bytes */
536*4882a593Smuzhiyun 			dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
537*4882a593Smuzhiyun 			for (byte = 0; byte < msgs[i].len; byte++) {
538*4882a593Smuzhiyun 				data = msgs[i].buf[byte];
539*4882a593Smuzhiyun 				dm_writeb(DM1105_I2CDAT + byte + 1, data);
540*4882a593Smuzhiyun 			}
541*4882a593Smuzhiyun 			dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
542*4882a593Smuzhiyun 			for (j = 0; j < 25; j++) {
543*4882a593Smuzhiyun 				mdelay(10);
544*4882a593Smuzhiyun 				status = dm_readb(DM1105_I2CSTS);
545*4882a593Smuzhiyun 				if ((status & 0xc0) == 0x40)
546*4882a593Smuzhiyun 					break;
547*4882a593Smuzhiyun 			}
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 			if (j >= 25)
550*4882a593Smuzhiyun 				return -1;
551*4882a593Smuzhiyun 		}
552*4882a593Smuzhiyun 	}
553*4882a593Smuzhiyun 	return num;
554*4882a593Smuzhiyun  err:
555*4882a593Smuzhiyun 	return rc;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun 
functionality(struct i2c_adapter * adap)558*4882a593Smuzhiyun static u32 functionality(struct i2c_adapter *adap)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun 	return I2C_FUNC_I2C;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun static const struct i2c_algorithm dm1105_algo = {
564*4882a593Smuzhiyun 	.master_xfer   = dm1105_i2c_xfer,
565*4882a593Smuzhiyun 	.functionality = functionality,
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun 
feed_to_dm1105_dev(struct dvb_demux_feed * feed)568*4882a593Smuzhiyun static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun 	return container_of(feed->demux, struct dm1105_dev, demux);
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun 
frontend_to_dm1105_dev(struct dvb_frontend * fe)573*4882a593Smuzhiyun static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun 	return container_of(fe->dvb, struct dm1105_dev, dvb_adapter);
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
dm1105_set_voltage(struct dvb_frontend * fe,enum fe_sec_voltage voltage)578*4882a593Smuzhiyun static int dm1105_set_voltage(struct dvb_frontend *fe,
579*4882a593Smuzhiyun 			      enum fe_sec_voltage voltage)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun 	struct dm1105_dev *dev = frontend_to_dm1105_dev(fe);
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1);
584*4882a593Smuzhiyun 	if (voltage == SEC_VOLTAGE_18)
585*4882a593Smuzhiyun 		dm1105_gpio_andor(dev,
586*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.mask,
587*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.v18);
588*4882a593Smuzhiyun 	else if (voltage == SEC_VOLTAGE_13)
589*4882a593Smuzhiyun 		dm1105_gpio_andor(dev,
590*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.mask,
591*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.v13);
592*4882a593Smuzhiyun 	else
593*4882a593Smuzhiyun 		dm1105_gpio_andor(dev,
594*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.mask,
595*4882a593Smuzhiyun 				dm1105_boards[dev->boardnr].lnb.off);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	return 0;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun 
dm1105_set_dma_addr(struct dm1105_dev * dev)600*4882a593Smuzhiyun static void dm1105_set_dma_addr(struct dm1105_dev *dev)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun 	dm_writel(DM1105_STADR, (__force u32)cpu_to_le32(dev->dma_addr));
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun 
dm1105_dma_map(struct dm1105_dev * dev)605*4882a593Smuzhiyun static int dm1105_dma_map(struct dm1105_dev *dev)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun 	dev->ts_buf = pci_alloc_consistent(dev->pdev,
608*4882a593Smuzhiyun 					6 * DM1105_DMA_BYTES,
609*4882a593Smuzhiyun 					&dev->dma_addr);
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	return !dev->ts_buf;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun 
dm1105_dma_unmap(struct dm1105_dev * dev)614*4882a593Smuzhiyun static void dm1105_dma_unmap(struct dm1105_dev *dev)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun 	pci_free_consistent(dev->pdev,
617*4882a593Smuzhiyun 			6 * DM1105_DMA_BYTES,
618*4882a593Smuzhiyun 			dev->ts_buf,
619*4882a593Smuzhiyun 			dev->dma_addr);
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun 
dm1105_enable_irqs(struct dm1105_dev * dev)622*4882a593Smuzhiyun static void dm1105_enable_irqs(struct dm1105_dev *dev)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun 	dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
625*4882a593Smuzhiyun 	dm_writeb(DM1105_CR, 1);
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun 
dm1105_disable_irqs(struct dm1105_dev * dev)628*4882a593Smuzhiyun static void dm1105_disable_irqs(struct dm1105_dev *dev)
629*4882a593Smuzhiyun {
630*4882a593Smuzhiyun 	dm_writeb(DM1105_INTMAK, INTMAK_IRM);
631*4882a593Smuzhiyun 	dm_writeb(DM1105_CR, 0);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
dm1105_start_feed(struct dvb_demux_feed * f)634*4882a593Smuzhiyun static int dm1105_start_feed(struct dvb_demux_feed *f)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun 	struct dm1105_dev *dev = feed_to_dm1105_dev(f);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	if (dev->full_ts_users++ == 0)
639*4882a593Smuzhiyun 		dm1105_enable_irqs(dev);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	return 0;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
dm1105_stop_feed(struct dvb_demux_feed * f)644*4882a593Smuzhiyun static int dm1105_stop_feed(struct dvb_demux_feed *f)
645*4882a593Smuzhiyun {
646*4882a593Smuzhiyun 	struct dm1105_dev *dev = feed_to_dm1105_dev(f);
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	if (--dev->full_ts_users == 0)
649*4882a593Smuzhiyun 		dm1105_disable_irqs(dev);
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	return 0;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun /* ir work handler */
dm1105_emit_key(struct work_struct * work)655*4882a593Smuzhiyun static void dm1105_emit_key(struct work_struct *work)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun 	struct infrared *ir = container_of(work, struct infrared, work);
658*4882a593Smuzhiyun 	u32 ircom = ir->ir_command;
659*4882a593Smuzhiyun 	u8 data;
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (ir_debug)
662*4882a593Smuzhiyun 		printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	data = (ircom >> 8) & 0x7f;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	/* FIXME: UNKNOWN because we don't generate a full NEC scancode (yet?) */
667*4882a593Smuzhiyun 	rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0);
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun /* work handler */
dm1105_dmx_buffer(struct work_struct * work)671*4882a593Smuzhiyun static void dm1105_dmx_buffer(struct work_struct *work)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work);
674*4882a593Smuzhiyun 	unsigned int nbpackets;
675*4882a593Smuzhiyun 	u32 oldwrp = dev->wrp;
676*4882a593Smuzhiyun 	u32 nextwrp = dev->nextwrp;
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	if (!((dev->ts_buf[oldwrp] == 0x47) &&
679*4882a593Smuzhiyun 			(dev->ts_buf[oldwrp + 188] == 0x47) &&
680*4882a593Smuzhiyun 			(dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {
681*4882a593Smuzhiyun 		dev->PacketErrorCount++;
682*4882a593Smuzhiyun 		/* bad packet found */
683*4882a593Smuzhiyun 		if ((dev->PacketErrorCount >= 2) &&
684*4882a593Smuzhiyun 				(dev->dmarst == 0)) {
685*4882a593Smuzhiyun 			dm_writeb(DM1105_RST, 1);
686*4882a593Smuzhiyun 			dev->wrp = 0;
687*4882a593Smuzhiyun 			dev->PacketErrorCount = 0;
688*4882a593Smuzhiyun 			dev->dmarst = 0;
689*4882a593Smuzhiyun 			return;
690*4882a593Smuzhiyun 		}
691*4882a593Smuzhiyun 	}
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun 	if (nextwrp < oldwrp) {
694*4882a593Smuzhiyun 		memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp);
695*4882a593Smuzhiyun 		nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188;
696*4882a593Smuzhiyun 	} else
697*4882a593Smuzhiyun 		nbpackets = (nextwrp - oldwrp) / 188;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	dev->wrp = nextwrp;
700*4882a593Smuzhiyun 	dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets);
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun 
dm1105_irq(int irq,void * dev_id)703*4882a593Smuzhiyun static irqreturn_t dm1105_irq(int irq, void *dev_id)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	struct dm1105_dev *dev = dev_id;
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	/* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
708*4882a593Smuzhiyun 	unsigned int intsts = dm_readb(DM1105_INTSTS);
709*4882a593Smuzhiyun 	dm_writeb(DM1105_INTSTS, intsts);
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	switch (intsts) {
712*4882a593Smuzhiyun 	case INTSTS_TSIRQ:
713*4882a593Smuzhiyun 	case (INTSTS_TSIRQ | INTSTS_IR):
714*4882a593Smuzhiyun 		dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
715*4882a593Smuzhiyun 		queue_work(dev->wq, &dev->work);
716*4882a593Smuzhiyun 		break;
717*4882a593Smuzhiyun 	case INTSTS_IR:
718*4882a593Smuzhiyun 		dev->ir.ir_command = dm_readl(DM1105_IRCODE);
719*4882a593Smuzhiyun 		schedule_work(&dev->ir.work);
720*4882a593Smuzhiyun 		break;
721*4882a593Smuzhiyun 	}
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	return IRQ_HANDLED;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun 
dm1105_ir_init(struct dm1105_dev * dm1105)726*4882a593Smuzhiyun static int dm1105_ir_init(struct dm1105_dev *dm1105)
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun 	struct rc_dev *dev;
729*4882a593Smuzhiyun 	int err = -ENOMEM;
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	dev = rc_allocate_device(RC_DRIVER_SCANCODE);
732*4882a593Smuzhiyun 	if (!dev)
733*4882a593Smuzhiyun 		return -ENOMEM;
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
736*4882a593Smuzhiyun 		"pci-%s/ir0", pci_name(dm1105->pdev));
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	dev->driver_name = MODULE_NAME;
739*4882a593Smuzhiyun 	dev->map_name = RC_MAP_DM1105_NEC;
740*4882a593Smuzhiyun 	dev->device_name = "DVB on-card IR receiver";
741*4882a593Smuzhiyun 	dev->input_phys = dm1105->ir.input_phys;
742*4882a593Smuzhiyun 	dev->input_id.bustype = BUS_PCI;
743*4882a593Smuzhiyun 	dev->input_id.version = 1;
744*4882a593Smuzhiyun 	if (dm1105->pdev->subsystem_vendor) {
745*4882a593Smuzhiyun 		dev->input_id.vendor = dm1105->pdev->subsystem_vendor;
746*4882a593Smuzhiyun 		dev->input_id.product = dm1105->pdev->subsystem_device;
747*4882a593Smuzhiyun 	} else {
748*4882a593Smuzhiyun 		dev->input_id.vendor = dm1105->pdev->vendor;
749*4882a593Smuzhiyun 		dev->input_id.product = dm1105->pdev->device;
750*4882a593Smuzhiyun 	}
751*4882a593Smuzhiyun 	dev->dev.parent = &dm1105->pdev->dev;
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	INIT_WORK(&dm1105->ir.work, dm1105_emit_key);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	err = rc_register_device(dev);
756*4882a593Smuzhiyun 	if (err < 0) {
757*4882a593Smuzhiyun 		rc_free_device(dev);
758*4882a593Smuzhiyun 		return err;
759*4882a593Smuzhiyun 	}
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	dm1105->ir.dev = dev;
762*4882a593Smuzhiyun 	return 0;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun 
dm1105_ir_exit(struct dm1105_dev * dm1105)765*4882a593Smuzhiyun static void dm1105_ir_exit(struct dm1105_dev *dm1105)
766*4882a593Smuzhiyun {
767*4882a593Smuzhiyun 	rc_unregister_device(dm1105->ir.dev);
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun 
dm1105_hw_init(struct dm1105_dev * dev)770*4882a593Smuzhiyun static int dm1105_hw_init(struct dm1105_dev *dev)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun 	dm1105_disable_irqs(dev);
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	dm_writeb(DM1105_HOST_CTR, 0);
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 	/*DATALEN 188,*/
777*4882a593Smuzhiyun 	dm_writeb(DM1105_DTALENTH, 188);
778*4882a593Smuzhiyun 	/*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
779*4882a593Smuzhiyun 	dm_writew(DM1105_TSCTR, 0xc10a);
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 	/* map DMA and set address */
782*4882a593Smuzhiyun 	dm1105_dma_map(dev);
783*4882a593Smuzhiyun 	dm1105_set_dma_addr(dev);
784*4882a593Smuzhiyun 	/* big buffer */
785*4882a593Smuzhiyun 	dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
786*4882a593Smuzhiyun 	dm_writeb(DM1105_INTCNT, 47);
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	/* IR NEC mode enable */
789*4882a593Smuzhiyun 	dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
790*4882a593Smuzhiyun 	dm_writeb(DM1105_IRMODE, 0);
791*4882a593Smuzhiyun 	dm_writew(DM1105_SYSTEMCODE, 0);
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	return 0;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun 
dm1105_hw_exit(struct dm1105_dev * dev)796*4882a593Smuzhiyun static void dm1105_hw_exit(struct dm1105_dev *dev)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun 	dm1105_disable_irqs(dev);
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	/* IR disable */
801*4882a593Smuzhiyun 	dm_writeb(DM1105_IRCTR, 0);
802*4882a593Smuzhiyun 	dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	dm1105_dma_unmap(dev);
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun static const struct stv0299_config sharp_z0194a_config = {
808*4882a593Smuzhiyun 	.demod_address = 0x68,
809*4882a593Smuzhiyun 	.inittab = sharp_z0194a_inittab,
810*4882a593Smuzhiyun 	.mclk = 88000000UL,
811*4882a593Smuzhiyun 	.invert = 1,
812*4882a593Smuzhiyun 	.skip_reinit = 0,
813*4882a593Smuzhiyun 	.lock_output = STV0299_LOCKOUTPUT_1,
814*4882a593Smuzhiyun 	.volt13_op0_op1 = STV0299_VOLT13_OP1,
815*4882a593Smuzhiyun 	.min_delay_ms = 100,
816*4882a593Smuzhiyun 	.set_symbol_rate = sharp_z0194a_set_symbol_rate,
817*4882a593Smuzhiyun };
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun static struct stv0288_config earda_config = {
820*4882a593Smuzhiyun 	.demod_address = 0x68,
821*4882a593Smuzhiyun 	.min_delay_ms = 100,
822*4882a593Smuzhiyun };
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun static struct si21xx_config serit_config = {
825*4882a593Smuzhiyun 	.demod_address = 0x68,
826*4882a593Smuzhiyun 	.min_delay_ms = 100,
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun };
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun static struct cx24116_config serit_sp2633_config = {
831*4882a593Smuzhiyun 	.demod_address = 0x55,
832*4882a593Smuzhiyun };
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun static struct ds3000_config dvbworld_ds3000_config = {
835*4882a593Smuzhiyun 	.demod_address = 0x68,
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun static struct ts2020_config dvbworld_ts2020_config  = {
839*4882a593Smuzhiyun 	.tuner_address = 0x60,
840*4882a593Smuzhiyun 	.clk_out_div = 1,
841*4882a593Smuzhiyun };
842*4882a593Smuzhiyun 
frontend_init(struct dm1105_dev * dev)843*4882a593Smuzhiyun static int frontend_init(struct dm1105_dev *dev)
844*4882a593Smuzhiyun {
845*4882a593Smuzhiyun 	int ret;
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 	switch (dev->boardnr) {
848*4882a593Smuzhiyun 	case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO:
849*4882a593Smuzhiyun 		dm1105_gpio_enable(dev, GPIO15, 1);
850*4882a593Smuzhiyun 		dm1105_gpio_clear(dev, GPIO15);
851*4882a593Smuzhiyun 		msleep(100);
852*4882a593Smuzhiyun 		dm1105_gpio_set(dev, GPIO15);
853*4882a593Smuzhiyun 		msleep(200);
854*4882a593Smuzhiyun 		dev->fe = dvb_attach(
855*4882a593Smuzhiyun 			stv0299_attach, &sharp_z0194a_config,
856*4882a593Smuzhiyun 			&dev->i2c_bb_adap);
857*4882a593Smuzhiyun 		if (dev->fe) {
858*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
859*4882a593Smuzhiyun 			dvb_attach(dvb_pll_attach, dev->fe, 0x60,
860*4882a593Smuzhiyun 					&dev->i2c_bb_adap, DVB_PLL_OPERA1);
861*4882a593Smuzhiyun 			break;
862*4882a593Smuzhiyun 		}
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 		dev->fe = dvb_attach(
865*4882a593Smuzhiyun 			stv0288_attach, &earda_config,
866*4882a593Smuzhiyun 			&dev->i2c_bb_adap);
867*4882a593Smuzhiyun 		if (dev->fe) {
868*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
869*4882a593Smuzhiyun 			dvb_attach(stb6000_attach, dev->fe, 0x61,
870*4882a593Smuzhiyun 					&dev->i2c_bb_adap);
871*4882a593Smuzhiyun 			break;
872*4882a593Smuzhiyun 		}
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 		dev->fe = dvb_attach(
875*4882a593Smuzhiyun 			si21xx_attach, &serit_config,
876*4882a593Smuzhiyun 			&dev->i2c_bb_adap);
877*4882a593Smuzhiyun 		if (dev->fe)
878*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
879*4882a593Smuzhiyun 		break;
880*4882a593Smuzhiyun 	case DM1105_BOARD_DVBWORLD_2004:
881*4882a593Smuzhiyun 		dev->fe = dvb_attach(
882*4882a593Smuzhiyun 			cx24116_attach, &serit_sp2633_config,
883*4882a593Smuzhiyun 			&dev->i2c_adap);
884*4882a593Smuzhiyun 		if (dev->fe) {
885*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
886*4882a593Smuzhiyun 			break;
887*4882a593Smuzhiyun 		}
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 		dev->fe = dvb_attach(
890*4882a593Smuzhiyun 			ds3000_attach, &dvbworld_ds3000_config,
891*4882a593Smuzhiyun 			&dev->i2c_adap);
892*4882a593Smuzhiyun 		if (dev->fe) {
893*4882a593Smuzhiyun 			dvb_attach(ts2020_attach, dev->fe,
894*4882a593Smuzhiyun 				&dvbworld_ts2020_config, &dev->i2c_adap);
895*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
896*4882a593Smuzhiyun 		}
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 		break;
899*4882a593Smuzhiyun 	case DM1105_BOARD_DVBWORLD_2002:
900*4882a593Smuzhiyun 	case DM1105_BOARD_AXESS_DM05:
901*4882a593Smuzhiyun 	default:
902*4882a593Smuzhiyun 		dev->fe = dvb_attach(
903*4882a593Smuzhiyun 			stv0299_attach, &sharp_z0194a_config,
904*4882a593Smuzhiyun 			&dev->i2c_adap);
905*4882a593Smuzhiyun 		if (dev->fe) {
906*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
907*4882a593Smuzhiyun 			dvb_attach(dvb_pll_attach, dev->fe, 0x60,
908*4882a593Smuzhiyun 					&dev->i2c_adap, DVB_PLL_OPERA1);
909*4882a593Smuzhiyun 			break;
910*4882a593Smuzhiyun 		}
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 		dev->fe = dvb_attach(
913*4882a593Smuzhiyun 			stv0288_attach, &earda_config,
914*4882a593Smuzhiyun 			&dev->i2c_adap);
915*4882a593Smuzhiyun 		if (dev->fe) {
916*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
917*4882a593Smuzhiyun 			dvb_attach(stb6000_attach, dev->fe, 0x61,
918*4882a593Smuzhiyun 					&dev->i2c_adap);
919*4882a593Smuzhiyun 			break;
920*4882a593Smuzhiyun 		}
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 		dev->fe = dvb_attach(
923*4882a593Smuzhiyun 			si21xx_attach, &serit_config,
924*4882a593Smuzhiyun 			&dev->i2c_adap);
925*4882a593Smuzhiyun 		if (dev->fe)
926*4882a593Smuzhiyun 			dev->fe->ops.set_voltage = dm1105_set_voltage;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 	}
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	if (!dev->fe) {
931*4882a593Smuzhiyun 		dev_err(&dev->pdev->dev, "could not attach frontend\n");
932*4882a593Smuzhiyun 		return -ENODEV;
933*4882a593Smuzhiyun 	}
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun 	ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe);
936*4882a593Smuzhiyun 	if (ret < 0) {
937*4882a593Smuzhiyun 		if (dev->fe->ops.release)
938*4882a593Smuzhiyun 			dev->fe->ops.release(dev->fe);
939*4882a593Smuzhiyun 		dev->fe = NULL;
940*4882a593Smuzhiyun 		return ret;
941*4882a593Smuzhiyun 	}
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	return 0;
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun 
dm1105_read_mac(struct dm1105_dev * dev,u8 * mac)946*4882a593Smuzhiyun static void dm1105_read_mac(struct dm1105_dev *dev, u8 *mac)
947*4882a593Smuzhiyun {
948*4882a593Smuzhiyun 	static u8 command[1] = { 0x28 };
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	struct i2c_msg msg[] = {
951*4882a593Smuzhiyun 		{
952*4882a593Smuzhiyun 			.addr = IIC_24C01_addr >> 1,
953*4882a593Smuzhiyun 			.flags = 0,
954*4882a593Smuzhiyun 			.buf = command,
955*4882a593Smuzhiyun 			.len = 1
956*4882a593Smuzhiyun 		}, {
957*4882a593Smuzhiyun 			.addr = IIC_24C01_addr >> 1,
958*4882a593Smuzhiyun 			.flags = I2C_M_RD,
959*4882a593Smuzhiyun 			.buf = mac,
960*4882a593Smuzhiyun 			.len = 6
961*4882a593Smuzhiyun 		},
962*4882a593Smuzhiyun 	};
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	dm1105_i2c_xfer(&dev->i2c_adap, msg , 2);
965*4882a593Smuzhiyun 	dev_info(&dev->pdev->dev, "MAC %pM\n", mac);
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun 
dm1105_probe(struct pci_dev * pdev,const struct pci_device_id * ent)968*4882a593Smuzhiyun static int dm1105_probe(struct pci_dev *pdev,
969*4882a593Smuzhiyun 				  const struct pci_device_id *ent)
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun 	struct dm1105_dev *dev;
972*4882a593Smuzhiyun 	struct dvb_adapter *dvb_adapter;
973*4882a593Smuzhiyun 	struct dvb_demux *dvbdemux;
974*4882a593Smuzhiyun 	struct dmx_demux *dmx;
975*4882a593Smuzhiyun 	int ret = -ENOMEM;
976*4882a593Smuzhiyun 	int i;
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	if (dm1105_devcount >= ARRAY_SIZE(card))
979*4882a593Smuzhiyun 		return -ENODEV;
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 	dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL);
982*4882a593Smuzhiyun 	if (!dev)
983*4882a593Smuzhiyun 		return -ENOMEM;
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	/* board config */
986*4882a593Smuzhiyun 	dev->nr = dm1105_devcount;
987*4882a593Smuzhiyun 	dev->boardnr = UNSET;
988*4882a593Smuzhiyun 	if (card[dev->nr] < ARRAY_SIZE(dm1105_boards))
989*4882a593Smuzhiyun 		dev->boardnr = card[dev->nr];
990*4882a593Smuzhiyun 	for (i = 0; UNSET == dev->boardnr &&
991*4882a593Smuzhiyun 				i < ARRAY_SIZE(dm1105_subids); i++)
992*4882a593Smuzhiyun 		if (pdev->subsystem_vendor ==
993*4882a593Smuzhiyun 			dm1105_subids[i].subvendor &&
994*4882a593Smuzhiyun 				pdev->subsystem_device ==
995*4882a593Smuzhiyun 					dm1105_subids[i].subdevice)
996*4882a593Smuzhiyun 			dev->boardnr = dm1105_subids[i].card;
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	if (UNSET == dev->boardnr) {
999*4882a593Smuzhiyun 		dev->boardnr = DM1105_BOARD_UNKNOWN;
1000*4882a593Smuzhiyun 		dm1105_card_list(pdev);
1001*4882a593Smuzhiyun 	}
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	dm1105_devcount++;
1004*4882a593Smuzhiyun 	dev->pdev = pdev;
1005*4882a593Smuzhiyun 	dev->buffer_size = 5 * DM1105_DMA_BYTES;
1006*4882a593Smuzhiyun 	dev->PacketErrorCount = 0;
1007*4882a593Smuzhiyun 	dev->dmarst = 0;
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	ret = pci_enable_device(pdev);
1010*4882a593Smuzhiyun 	if (ret < 0)
1011*4882a593Smuzhiyun 		goto err_kfree;
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1014*4882a593Smuzhiyun 	if (ret < 0)
1015*4882a593Smuzhiyun 		goto err_pci_disable_device;
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	pci_set_master(pdev);
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun 	ret = pci_request_regions(pdev, DRIVER_NAME);
1020*4882a593Smuzhiyun 	if (ret < 0)
1021*4882a593Smuzhiyun 		goto err_pci_disable_device;
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun 	dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
1024*4882a593Smuzhiyun 	if (!dev->io_mem) {
1025*4882a593Smuzhiyun 		ret = -EIO;
1026*4882a593Smuzhiyun 		goto err_pci_release_regions;
1027*4882a593Smuzhiyun 	}
1028*4882a593Smuzhiyun 
1029*4882a593Smuzhiyun 	spin_lock_init(&dev->lock);
1030*4882a593Smuzhiyun 	pci_set_drvdata(pdev, dev);
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	ret = dm1105_hw_init(dev);
1033*4882a593Smuzhiyun 	if (ret < 0)
1034*4882a593Smuzhiyun 		goto err_pci_iounmap;
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	/* i2c */
1037*4882a593Smuzhiyun 	i2c_set_adapdata(&dev->i2c_adap, dev);
1038*4882a593Smuzhiyun 	strscpy(dev->i2c_adap.name, DRIVER_NAME, sizeof(dev->i2c_adap.name));
1039*4882a593Smuzhiyun 	dev->i2c_adap.owner = THIS_MODULE;
1040*4882a593Smuzhiyun 	dev->i2c_adap.dev.parent = &pdev->dev;
1041*4882a593Smuzhiyun 	dev->i2c_adap.algo = &dm1105_algo;
1042*4882a593Smuzhiyun 	dev->i2c_adap.algo_data = dev;
1043*4882a593Smuzhiyun 	ret = i2c_add_adapter(&dev->i2c_adap);
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun 	if (ret < 0)
1046*4882a593Smuzhiyun 		goto err_dm1105_hw_exit;
1047*4882a593Smuzhiyun 
1048*4882a593Smuzhiyun 	i2c_set_adapdata(&dev->i2c_bb_adap, dev);
1049*4882a593Smuzhiyun 	strscpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME,
1050*4882a593Smuzhiyun 		sizeof(dev->i2c_bb_adap.name));
1051*4882a593Smuzhiyun 	dev->i2c_bb_adap.owner = THIS_MODULE;
1052*4882a593Smuzhiyun 	dev->i2c_bb_adap.dev.parent = &pdev->dev;
1053*4882a593Smuzhiyun 	dev->i2c_bb_adap.algo_data = &dev->i2c_bit;
1054*4882a593Smuzhiyun 	dev->i2c_bit.data = dev;
1055*4882a593Smuzhiyun 	dev->i2c_bit.setsda = dm1105_setsda;
1056*4882a593Smuzhiyun 	dev->i2c_bit.setscl = dm1105_setscl;
1057*4882a593Smuzhiyun 	dev->i2c_bit.getsda = dm1105_getsda;
1058*4882a593Smuzhiyun 	dev->i2c_bit.getscl = dm1105_getscl;
1059*4882a593Smuzhiyun 	dev->i2c_bit.udelay = 10;
1060*4882a593Smuzhiyun 	dev->i2c_bit.timeout = 10;
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 	/* Raise SCL and SDA */
1063*4882a593Smuzhiyun 	dm1105_setsda(dev, 1);
1064*4882a593Smuzhiyun 	dm1105_setscl(dev, 1);
1065*4882a593Smuzhiyun 
1066*4882a593Smuzhiyun 	ret = i2c_bit_add_bus(&dev->i2c_bb_adap);
1067*4882a593Smuzhiyun 	if (ret < 0)
1068*4882a593Smuzhiyun 		goto err_i2c_del_adapter;
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	/* dvb */
1071*4882a593Smuzhiyun 	ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME,
1072*4882a593Smuzhiyun 					THIS_MODULE, &pdev->dev, adapter_nr);
1073*4882a593Smuzhiyun 	if (ret < 0)
1074*4882a593Smuzhiyun 		goto err_i2c_del_adapters;
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	dvb_adapter = &dev->dvb_adapter;
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	dm1105_read_mac(dev, dvb_adapter->proposed_mac);
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 	dvbdemux = &dev->demux;
1081*4882a593Smuzhiyun 	dvbdemux->filternum = 256;
1082*4882a593Smuzhiyun 	dvbdemux->feednum = 256;
1083*4882a593Smuzhiyun 	dvbdemux->start_feed = dm1105_start_feed;
1084*4882a593Smuzhiyun 	dvbdemux->stop_feed = dm1105_stop_feed;
1085*4882a593Smuzhiyun 	dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1086*4882a593Smuzhiyun 			DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
1087*4882a593Smuzhiyun 	ret = dvb_dmx_init(dvbdemux);
1088*4882a593Smuzhiyun 	if (ret < 0)
1089*4882a593Smuzhiyun 		goto err_dvb_unregister_adapter;
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	dmx = &dvbdemux->dmx;
1092*4882a593Smuzhiyun 	dev->dmxdev.filternum = 256;
1093*4882a593Smuzhiyun 	dev->dmxdev.demux = dmx;
1094*4882a593Smuzhiyun 	dev->dmxdev.capabilities = 0;
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter);
1097*4882a593Smuzhiyun 	if (ret < 0)
1098*4882a593Smuzhiyun 		goto err_dvb_dmx_release;
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	dev->hw_frontend.source = DMX_FRONTEND_0;
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	ret = dmx->add_frontend(dmx, &dev->hw_frontend);
1103*4882a593Smuzhiyun 	if (ret < 0)
1104*4882a593Smuzhiyun 		goto err_dvb_dmxdev_release;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	dev->mem_frontend.source = DMX_MEMORY_FE;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	ret = dmx->add_frontend(dmx, &dev->mem_frontend);
1109*4882a593Smuzhiyun 	if (ret < 0)
1110*4882a593Smuzhiyun 		goto err_remove_hw_frontend;
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	ret = dmx->connect_frontend(dmx, &dev->hw_frontend);
1113*4882a593Smuzhiyun 	if (ret < 0)
1114*4882a593Smuzhiyun 		goto err_remove_mem_frontend;
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx);
1117*4882a593Smuzhiyun 	if (ret < 0)
1118*4882a593Smuzhiyun 		goto err_disconnect_frontend;
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	ret = frontend_init(dev);
1121*4882a593Smuzhiyun 	if (ret < 0)
1122*4882a593Smuzhiyun 		goto err_dvb_net;
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	dm1105_ir_init(dev);
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	INIT_WORK(&dev->work, dm1105_dmx_buffer);
1127*4882a593Smuzhiyun 	sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
1128*4882a593Smuzhiyun 	dev->wq = create_singlethread_workqueue(dev->wqn);
1129*4882a593Smuzhiyun 	if (!dev->wq) {
1130*4882a593Smuzhiyun 		ret = -ENOMEM;
1131*4882a593Smuzhiyun 		goto err_dvb_net;
1132*4882a593Smuzhiyun 	}
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED,
1135*4882a593Smuzhiyun 						DRIVER_NAME, dev);
1136*4882a593Smuzhiyun 	if (ret < 0)
1137*4882a593Smuzhiyun 		goto err_workqueue;
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	return 0;
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun err_workqueue:
1142*4882a593Smuzhiyun 	destroy_workqueue(dev->wq);
1143*4882a593Smuzhiyun err_dvb_net:
1144*4882a593Smuzhiyun 	dvb_net_release(&dev->dvbnet);
1145*4882a593Smuzhiyun err_disconnect_frontend:
1146*4882a593Smuzhiyun 	dmx->disconnect_frontend(dmx);
1147*4882a593Smuzhiyun err_remove_mem_frontend:
1148*4882a593Smuzhiyun 	dmx->remove_frontend(dmx, &dev->mem_frontend);
1149*4882a593Smuzhiyun err_remove_hw_frontend:
1150*4882a593Smuzhiyun 	dmx->remove_frontend(dmx, &dev->hw_frontend);
1151*4882a593Smuzhiyun err_dvb_dmxdev_release:
1152*4882a593Smuzhiyun 	dvb_dmxdev_release(&dev->dmxdev);
1153*4882a593Smuzhiyun err_dvb_dmx_release:
1154*4882a593Smuzhiyun 	dvb_dmx_release(dvbdemux);
1155*4882a593Smuzhiyun err_dvb_unregister_adapter:
1156*4882a593Smuzhiyun 	dvb_unregister_adapter(dvb_adapter);
1157*4882a593Smuzhiyun err_i2c_del_adapters:
1158*4882a593Smuzhiyun 	i2c_del_adapter(&dev->i2c_bb_adap);
1159*4882a593Smuzhiyun err_i2c_del_adapter:
1160*4882a593Smuzhiyun 	i2c_del_adapter(&dev->i2c_adap);
1161*4882a593Smuzhiyun err_dm1105_hw_exit:
1162*4882a593Smuzhiyun 	dm1105_hw_exit(dev);
1163*4882a593Smuzhiyun err_pci_iounmap:
1164*4882a593Smuzhiyun 	pci_iounmap(pdev, dev->io_mem);
1165*4882a593Smuzhiyun err_pci_release_regions:
1166*4882a593Smuzhiyun 	pci_release_regions(pdev);
1167*4882a593Smuzhiyun err_pci_disable_device:
1168*4882a593Smuzhiyun 	pci_disable_device(pdev);
1169*4882a593Smuzhiyun err_kfree:
1170*4882a593Smuzhiyun 	kfree(dev);
1171*4882a593Smuzhiyun 	return ret;
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun 
dm1105_remove(struct pci_dev * pdev)1174*4882a593Smuzhiyun static void dm1105_remove(struct pci_dev *pdev)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun 	struct dm1105_dev *dev = pci_get_drvdata(pdev);
1177*4882a593Smuzhiyun 	struct dvb_adapter *dvb_adapter = &dev->dvb_adapter;
1178*4882a593Smuzhiyun 	struct dvb_demux *dvbdemux = &dev->demux;
1179*4882a593Smuzhiyun 	struct dmx_demux *dmx = &dvbdemux->dmx;
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	dm1105_ir_exit(dev);
1182*4882a593Smuzhiyun 	dmx->close(dmx);
1183*4882a593Smuzhiyun 	dvb_net_release(&dev->dvbnet);
1184*4882a593Smuzhiyun 	if (dev->fe)
1185*4882a593Smuzhiyun 		dvb_unregister_frontend(dev->fe);
1186*4882a593Smuzhiyun 
1187*4882a593Smuzhiyun 	dmx->disconnect_frontend(dmx);
1188*4882a593Smuzhiyun 	dmx->remove_frontend(dmx, &dev->mem_frontend);
1189*4882a593Smuzhiyun 	dmx->remove_frontend(dmx, &dev->hw_frontend);
1190*4882a593Smuzhiyun 	dvb_dmxdev_release(&dev->dmxdev);
1191*4882a593Smuzhiyun 	dvb_dmx_release(dvbdemux);
1192*4882a593Smuzhiyun 	dvb_unregister_adapter(dvb_adapter);
1193*4882a593Smuzhiyun 	i2c_del_adapter(&dev->i2c_adap);
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 	dm1105_hw_exit(dev);
1196*4882a593Smuzhiyun 	free_irq(pdev->irq, dev);
1197*4882a593Smuzhiyun 	pci_iounmap(pdev, dev->io_mem);
1198*4882a593Smuzhiyun 	pci_release_regions(pdev);
1199*4882a593Smuzhiyun 	pci_disable_device(pdev);
1200*4882a593Smuzhiyun 	dm1105_devcount--;
1201*4882a593Smuzhiyun 	kfree(dev);
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun static const struct pci_device_id dm1105_id_table[] = {
1205*4882a593Smuzhiyun 	{
1206*4882a593Smuzhiyun 		.vendor = PCI_VENDOR_ID_TRIGEM,
1207*4882a593Smuzhiyun 		.device = PCI_DEVICE_ID_DM1105,
1208*4882a593Smuzhiyun 		.subvendor = PCI_ANY_ID,
1209*4882a593Smuzhiyun 		.subdevice = PCI_ANY_ID,
1210*4882a593Smuzhiyun 	}, {
1211*4882a593Smuzhiyun 		.vendor = PCI_VENDOR_ID_AXESS,
1212*4882a593Smuzhiyun 		.device = PCI_DEVICE_ID_DM05,
1213*4882a593Smuzhiyun 		.subvendor = PCI_ANY_ID,
1214*4882a593Smuzhiyun 		.subdevice = PCI_ANY_ID,
1215*4882a593Smuzhiyun 	}, {
1216*4882a593Smuzhiyun 		/* empty */
1217*4882a593Smuzhiyun 	},
1218*4882a593Smuzhiyun };
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, dm1105_id_table);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun static struct pci_driver dm1105_driver = {
1223*4882a593Smuzhiyun 	.name = DRIVER_NAME,
1224*4882a593Smuzhiyun 	.id_table = dm1105_id_table,
1225*4882a593Smuzhiyun 	.probe = dm1105_probe,
1226*4882a593Smuzhiyun 	.remove = dm1105_remove,
1227*4882a593Smuzhiyun };
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun module_pci_driver(dm1105_driver);
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>");
1232*4882a593Smuzhiyun MODULE_DESCRIPTION("SDMC DM1105 DVB driver");
1233*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1234